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-- Title          : Wishbone slave core for Pulse counter registers
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-- File           : pulse_cnt_wb.vhd
-- Author         : auto-generated by wbgen2 from pulse_cnt_wb.wb
-- Created        : Mon Nov  3 09:56:02 2014
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pulse_cnt_wb is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1OCR'
    pulse_cnt_ttlch1o_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch1o_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch1o_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH1ICR'
    pulse_cnt_ttlch1i_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch1i_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch1i_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2OCR'
    pulse_cnt_ttlch2o_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch2o_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch2o_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH2ICR'
    pulse_cnt_ttlch2i_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch2i_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch2i_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3OCR'
    pulse_cnt_ttlch3o_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch3o_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch3o_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH3ICR'
    pulse_cnt_ttlch3i_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch3i_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch3i_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4OCR'
    pulse_cnt_ttlch4o_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch4o_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch4o_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH4ICR'
    pulse_cnt_ttlch4i_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch4i_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch4i_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5OCR'
    pulse_cnt_ttlch5o_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch5o_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch5o_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH5ICR'
    pulse_cnt_ttlch5i_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch5i_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch5i_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6OCR'
    pulse_cnt_ttlch6o_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch6o_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch6o_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'TTLCH6ICR'
    pulse_cnt_ttlch6i_o                      : out    std_logic_vector(31 downto 0);
    pulse_cnt_ttlch6i_i                      : in     std_logic_vector(31 downto 0);
    pulse_cnt_ttlch6i_load_o                 : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAOCR'
    pulse_cnt_invttlchao_o                   : out    std_logic_vector(31 downto 0);
    pulse_cnt_invttlchao_i                   : in     std_logic_vector(31 downto 0);
    pulse_cnt_invttlchao_load_o              : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHAICR'
    pulse_cnt_invttlchai_o                   : out    std_logic_vector(31 downto 0);
    pulse_cnt_invttlchai_i                   : in     std_logic_vector(31 downto 0);
    pulse_cnt_invttlchai_load_o              : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBOCR'
    pulse_cnt_invttlchbo_o                   : out    std_logic_vector(31 downto 0);
    pulse_cnt_invttlchbo_i                   : in     std_logic_vector(31 downto 0);
    pulse_cnt_invttlchbo_load_o              : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHBICR'
    pulse_cnt_invttlchbi_o                   : out    std_logic_vector(31 downto 0);
    pulse_cnt_invttlchbi_i                   : in     std_logic_vector(31 downto 0);
    pulse_cnt_invttlchbi_load_o              : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCOCR'
    pulse_cnt_invttlchco_o                   : out    std_logic_vector(31 downto 0);
    pulse_cnt_invttlchco_i                   : in     std_logic_vector(31 downto 0);
    pulse_cnt_invttlchco_load_o              : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHCICR'
    pulse_cnt_invttlchci_o                   : out    std_logic_vector(31 downto 0);
    pulse_cnt_invttlchci_i                   : in     std_logic_vector(31 downto 0);
    pulse_cnt_invttlchci_load_o              : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDOCR'
    pulse_cnt_invttlchdo_o                   : out    std_logic_vector(31 downto 0);
    pulse_cnt_invttlchdo_i                   : in     std_logic_vector(31 downto 0);
    pulse_cnt_invttlchdo_load_o              : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'INVTTLCHDICR'
    pulse_cnt_invttlchdi_o                   : out    std_logic_vector(31 downto 0);
    pulse_cnt_invttlchdi_i                   : in     std_logic_vector(31 downto 0);
    pulse_cnt_invttlchdi_load_o              : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1OCR'
    pulse_cnt_rearch1o_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch1o_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch1o_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH1ICR'
    pulse_cnt_rearch1i_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch1i_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch1i_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2OCR'
    pulse_cnt_rearch2o_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch2o_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch2o_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH2ICR'
    pulse_cnt_rearch2i_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch2i_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch2i_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3OCR'
    pulse_cnt_rearch3o_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch3o_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch3o_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH3ICR'
    pulse_cnt_rearch3i_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch3i_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch3i_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4OCR'
    pulse_cnt_rearch4o_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch4o_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch4o_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH4ICR'
    pulse_cnt_rearch4i_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch4i_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch4i_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5OCR'
    pulse_cnt_rearch5o_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch5o_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch5o_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH5ICR'
    pulse_cnt_rearch5i_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch5i_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch5i_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6OCR'
    pulse_cnt_rearch6o_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch6o_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch6o_load_o                : out    std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'REARCH6ICR'
    pulse_cnt_rearch6i_o                     : out    std_logic_vector(31 downto 0);
    pulse_cnt_rearch6i_i                     : in     std_logic_vector(31 downto 0);
    pulse_cnt_rearch6i_load_o                : out    std_logic
  );
end pulse_cnt_wb;

architecture syn of pulse_cnt_wb is

signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(4 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      pulse_cnt_ttlch1o_load_o <= '0';
      pulse_cnt_ttlch1i_load_o <= '0';
      pulse_cnt_ttlch2o_load_o <= '0';
      pulse_cnt_ttlch2i_load_o <= '0';
      pulse_cnt_ttlch3o_load_o <= '0';
      pulse_cnt_ttlch3i_load_o <= '0';
      pulse_cnt_ttlch4o_load_o <= '0';
      pulse_cnt_ttlch4i_load_o <= '0';
      pulse_cnt_ttlch5o_load_o <= '0';
      pulse_cnt_ttlch5i_load_o <= '0';
      pulse_cnt_ttlch6o_load_o <= '0';
      pulse_cnt_ttlch6i_load_o <= '0';
      pulse_cnt_invttlchao_load_o <= '0';
      pulse_cnt_invttlchai_load_o <= '0';
      pulse_cnt_invttlchbo_load_o <= '0';
      pulse_cnt_invttlchbi_load_o <= '0';
      pulse_cnt_invttlchco_load_o <= '0';
      pulse_cnt_invttlchci_load_o <= '0';
      pulse_cnt_invttlchdo_load_o <= '0';
      pulse_cnt_invttlchdi_load_o <= '0';
      pulse_cnt_rearch1o_load_o <= '0';
      pulse_cnt_rearch1i_load_o <= '0';
      pulse_cnt_rearch2o_load_o <= '0';
      pulse_cnt_rearch2i_load_o <= '0';
      pulse_cnt_rearch3o_load_o <= '0';
      pulse_cnt_rearch3i_load_o <= '0';
      pulse_cnt_rearch4o_load_o <= '0';
      pulse_cnt_rearch4i_load_o <= '0';
      pulse_cnt_rearch5o_load_o <= '0';
      pulse_cnt_rearch5i_load_o <= '0';
      pulse_cnt_rearch6o_load_o <= '0';
      pulse_cnt_rearch6i_load_o <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          pulse_cnt_ttlch1o_load_o <= '0';
          pulse_cnt_ttlch1i_load_o <= '0';
          pulse_cnt_ttlch2o_load_o <= '0';
          pulse_cnt_ttlch2i_load_o <= '0';
          pulse_cnt_ttlch3o_load_o <= '0';
          pulse_cnt_ttlch3i_load_o <= '0';
          pulse_cnt_ttlch4o_load_o <= '0';
          pulse_cnt_ttlch4i_load_o <= '0';
          pulse_cnt_ttlch5o_load_o <= '0';
          pulse_cnt_ttlch5i_load_o <= '0';
          pulse_cnt_ttlch6o_load_o <= '0';
          pulse_cnt_ttlch6i_load_o <= '0';
          pulse_cnt_invttlchao_load_o <= '0';
          pulse_cnt_invttlchai_load_o <= '0';
          pulse_cnt_invttlchbo_load_o <= '0';
          pulse_cnt_invttlchbi_load_o <= '0';
          pulse_cnt_invttlchco_load_o <= '0';
          pulse_cnt_invttlchci_load_o <= '0';
          pulse_cnt_invttlchdo_load_o <= '0';
          pulse_cnt_invttlchdi_load_o <= '0';
          pulse_cnt_rearch1o_load_o <= '0';
          pulse_cnt_rearch1i_load_o <= '0';
          pulse_cnt_rearch2o_load_o <= '0';
          pulse_cnt_rearch2i_load_o <= '0';
          pulse_cnt_rearch3o_load_o <= '0';
          pulse_cnt_rearch3i_load_o <= '0';
          pulse_cnt_rearch4o_load_o <= '0';
          pulse_cnt_rearch4i_load_o <= '0';
          pulse_cnt_rearch5o_load_o <= '0';
          pulse_cnt_rearch5i_load_o <= '0';
          pulse_cnt_rearch6o_load_o <= '0';
          pulse_cnt_rearch6i_load_o <= '0';
          ack_in_progress <= '0';
        else
          pulse_cnt_ttlch1o_load_o <= '0';
          pulse_cnt_ttlch1i_load_o <= '0';
          pulse_cnt_ttlch2o_load_o <= '0';
          pulse_cnt_ttlch2i_load_o <= '0';
          pulse_cnt_ttlch3o_load_o <= '0';
          pulse_cnt_ttlch3i_load_o <= '0';
          pulse_cnt_ttlch4o_load_o <= '0';
          pulse_cnt_ttlch4i_load_o <= '0';
          pulse_cnt_ttlch5o_load_o <= '0';
          pulse_cnt_ttlch5i_load_o <= '0';
          pulse_cnt_ttlch6o_load_o <= '0';
          pulse_cnt_ttlch6i_load_o <= '0';
          pulse_cnt_invttlchao_load_o <= '0';
          pulse_cnt_invttlchai_load_o <= '0';
          pulse_cnt_invttlchbo_load_o <= '0';
          pulse_cnt_invttlchbi_load_o <= '0';
          pulse_cnt_invttlchco_load_o <= '0';
          pulse_cnt_invttlchci_load_o <= '0';
          pulse_cnt_invttlchdo_load_o <= '0';
          pulse_cnt_invttlchdi_load_o <= '0';
          pulse_cnt_rearch1o_load_o <= '0';
          pulse_cnt_rearch1i_load_o <= '0';
          pulse_cnt_rearch2o_load_o <= '0';
          pulse_cnt_rearch2i_load_o <= '0';
          pulse_cnt_rearch3o_load_o <= '0';
          pulse_cnt_rearch3i_load_o <= '0';
          pulse_cnt_rearch4o_load_o <= '0';
          pulse_cnt_rearch4i_load_o <= '0';
          pulse_cnt_rearch5o_load_o <= '0';
          pulse_cnt_rearch5i_load_o <= '0';
          pulse_cnt_rearch6o_load_o <= '0';
          pulse_cnt_rearch6i_load_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(4 downto 0) is
          when "00000" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch1o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch1o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch1i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch1i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch2o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch2o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch2i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch2i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch3o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch3o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch3i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch3i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch4o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch4o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch4i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch4i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch5o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch5o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch5i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch5i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch6o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch6o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011" => 
            if (wb_we_i = '1') then
              pulse_cnt_ttlch6i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_ttlch6i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100" => 
            if (wb_we_i = '1') then
              pulse_cnt_invttlchao_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_invttlchao_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101" => 
            if (wb_we_i = '1') then
              pulse_cnt_invttlchai_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_invttlchai_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110" => 
            if (wb_we_i = '1') then
              pulse_cnt_invttlchbo_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_invttlchbo_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111" => 
            if (wb_we_i = '1') then
              pulse_cnt_invttlchbi_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_invttlchbi_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000" => 
            if (wb_we_i = '1') then
              pulse_cnt_invttlchco_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_invttlchco_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001" => 
            if (wb_we_i = '1') then
              pulse_cnt_invttlchci_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_invttlchci_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010" => 
            if (wb_we_i = '1') then
              pulse_cnt_invttlchdo_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_invttlchdo_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10011" => 
            if (wb_we_i = '1') then
              pulse_cnt_invttlchdi_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_invttlchdi_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10100" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch1o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch1o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10101" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch1i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch1i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10110" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch2o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch2o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10111" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch2i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch2i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11000" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch3o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch3o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11001" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch3i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch3i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11010" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch4o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch4o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11011" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch4i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch4i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11100" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch5o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch5o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11101" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch5i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch5i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11110" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch6o_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch6o_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11111" => 
            if (wb_we_i = '1') then
              pulse_cnt_rearch6i_load_o <= '1';
            end if;
            rddata_reg(31 downto 0) <= pulse_cnt_rearch6i_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- Pulse counter value
  pulse_cnt_ttlch1o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch1i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch2o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch2i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch3o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch3i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch4o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch4i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch5o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch5i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch6o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_ttlch6i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_invttlchao_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_invttlchai_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_invttlchbo_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_invttlchbi_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_invttlchco_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_invttlchci_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_invttlchdo_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_invttlchdi_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch1o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch1i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch2o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch2i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch3o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch3i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch4o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch4i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch5o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch5i_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch6o_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
  pulse_cnt_rearch6i_o <= wrdata_reg(31 downto 0);
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
