Commit c06a85ea authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

modified pts registers to add pcb version number register to memory map

parent 987fa158
This diff is collapsed.
This diff is collapsed.
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : pts_regs.vhd -- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb -- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Thu Dec 4 10:03:35 2014 -- Created : 10/27/17 10:47:57
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
...@@ -18,7 +18,7 @@ entity pts_regs is ...@@ -18,7 +18,7 @@ entity pts_regs is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0); wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
...@@ -51,13 +51,13 @@ entity pts_regs is ...@@ -51,13 +51,13 @@ entity pts_regs is
pts_csr_rst_unlock_o : out std_logic; pts_csr_rst_unlock_o : out std_logic;
pts_csr_rst_unlock_i : in std_logic; pts_csr_rst_unlock_i : in std_logic;
pts_csr_rst_unlock_load_o : out std_logic; pts_csr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CSR' -- Ports for BIT field: 'Reset bit -- active only if RST_UNLOCK is 1' in reg: 'CSR'
pts_csr_rst_o : out std_logic; pts_csr_rst_o : out std_logic;
pts_csr_rst_i : in std_logic; pts_csr_rst_i : in std_logic;
pts_csr_rst_load_o : out std_logic; pts_csr_rst_load_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR' -- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i : in std_logic_vector(7 downto 0); pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'CSR' -- Port for std_logic_vector field: 'RTM detection lines' in reg: 'CSR'
pts_csr_rtm_i : in std_logic_vector(5 downto 0); pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR' -- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o : out std_logic; pts_csr_i2c_err_o : out std_logic;
...@@ -82,7 +82,9 @@ entity pts_regs is ...@@ -82,7 +82,9 @@ entity pts_regs is
-- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER' -- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER'
pts_ter_iterm_o : out std_logic_vector(5 downto 0); pts_ter_iterm_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER' -- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
pts_ter_oterm_o : out std_logic_vector(5 downto 0) pts_ter_oterm_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'PCB version number' in reg: 'HWVERS'
pts_hwvr_hwvers_i : in std_logic_vector(5 downto 0)
); );
end pts_regs; end pts_regs;
...@@ -103,7 +105,7 @@ signal ack_sreg : std_logic_vector(9 downto 0); ...@@ -103,7 +105,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0); signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0); signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ; signal ack_in_progress : std_logic ;
signal wr_int : std_logic ; signal wr_int : std_logic ;
signal rd_int : std_logic ; signal rd_int : std_logic ;
...@@ -160,14 +162,14 @@ begin ...@@ -160,14 +162,14 @@ begin
end if; end if;
else else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is case rwaddr_reg(2 downto 0) is
when "00" => when "000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(31 downto 0) <= pts_bidr_i; rddata_reg(31 downto 0) <= pts_bidr_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01" => when "001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
pts_csr_chledt_int <= wrdata_reg(0); pts_csr_chledt_int <= wrdata_reg(0);
pts_csr_stledt_int <= wrdata_reg(1); pts_csr_stledt_int <= wrdata_reg(1);
...@@ -205,7 +207,7 @@ begin ...@@ -205,7 +207,7 @@ begin
rddata_reg(13) <= 'X'; rddata_reg(13) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10" => when "010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(5 downto 0) <= pts_lsr_front_i; rddata_reg(5 downto 0) <= pts_lsr_front_i;
...@@ -216,7 +218,7 @@ begin ...@@ -216,7 +218,7 @@ begin
rddata_reg(31 downto 26) <= pts_lsr_rearfs_i; rddata_reg(31 downto 26) <= pts_lsr_rearfs_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11" => when "011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
pts_ter_iterm_int <= wrdata_reg(5 downto 0); pts_ter_iterm_int <= wrdata_reg(5 downto 0);
pts_ter_oterm_int <= wrdata_reg(11 downto 6); pts_ter_oterm_int <= wrdata_reg(11 downto 6);
...@@ -245,6 +247,38 @@ begin ...@@ -245,6 +247,38 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(5 downto 0) <= pts_hwvr_hwvers_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others => when others =>
-- prevent the slave from hanging the bus on invalid address -- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1'; ack_in_progress <= '1';
...@@ -279,10 +313,10 @@ begin ...@@ -279,10 +313,10 @@ begin
pts_csr_tstcs1_o <= pts_csr_tstcs1_int; pts_csr_tstcs1_o <= pts_csr_tstcs1_int;
-- Reset unlock bit -- Reset unlock bit
pts_csr_rst_unlock_o <= wrdata_reg(14); pts_csr_rst_unlock_o <= wrdata_reg(14);
-- Reset bit -- Reset bit -- active only if RST_UNLOCK is 1
pts_csr_rst_o <= wrdata_reg(15); pts_csr_rst_o <= wrdata_reg(15);
-- switches -- switches
-- RTM -- RTM detection lines
-- I2C communication error -- I2C communication error
pts_csr_i2c_err_o <= wrdata_reg(30); pts_csr_i2c_err_o <= wrdata_reg(30);
-- I2C communication watchdog timeout error -- I2C communication watchdog timeout error
...@@ -297,6 +331,7 @@ begin ...@@ -297,6 +331,7 @@ begin
pts_ter_iterm_o <= pts_ter_iterm_int; pts_ter_iterm_o <= pts_ter_iterm_int;
-- Output termination enable -- Output termination enable
pts_ter_oterm_o <= pts_ter_oterm_int; pts_ter_oterm_o <= pts_ter_oterm_int;
-- PCB version number
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
......
...@@ -328,5 +328,24 @@ peripheral { ...@@ -328,5 +328,24 @@ peripheral {
access_bus = READ_WRITE; access_bus = READ_WRITE;
}; };
}; };
reg {
name = "HWVERS";
description = "Hardware version register";
prefix = "hwvr";
field {
name = "PCB version number";
description = "6 bits representing HW/PCB version number \
4 MSB represent HW version number \
2 LSB represent number of execution \
Eg: value 010010 represents PCB version 4.2";
prefix = "hwvers";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
}; };
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