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Conv TTL RS485 - Testing
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Conv TTL RS485 - Testing
Commits
e4071273
Commit
e4071273
authored
Sep 21, 2018
by
Denia Bouhired-Ferrag
Browse files
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Plain Diff
Updated links to new pts bitstream and new release and golden gateware
parent
c3205308
Hide whitespace changes
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Side-by-side
Showing
7 changed files
with
98 additions
and
139 deletions
+98
-139
pts_regs.vhd
hdl/modules/pts_regs.vhd
+11
-48
pts_regs.wb
hdl/modules/pts_regs.wb
+5
-10
pts.xise
hdl/syn/pts.xise
+3
-2
pts.vhd
hdl/top/pts.vhd
+75
-75
Makefile
pts-fm/Makefile
+2
-2
flash
pts-fm/shell/flash
+1
-1
program
pts-fm/shell/program
+1
-1
No files found.
hdl/modules/pts_regs.vhd
View file @
e4071273
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created :
10/27/17 10:47:57
-- Created :
01/26/18 11:51:31
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
...
...
@@ -18,7 +18,7 @@ entity pts_regs is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
...
...
@@ -83,8 +83,8 @@ entity pts_regs is
pts_ter_iterm_o
:
out
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
pts_ter_oterm_o
:
out
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'PCB version number' in reg: '
HWVERS
'
pts_
hwvr_hwvers_i
:
in
std_logic_vector
(
5
downto
0
)
-- Port for std_logic_vector field: 'PCB version number' in reg: '
TER
'
pts_
ter_hwvers_i
:
in
std_logic_vector
(
5
downto
0
)
);
end
pts_regs
;
...
...
@@ -105,7 +105,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
2
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
...
...
@@ -162,14 +162,14 @@ begin
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
2
downto
0
)
is
when
"00
0
"
=>
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
pts_bidr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0
0
1"
=>
when
"01"
=>
if
(
wb_we_i
=
'1'
)
then
pts_csr_chledt_int
<=
wrdata_reg
(
0
);
pts_csr_stledt_int
<=
wrdata_reg
(
1
);
...
...
@@ -207,7 +207,7 @@ begin
rddata_reg
(
13
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"
0
10"
=>
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
5
downto
0
)
<=
pts_lsr_front_i
;
...
...
@@ -218,55 +218,18 @@ begin
rddata_reg
(
31
downto
26
)
<=
pts_lsr_rearfs_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"
0
11"
=>
when
"11"
=>
if
(
wb_we_i
=
'1'
)
then
pts_ter_iterm_int
<=
wrdata_reg
(
5
downto
0
);
pts_ter_oterm_int
<=
wrdata_reg
(
11
downto
6
);
end
if
;
rddata_reg
(
5
downto
0
)
<=
pts_ter_iterm_int
;
rddata_reg
(
11
downto
6
)
<=
pts_ter_oterm_int
;
rddata_reg
(
21
downto
16
)
<=
pts_ter_hwvers_i
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
5
downto
0
)
<=
pts_hwvr_hwvers_i
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
...
...
hdl/modules/pts_regs.wb
View file @
e4071273
...
...
@@ -327,25 +327,20 @@ peripheral {
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "HWVERS";
description = "Hardware version register";
prefix = "hwvr";
field {
field {
name = "PCB version number";
description = "6 bits representing HW/PCB version number \
4 MSB represent HW version number \
2 LSB represent number of execution \
Eg: value 010010 represents PCB version 4.2";
prefix = "hwvers";
align = 16;
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
};
};
hdl/syn/pts.xise
View file @
e4071273
...
...
@@ -36,7 +36,7 @@
<property
xil_pn:name=
"Analysis Effort Level"
xil_pn:value=
"Standard"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Asynchronous To Synchronous"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Auto Implementation Compile Order"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Auto Implementation Top"
xil_pn:value=
"
false"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Auto Implementation Top"
xil_pn:value=
"
true"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Automatic BRAM Packing"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Automatically Insert glbl Module in the Netlist"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Automatically Run Generate Target PROM/ACE File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -59,7 +59,7 @@
<property
xil_pn:name=
"Configuration Rate spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Correlate Output to Input Design"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create ASCII Configuration File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Create Bit File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create I/O Pads from Ports"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create IEEE 1532 Configuration File spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -93,6 +93,7 @@
<property
xil_pn:name=
"Equivalent Register Removal Map"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Equivalent Register Removal XST"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Essential Bits"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Evaluation Development Board"
xil_pn:value=
"None Specified"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of Deprecated EDK Cores"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of EDK Sub-Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Extra Cost Tables Map"
xil_pn:value=
"0"
xil_pn:valueState=
"default"
/>
...
...
hdl/top/pts.vhd
View file @
e4071273
...
...
@@ -148,10 +148,10 @@ entity pts is
sw_gp_n_i
:
in
std_logic_vector
(
7
downto
0
);
sw_multicast_n_i
:
in
std_logic_vector
(
3
downto
0
);
-- PCB version recognition
pcbrev_i
:
in
std_logic_vector
(
5
downto
0
);
pcbrev_i
:
in
std_logic_vector
(
5
downto
0
);
-- RTM lines
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
-- Front panel bicolor LEDs
led_ctrl0_o
:
out
std_logic
;
...
...
@@ -268,76 +268,76 @@ architecture arch of pts is
--============================================================================
-- Regs to test I2C operation
component
pts_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
pts_bidr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for BIT field: 'Front
pulse LED enable' in reg: 'CSR'
pts_csr_chledt_o
:
out
std_logic
;
-- Port for BIT field: 'Status LED enable' in reg: 'CSR'
pts_csr_stledt_o
:
out
std_logic
;
-- Port for BIT field: 'Rear pulse LED enabl
e' in reg: 'CSR'
pts_csr_rledt_o
:
out
std_logic
;
-- Port for BIT field: 'TTL test enable' in reg: 'CSR'
pts_csr_ttlpt_o
:
out
std_logic
;
-- Port for BIT field: 'RS485
pulse enable' in reg: 'CSR'
pts_csr_rearpt_o
:
out
std_logic
;
-- Port for BIT field: 'RS485 tester card VCC' in reg: 'CSR'
pts_csr_tstcvcc_o
:
out
std_logic
;
-- Port for BIT field: 'RS485 tester card MUX enable' in reg: 'CSR'
pts_csr_tstcmuxen_o
:
out
std_logic
;
-- Port for BIT field: 'RS485 tester card MUX S0 line' in reg: 'CSR'
pts_csr_tstcs0_o
:
out
std_logic
;
-- Port for BIT field: 'RS485 tester card MUX S1 line' in reg: 'CSR'
pts_csr_tstcs1_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o
:
out
std_logic
;
pts_csr_rst_unlock_i
:
in
std_logic
;
pts_csr_rst_unlock_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset bit
' in reg: 'CSR'
pts_csr_rst_o
:
out
std_logic
;
pts_csr_rst_i
:
in
std_logic
;
pts_csr_rst_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM
' in reg: 'CSR'
pts_csr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o
:
out
std_logic
;
pts_csr_i2c_err_i
:
in
std_logic
;
pts_csr_i2c_err_load_o
:
out
std_logic
;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'CSR'
pts_csr_i2c_wdto_o
:
out
std_logic
;
pts_csr_i2c_wdto_i
:
in
std_logic
;
pts_csr_i2c_wdto_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
pts_lsr_front_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
pts_lsr_frontinv_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
pts_lsr_rear_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
pts_lsr_frontfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
pts_lsr_frontinvfs_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
pts_lsr_rearfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER'
pts_ter_iterm_o
:
out
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
pts_ter_oterm_o
:
out
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'PCB version number' in reg: 'HWVERS
'
pts_hwvr_hwvers_i
:
in
std_logic_vector
(
5
downto
0
)
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
pts_bidr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for BIT field: 'Channel
pulse LED enable' in reg: 'CSR'
pts_csr_chledt_o
:
out
std_logic
;
-- Port for BIT field: 'Status LED enable' in reg: 'CSR'
pts_csr_stledt_o
:
out
std_logic
;
-- Port for BIT field: 'Rear pulse LED lin
e' in reg: 'CSR'
pts_csr_rledt_o
:
out
std_logic
;
-- Port for BIT field: 'TTL test enable' in reg: 'CSR'
pts_csr_ttlpt_o
:
out
std_logic
;
-- Port for BIT field: 'Rear
pulse enable' in reg: 'CSR'
pts_csr_rearpt_o
:
out
std_logic
;
-- Port for BIT field: 'RS485 tester card VCC' in reg: 'CSR'
pts_csr_tstcvcc_o
:
out
std_logic
;
-- Port for BIT field: 'RS485 tester card MUX enable' in reg: 'CSR'
pts_csr_tstcmuxen_o
:
out
std_logic
;
-- Port for BIT field: 'RS485 tester card MUX S0 line' in reg: 'CSR'
pts_csr_tstcs0_o
:
out
std_logic
;
-- Port for BIT field: 'RS485 tester card MUX S1 line' in reg: 'CSR'
pts_csr_tstcs1_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CSR'
pts_csr_rst_unlock_o
:
out
std_logic
;
pts_csr_rst_unlock_i
:
in
std_logic
;
pts_csr_rst_unlock_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset bit -- active only if RST_UNLOCK is 1
' in reg: 'CSR'
pts_csr_rst_o
:
out
std_logic
;
pts_csr_rst_i
:
in
std_logic
;
pts_csr_rst_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'switches' in reg: 'CSR'
pts_csr_switch_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection lines
' in reg: 'CSR'
pts_csr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Ports for BIT field: 'I2C communication error' in reg: 'CSR'
pts_csr_i2c_err_o
:
out
std_logic
;
pts_csr_i2c_err_i
:
in
std_logic
;
pts_csr_i2c_err_load_o
:
out
std_logic
;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'CSR'
pts_csr_i2c_wdto_o
:
out
std_logic
;
pts_csr_i2c_wdto_i
:
in
std_logic
;
pts_csr_i2c_wdto_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
pts_lsr_front_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
pts_lsr_frontinv_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
pts_lsr_rear_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
pts_lsr_frontfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
pts_lsr_frontinvfs_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
pts_lsr_rearfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Input termination enable' in reg: 'TER'
pts_ter_iterm_o
:
out
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Output termination enable' in reg: 'TER'
pts_ter_oterm_o
:
out
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'PCB version number' in reg: 'TER
'
pts_ter_hwvers_i
:
in
std_logic_vector
(
5
downto
0
)
);
end
component
pts_regs
;
...
...
@@ -940,7 +940,7 @@ begin
(
rst_n_i
=>
rst_20_n
,
clk_sys_i
=>
clk_20_i
,
wb_adr_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
adr
(
4
downto
2
),
wb_adr_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
adr
(
3
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_pts_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_pts_regs
)
.
cyc
,
...
...
@@ -985,7 +985,7 @@ begin
pts_lsr_rearfs_i
=>
line_rear_fs
,
pts_ter_iterm_o
=>
iterm_en_o
,
pts_ter_oterm_o
=>
oterm_en_o
,
pts_
hwvr_hwvers_i
=>
pcb_version
pts_
ter_hwvers_i
=>
pcb_version
);
-- Implement the RST_UNLOCK bit
...
...
pts-fm/Makefile
View file @
e4071273
...
...
@@ -33,9 +33,9 @@ all:
mkdir
-p
ubuntu/$(BOARD)/boot
mv
ubuntu/$(BOARD)/shell/program
ubuntu/$(BOARD)/boot
mv
ubuntu/$(BOARD)/shell/flash
ubuntu/$(BOARD)/boot
wget -P ubuntu/$(BOARD)/boot https
:
//www.ohwr.org/attachments/5
782/pts-v2.1
.bit
wget -P ubuntu/$(BOARD)/boot https
:
//www.ohwr.org/attachments/5
853/pts
.bit
wget
-P
ubuntu/
$(BOARD)
/boot http://www.ohwr.org/attachments/download/3710/flash_load.bit
wget
-P
ubuntu/
$(BOARD)
/boot https://www.ohwr.org/attachments/5
781/golden-v0.0
_release-v2.0.bin
wget
-P
ubuntu/
$(BOARD)
/boot https://www.ohwr.org/attachments/5
860/golden-v0.1
_release-v2.0.bin
chmod
a+x ubuntu/
$(BOARD)
/shell/
*
chmod
a+x ubuntu/
$(BOARD)
/boot/
*
chmod
a+x ubuntu/
$(BOARD)
/jpts
...
...
pts-fm/shell/flash
View file @
e4071273
#!/bin/bash
xc3sprog
-c
xpc flash_load.bit
xc3sprog
-c
xpc
-I
golden-v0.
0
_release-v2.0.bin:w:0:bin
xc3sprog
-c
xpc
-I
golden-v0.
1
_release-v2.0.bin:w:0:bin
pts-fm/shell/program
View file @
e4071273
#!/bin/bash
xc3sprog
-c
xpc pts
-v2
.bit
xc3sprog
-c
xpc pts.bit
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