LAYOUT NOTES

POSITIONING/LAYOUT OF THE COMPONENTS

** 5V and 3V3 POWER SUPPLY PI FILTERS
The pi filters are a little bit bulky due to the OSCON capacitor. Most of the
power lines from VME are in the lower part of P1 connector, so the snippets can
be placed in between P1 and P2, respecting the spacing to the end of the board
(better if OSCONs are not the closest capacitors to the border, because they
can get accidentally damaged due to its bigger height).

Small pi filters for HS lines should be placed as close as possible to their
respective ICs.

** POWER SUPPLY
This design only has a switching power supply. Recommended layout from Texas can
be found in the datasheet and it should be followed. If better layout can be
done, do not hesitate to tell! :-)

The 3V3_VME net is located in P1 connector. This is the net that, after the pi
filter, will offer the power to the input of thee switching power supplies. So,
the PS should be positioned in the upper mid part of the VME board.

** I2C and VME GA pins
This board is not using VME bus. Instead is only underlying in SERA, SERB pins
from VME64x standard.

The buffer for these two lines should be placed close to P1 connector.

** RS485 DRIVERS
This board is intended to be used together with a separate second board.
This additional board, namely a Rear Transition Module, will be connected in
the rear part of a VME crate and will interconnect lines with the Front VME
board via P2 connector.

The lines connected by the P2 connector will be the RS485 I/O lines. Hence,
all the RS485 drivers must be placed in the lower mid part of the double height
VME board.

** FPGA
Pin swapping can be performed in most of the FPGA. Do not do pin swapping in
 PROM lines. If clock lines are moved please assign it to GLCK pins.

** EXTERNAL PLL
Better if this part is positioned away from the RS485 drivers. It can be placed
as in CONV-TTL-BLO in the upper part inbetween SFP connector and FPGA.

Same for the the DACs fetched into it.

** FLASH MEMORY
The closer to FPGA, the better.


** FRONT PANEL
If possible, it should be placed the SFP connector and the double LEMOs in
exactly the same fashion.

For the LEDs, three rows of LEDs will be placed in the upper part of the board.
The first LED out of four in the pack must be the one that goes closer to the
board.

Starting from the top, the first row corresponds to LED_SYS_PW_N, the second one
to LED_MULTICAST1_N and the third one to LED_WR_OWN_ADDR_N

** SWITCHES
There are two micro-switches:
- 8 switch: applies serigraphie for individual switch.
- 4 switch: it should have serigraphie with "MULTICAST ADDR" and markings "MSB"
 and "LSB"

** SERIGRAPHIE
Please, do not put CERN logo. Instead put
"http://www.ohwr.org/projects/conv-ttl-rs485/"
"Conv-TTL-RS485"
"[EDA number]"

LAYERS
It should fit in a six layers board.

HS LINES
The ones of the clocking resources and the FPGA MGT. MGTRREF must be equalized
as it is specified by Spartan 6 layout notes.

FRONT PANEL
It must follow a similar design to CONV-TTL-BLO front panel with the exception
of the top three rows of LEDs.
