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SVEC schematics review         10.06.2012
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MEETING SUMMARY

  + DATE           10.06.2012  15:30 - 16:30 
  + PLACE          CERN Prevessin, Building 864, Room 1-A15
  + SUBJECT        CONV-TTL-RS485 Review
  + SVN/GIT        git@ohwr.org:level-conversion/conv-ttl-rs485.git
  + REVISION       0
  + PARTICIPANTS: 
      Van der Bij, Erik          EVB    Erik.van.der.Bij@cern.ch 
      Cattin, Matthieu           MC     matthieu.cattin@cern.ch
      Gousiou, Evangelia         EG     Evangelia.Gousiou@cern.ch
      Gil Soriano, Carlos        CGS    carlos.gil.soriano@cern.ch
  + SUMMARY
      It should be checked the operation voltages of some ICs

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                    |         ! : fatal                 |  
                    |         + : important             |  
                    |         - : minor                 |   
                    |         ? : question              |  
                    |         * : note                  |  
                    |         A : already said          |  
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===============================================================================
SCHEMATICS

+ convTTLrs485_TOP.SchDoc
--+ Clocks&Monitor.SchDoc
--+ Communication.SchDoc
--+ FPGAbank.SchDoc
--+ FPGAps.SchDoc
--+ FrontPanelLeds.SchDoc
--+ FrontTTL.SchDoc
--+ JTAG&Button.SchDoc
--+ VME64xConn.SchDoc
--+ Input RS485.SchDoc
  --+ Input Unit RS485.SchDoc
--+ Output RS485.SchDoc
  --+ Output Unit RS485.SchDoc

--> BOM
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convTTLrs485_TOP.SchDoc
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[CGS]  *   Nothing reported in review.
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Clocks&Monitor.SchDoc
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[CGS]  *   Nothing reported in review.
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Communication.SchDoc
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[EVB]  -   R21 mounting status should be reported back to CONV-TTL-BLO.
  «CGS»     Done. OHWR issue reference: 501.
[MC]   -   R21 should be not mounted.
  «CGS»     Done.
[MC]   ?   R22, R23 are accurate enough for providing 50 Ohms?
  «CGS»     It is done for reducing BOM. Depending on CONV-TTL-BLO check.
[MC]   -   Move yellow comment box closer to R22, R23.
  «CGS»     Done.
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FPGAbank.SchDoc
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[EVB]  -   Improve alignement.
[MC]   -   Improve alignement.
  «CGS»     Done.
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FPGAps.SchDoc
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[MC]   -   Move yellow comment box closer to FPGA_MGTAVCC.
  «CGS»     Done.
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FrontPanelLeds.SchDoc
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[EVB]  ?   Why do we have SN74ACT14D for the LEDs?
  «CGS»     Legacy, it was done in CONV-TTL-BLO. It can be directly connected to FPGA.
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FrontTTL.SchDoc
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[EVB]  ?   Why do we have that resistor in the input?
  «CGS»     It is not mounted. It can be removed.
[EVB]  *   Perform a ESD test on CONV-TTL-BLO inputs as [EG] did.
  «CGS»     Happy to go for it.
[EVB]  ?   Is HC 3V3 capable?
  «CGS»     Yes, it is. The antiglitch feature works fine in CONV-TTL-BLO.
--------------------------------------

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JTAG&Button.SchDoc
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[MC]  -   R112 should be not mounted.
  «CGS»     Done.
[MC]  *   R112 mounting status should be reported back to CONV-TTL-BLO.
  «CGS»     Done. OHWR issue reference: 501.
--------------------------------------

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VME64xConn.SchDoc
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[MC]  !   Check VME64x daisy-chain configuration.
[MC]  !   Report back VME64x daisy-chain configuration for CONV-TTL-BLO.
  «CGS»     Done. OHWR issue reference: 501.
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Input RS485.SchDoc
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[CGS]  *   Nothing reported in review.
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Input Unit RS485.SchDoc
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[EVB]  !   IC25 must have pins 6 and 7 swapped.
  «CGS»     Done.
[EVB]  +   Pin 4 in IC24 and IC25 should be left floating?
  «CGS»     Datasheet doesn't recommend to place it in a particular value
            if not used the driving capability. Now it is grounded.
[EVB]  ?   Does SN65HVD30888ED needs external protection diodes?
  «CGS»     Datasheet claims "Bus-Pin ESD Protection Up to 15 kV". I think that protection
            is enough. Furthermore, adding external diodes will increase the input
            capacitance, so less connections would be possible.
[CGS]  *   Fail safe operation of SN65HVD3088ED is 50V.
  «CGS»     No! It is lower (16V). Enough for our needs.
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Output RS485.SchDoc
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[CGS]  *   Nothing reported in review.
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Output Unit RS485.SchDoc
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[CGS]  *   SN65HVD30888ED have builtin antiglitch feature on Power-up and down.
[CGS]  *   Even though the connection schema is pretty simple, some work behind the ropes
           was done beforehand. Ott's "Noise Reduction Techniques" gives an insight about
           when we will profit about the different shieldings and the effectivess of
           placing chokes. At the frequencies the board is thought to be working (20MHz
           rise time), the effect of the choke will not be that important. They are not
           included and BOM is reduced.
           "Grounds for Grounding", more verbose than Ott's, gives a whole-system view
           proper grounding. Several options where considered based on recommendation of
           this book (isolated transceivers, external protections, safety,...). Then, due
           to the characteristics of the board (frequency, distance, number of channels,
           complexity of layout other solutions, detection of open links...) a simple
           schema of connection will provide good results.
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LAYOUT
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