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Conv TTL RS485
Commit 06886f17 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Added V1 ucf

parent 06e0ab1c
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hdl/IMAGES/image1/constraints/V1/BloV2.ucf2 0 → 100644
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hdl/IMAGES/image1/constraints/V1/FPGAbank.NET 0 → 100644
View file @ 06886f17
CLK20_VCXO IC15-E16
EXTRA_SWITCH_1 IC15-F22
EXTRA_SWITCH_2 IC15-G22
EXTRA_SWITCH_3 IC15-H21
EXTRA_SWITCH_4 IC15-H22
EXTRA_SWITCH_5 IC15-J22
EXTRA_SWITCH_6 IC15-K21
EXTRA_SWITCH_7 IC15-K22
FPGA_CLK_N IC15-G11
FPGA_CLK_P IC15-H12
FPGA_GA0 IC15-H20
FPGA_GA1 IC15-J20
FPGA_GA2 IC15-K19
FPGA_GA3 IC15-K20
FPGA_GA4 IC15-L19
FPGA_GAP IC15-H19
FPGA_INPUT_TTL1_N IC15-T3
FPGA_INPUT_TTL2_N IC15-U4
FPGA_INPUT_TTL3_N IC15-W3
FPGA_INPUT_TTL4_N IC15-W4
FPGA_INPUT_TTL5_N IC15-V3
FPGA_INPUT_TTL6_N IC15-U3
FPGA_INV_OE IC15-N4
FPGA_OE IC15-N3
FPGA_OUT_TTL1 IC15-D1
FPGA_OUT_TTL2 IC15-E1
FPGA_OUT_TTL3 IC15-F2
FPGA_OUT_TTL4 IC15-F1
FPGA_OUT_TTL5 IC15-G1
FPGA_OUT_TTL6 IC15-H2
FPGA_PLLDAC1_DIN IC15-Y14
FPGA_PLLDAC1_SCLK IC15-AA14
FPGA_PLLDAC1_SYNC_N IC15-AB15
FPGA_PLLDAC2_DIN IC15-AB13
FPGA_PLLDAC2_SCLK IC15-Y13
FPGA_PLLDAC2_SYNC_N IC15-AB14
FPGA_PROM_CCLK IC15-Y20
FPGA_PROM_CSO_B_N IC15-AA3
FPGA_PROM_DIN IC15-AA20
FPGA_PROM_MOSI IC15-AB20
FPGA_RS485_INA_TTL_1 IC15-Y12
FPGA_RS485_INA_TTL_2 IC15-AB12
FPGA_RS485_INA_TTL_3 IC15-AB11
FPGA_RS485_INA_TTL_4 IC15-AB10
FPGA_RS485_INA_TTL_5 IC15-AB9
FPGA_RS485_INA_TTL_6 IC15-AA8
FPGA_RS485_INB_TTL_1 IC15-AA12
FPGA_RS485_INB_TTL_2 IC15-Y11
FPGA_RS485_INB_TTL_3 IC15-Y10
FPGA_RS485_INB_TTL_4 IC15-AA10
FPGA_RS485_INB_TTL_5 IC15-AB8
FPGA_RS485_INB_TTL_6 IC15-AB7
FPGA_RS485_OE IC15-AB6
FPGA_RTMM0 IC15-V21
FPGA_RTMM1 IC15-V22
FPGA_RTMM2 IC15-U22
FPGA_RTMP0 IC15-W22
FPGA_RTMP1 IC15-Y22
FPGA_RTMP2 IC15-Y21
FPGA_SFP_LOS IC15-G3
FPGA_SFP_PRESENCE IC15-E3
FPGA_SFP_RATE_SELECT IC15-C4
FPGA_SFP_SCL IC15-F3
FPGA_SFP_SDA IC15-G4
FPGA_SYSRESET_N IC15-L20
FPGA_TRIG_RS485_1 IC15-W18
FPGA_TRIG_RS485_2 IC15-Y18
FPGA_TRIG_RS485_3 IC15-W17
FPGA_TRIG_RS485_4 IC15-Y17
FPGA_TRIG_RS485_5 IC15-Y16
FPGA_TRIG_RS485_6 IC15-Y15
FPGA_TRIG_TTL_OE IC15-M3
GND R134-2
INV_IN_1_N IC15-Y1
INV_IN_2_N IC15-Y2
INV_IN_3_N IC15-AA1
INV_IN_4_N IC15-AA2
INV_OUT_1 IC15-H1
INV_OUT_2 IC15-J1
INV_OUT_3 IC15-K2
INV_OUT_4 IC15-K1
LED_CTRL0 IC15-M5
LED_CTRL0_OEN IC15-M4
LED_CTRL1 IC15-K6
LED_CTRL1_OEN IC15-K5
LED_MULTICAST_2_0 IC15-F9
LED_MULTICAST_3_1 IC15-F10
LED_WR_GMT_TTL_TTLN IC15-E5
LED_WR_LINK_SYSERROR IC15-F7
LED_WR_OK_SYSPW IC15-F8
LED_WR_OWNADDR_I2C IC15-E6
MULTICAST_ADDR_1 IC15-B21
MULTICAST_ADDR_2 IC15-B22
MULTICAST_ADDR_3 IC15-C22
MULTICAST_ADDR_4 IC15-D21
P3V3 R100-2 R111-2 R133-2
PULSE_FRONT_LED1_N IC15-H3
PULSE_FRONT_LED2_N IC15-J4
PULSE_FRONT_LED3_N IC15-J3
PULSE_FRONT_LED4_N IC15-K3
PULSE_FRONT_LED5_N IC15-L4
PULSE_FRONT_LED6_N IC15-L3
PULSE_REAR_LED1 IC15-AB17
PULSE_REAR_LED2 IC15-AB19
PULSE_REAR_LED3 IC15-AA16
PULSE_REAR_LED4 IC15-AA18
PULSE_REAR_LED5 IC15-AB16
PULSE_REAR_LED6 IC15-AB18
RST IC15-M16
SCL_I IC15-F19
SCL_O IC15-E20
SCL_OE IC15-H18
SDA_I IC15-G20
SDA_O IC15-F20
SDA_OE IC15-J19
SFP_TX_DISABLE IC15-E4
SFP_TX_FAULT IC15-D2
THERMOMETER IC15-B1
TTL/INV_TTL_N IC15-L22
FPGA_HEADER_IN1 IC15-A17
FPGA_HEADER_IN2 IC15-A18
FPGA_HEADER_IN3 IC15-B18
FPGA_HEADER_IN4 IC15-A19
FPGA_HEADER_IN5 IC15-A20
FPGA_HEADER_IN6 IC15-B20
FPGA_HEADER_OUT1 IC15-F15
FPGA_HEADER_OUT2 IC15-F16
FPGA_HEADER_OUT3 IC15-F17
FPGA_HEADER_OUT4 IC15-F14
FPGA_HEADER_OUT5 IC15-H14
FPGA_HEADER_OUT6 IC15-H13
hdl/IMAGES/image1/constraints/V1/net2ucf.py 0 → 100644
View file @ 06886f17
#!/usr/bin/python
## @package net2ucf.py
# @author Matthieu Cattin, Carlos Gil Soriano.
# This is a modified net2ucf.py by Carlos Gil Soriano,
# previously done by Matthieu Cattin.
import re
## @class net2ucf class able to extract ucf files from an Altium NET files
class NET2UCF:
## @brief Constructor of the ucf extractor
# @param path_ucfFile Path to be written the ucf file
# @param path_excludedNetsFile A path with the nets files to be excluded
# @param ICid IC identificator to extract the ucf from
def __init__(self, path_netFile, path_ucfFile, path_excludedNetsFile, ICid):
if path_netFile.endswith('.NET'):
try:
self.netFile = open(path_netFile, "r")
except IOError as e:
print '.NET file does not exist!'
else:
raise Exception('Bad extension of the net file')
if path_ucfFile.endswith('.ucf'):
try:
self.ucfFile = open(path_ucfFile, "w")
except IOError as e:
print '.ucf file does not exist!'
else:
raise Exception('Bad extension of the ucf file')
if path_excludedNetsFile.endswith('.XNET'):
try:
self.excludedNetsFile = open(path_excludedNetsFile, "r")
except IOError as e:
print '.XNET file does not exist!'
print "I'm here!"
self.listExcludedNets = []
for line in self.excludedNetsFile:
ln = line.split()
self.listExcludedNets.append(ln[0])
print 'Excluded nets:\n' + str(self.listExcludedNets)
else:
raise Exception('Bad extension of the excluded nets file')
self.ICid = ICid
## @fn generateUCF(self)
# @brief Function that process the NET file and generates the UCF one.
def generateUCF(self):
for line in self.netFile:
ln = line.split()
skip = False
for item in self.listExcludedNets:
if ln[0].startswith(str(item)):
print str(ln[0])+'Omitted because is a excluded net'
skip = True
if skip == False:
try:
print ln;
if ln[1].startswith('IC15'):
self.ucfFile.write("NET \""+ln[0]+"\" LOC = "+ln[1].split('-')[1]+";\n")
except IOError as e:
print 'Bad line in FPGA.NET'
print '-------------------------------------'
print '-------- NET2UCF program --------'
print '-------------------------------------\n'
print 'Case sensitive!\n'
path_NetFile = raw_input('Insert the path of the NET file. Format is \n'+'-- [PATH]/[name].NET:\t')
path_ucfFile = raw_input('Insert path of the ucf file. Format is \n'+'-- [PATH]/[name].ucf:\t')
path_excludedNetsFile = raw_input('Insert path of the file containing nets not to be included'+ '-- [PATH]/[name].XNET:\t')
ICid = raw_input('Insert which IC to get the ucf file from:\t')
net2ucf_inst = NET2UCF(path_NetFile, path_ucfFile, path_excludedNetsFile, ICid)
net2ucf_inst.generateUCF()
hdl/IMAGES/image1/constraints/V1/rs485.ucf 0 → 100644
View file @ 06886f17
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pcb/proto1/Proto1.SchDoc
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