CONV-TTL-RS485 project
Project Description
The CONV-TTL-RS485 system belongs to the level conversion circuits. One fully-equipped CONV-TTL-RS485 system converts to and from TTL or TTL-BAR levels to RS485 or optical signals. The project is similar to the CONV-TTL-BLO, the main difference is related to the input/output at the rear transition modules. The board is compatible with two RTMs:
- A 2-channel D-Sub9 RTM, for copper signal repetition, each channel having five outputs
- A 3-channel Optical RTM, for optical signal repetition, each channel having two outputs
Features
- VME64x 6U form-factor
- Possibility to use as timing repeater card
- Independent pulse replication channels, each channel capable of
replicating
- With CONV-TTL-RS485 motherboard alone - 6 Channels with:
- TTL to TTL
- TTL-BAR to TTL-BAR
- With
CONV-TTL-RS485-RTM-DB9
board - 2 Channels with:
- TTL to RS-485
- TTL-BAR to RS-485
- RS-485 to TTL
- RS-485 to TTL-BAR
- RS-485 to RS-485
- With
CONV-RS485-OPT-RTM
board - 3 Channels with:
- TTL to Optical
- TTL-BAR to Optical
- Optical to TTL
- Optical to TTL-BAR
- Optical to Optical
- With CONV-TTL-RS485 motherboard alone - 6 Channels with:
- Four general-purpose inverter channels
- TTL to TTL-BAR
- TTL-BAR to TTL
- Each TTL and inverter channel has 50 ohm input termination, using LEMO 00 1-pin connector
- Each TTL and inverter channel capable of driving 50 ohm load
- Each RS-485 channel capable of driving up to 256 nodes, using D-Sub9 connector
- Each RS-485 channel contains lack of signal detection logic
- SFP connector
- Diagnostics
- converter board ID
- hardware version
- gateware version
- state of on-board switches and RTM detection lines
- line state at board input
- remotely reset the FPGA logic
- input pulse counters
- input pulse time-tagging with dedicated per-channel latest timestamp readout
- manual pulse triggering
- Remote reprogramming over I2C lines on VME P1 connector
- Status LEDs
- Pulse LEDs for each replication channel
Project Information
This project is divided into three separate projects:
Useful user documentation can be found at these locations:
Project status
Date | Event |
09-12-2011 | Kicking off the project. Samples of RS-485 transceivers requested from different vendors. |
27-01-2012 | First prototype added to repo. Tests will be done next week. |
17-08-2012 | Design is finished by DEM. Front panels added to the project: EDA-02541 . Pending upon section approval for manufacturing of the prototypes. |
29-08-2012 | Design modified and accepted. Moving into prototype assembly. |
24-10-2012 | Three prototypes received. Project on hold (lower priority than conv-ttl-blo) |
29-05-2014 | Restarting work on project |
14-08-2014 | Identified an error with RTM piggiback cards, launching V2 design and production order with DEM |
29-08-2014 | Placed design and fabrication order for a V2 version of front module |
25-09-2014 | Starting RTM with piggyback V2 production |
24-10-2014 | Start of production of front module V2 boards |
05-11-2014 | Received 3x RTM with piggyback RS485 prototypes |
19-11-2014 | Received 3x front module V2 prototypes |
06-01-2015 | Golden gateware v0.0 released |
06-01-2015 | Release gateware v1.0 released |
07-01-2015 | Identified possible changes for a V3 front module card, issuing design and production order with DEM |
12-01-2015 | Start of production of 3x front module V3 prototypes |
15-03-2015 | Received 3x front module V2 prototypes |
13-06-2017 | v3 prototypes powered up and working |
30-06-2017 | Launch design of new compatible D-Sub9 RTM |
30-06-2017 | Launch design of new compatible optical to optical RTM |
27-09-2017 | Held schematics review for conv-ttl-rs485 v4 motherboard and conv-ttl-rs485 RTM DB9-to-DB9 RTM |
13-11-2017 | Held layout review for conv-ttl-rs485 v4 motherboard and conv-ttl-rs485 RTM DB9-to-DB9 RTM |
06-02-2018 | 5 prototypes for the RTM in D-SUB 9 received |
28-02-2018 | Launch layout modifications for v2 of DB9 RTM |
Theodor-Adrian Stana, Carlos Gil Soriano, Erik Van Der Bij, Denia Bouhired-Ferrag - March 12th, 2018