Version CUTEDP-V2.2.

3373722c · hongming · 860ee0fa · 3373722c · 3373722c · 3373722c
Commit 3373722c authored Mar 30, 2018 by hongming
38 changed files
--- a/PCB/cutewr_dp_v2.1.PcbDoc
+++ b/PCB/cutewr_dp_v2.1.PcbDoc
--- a/PCB/cutewr_dp_v2.2.PcbDoc
+++ b/PCB/cutewr_dp_v2.2.PcbDoc
--- a/doc/50欧姆,100欧姆,90欧姆,1.6MM,8层阻抗设计-3.xls
+++ b/doc/50欧姆,100欧姆,90欧姆,1.6MM,8层阻抗设计-3.xls
--- a/doc/ABDFTCXO_ABDFVCTCXO.pdf
+++ b/doc/ABDFTCXO_ABDFVCTCXO.pdf
--- a/doc/AST3TQ-28.pdf
+++ b/doc/AST3TQ-28.pdf
--- a/doc/LFTVXO076346Reel-1148098.pdf
+++ b/doc/LFTVXO076346Reel-1148098.pdf
--- a/doc/cdcm61004.pdf
+++ b/doc/cdcm61004.pdf
--- a/project/cutewrdpV2.1.pdf
+++ b/project/cutewrdpV2.1.pdf
--- a/project/cutewrdpV2.pdf
+++ b/project/cutewrdpV2.pdf
--- a/product/cutedpv2.1/cutewr_dp_v2.1.PcbDoc
+++ b/product/cutedpv2.1/cutewr_dp_v2.1.PcbDoc
--- a/product/cutedpv2.1/cutewrdp_bom.xlsx
+++ b/product/cutedpv2.1/cutewrdp_bom.xlsx
--- a/product/cutedpv2.2/50欧姆,100欧姆,90欧姆,1.6MM,8层阻抗设计-3.xls
+++ b/product/cutedpv2.2/50欧姆,100欧姆,90欧姆,1.6MM,8层阻抗设计-3.xls
--- a/product/cutedpv2.2/cutewr_dp_v2.2.PcbDoc
+++ b/product/cutedpv2.2/cutewr_dp_v2.2.PcbDoc
--- a/product/cutedpv2.2/cutewrdpV2.2_for_CERN_Matteo Di Cosmo.xlsx
+++ b/product/cutedpv2.2/cutewrdpV2.2_for_CERN_Matteo Di Cosmo.xlsx
--- a/product/cutewrdp_bom.xlsx
+++ b/product/cutewrdp_bom.xlsx
--- a/project/cutewrdpV2.PrjPCB
+++ b/project/cutewrdpV2.PrjPCB
@@ -30,7 +30,7 @@ DItemRevisionGUID=
 ReportSuppressedErrorsInMessages=0
 FSMCodingStyle=eFMSDropDownList_OneProcess
 FSMEncodingStyle=eFMSDropDownList_OneHot
-OutputPath=Project Outputs for cutewrdpV2
+OutputPath=
 LogFolderPath=
 ManagedProjectGUID=
@@ -293,6 +293,10 @@ DItemRevisionGUID=
 GenerateClassCluster=0
 DocumentUniqueId=GMRTVGJC
+[GeneratedDocument1]
+DocumentPath=Project Outputs for cutewrdpV2\Design Rule Check - cutewr_dp_v2.html
+DItemRevisionGUID=
 [Configuration1]
 Name=Default Configuration
 ParameterCount=0
@@ -339,7 +343,7 @@ SCH_ShowNote=-1
 SCH_ShowNoteCollapsed=-1
 [Generic_EDE]
-OutputDir=Project Outputs for cutewrdpV2
+OutputDir=
 [OutputGroup1]
 Name=Netlist Outputs

--- a/project/cutewrdpV2.2.PrjPCB
+++ b/project/cutewrdpV2.2.PrjPCB
--- a/schematics/00cutewr_dp.SchDoc
+++ b/schematics/00cutewr_dp.SchDoc
--- a/schematics/01-Clocks.SchDoc
+++ b/schematics/01-Clocks.SchDoc
--- a/schematics/03-FPGA_bank1.SchDoc
+++ b/schematics/03-FPGA_bank1.SchDoc
--- a/schematics/04-FPGA_bank2.SchDoc
+++ b/schematics/04-FPGA_bank2.SchDoc
--- a/schematics/05-FPGA_bank3.SchDoc
+++ b/schematics/05-FPGA_bank3.SchDoc
--- a/schematics/06-FPGA_GTP.SchDoc
+++ b/schematics/06-FPGA_GTP.SchDoc
--- a/schematics/07-FPGA_Config.SchDoc
+++ b/schematics/07-FPGA_Config.SchDoc
--- a/schematics/08-FPGA_Power.SchDoc
+++ b/schematics/08-FPGA_Power.SchDoc
--- a/schematics/09-Power.SchDoc
+++ b/schematics/09-Power.SchDoc
--- a/schematics/1-Clocks.SchDoc
+++ b/schematics/1-Clocks.SchDoc
--- a/schematics/10-SFP.SchDoc
+++ b/schematics/10-SFP.SchDoc
--- a/schematics/12-Pmod_Connector.SchDoc
+++ b/schematics/12-Pmod_Connector.SchDoc
--- a/schematics/13-User_Interface.SchDoc
+++ b/schematics/13-User_Interface.SchDoc
--- a/schematics/2-FPGA_bank0.SchDoc
+++ b/schematics/2-FPGA_bank0.SchDoc
--- a/schematics/3-FPGA_bank1.SchDoc
+++ b/schematics/3-FPGA_bank1.SchDoc
--- a/schematics/4-FPGA_bank2.SchDoc
+++ b/schematics/4-FPGA_bank2.SchDoc
--- a/schematics/5-FPGA_bank3.SchDoc
+++ b/schematics/5-FPGA_bank3.SchDoc
--- a/schematics/6-FPGA_GTP.SchDoc
+++ b/schematics/6-FPGA_GTP.SchDoc
--- a/schematics/7-FPGA_Config.SchDoc
+++ b/schematics/7-FPGA_Config.SchDoc
--- a/schematics/8-FPGA_Power.SchDoc
+++ b/schematics/8-FPGA_Power.SchDoc
--- a/schematics/9-Power.SchDoc
+++ b/schematics/9-Power.SchDoc