Commit 989f847a authored by hongming's avatar hongming

Rebuild as lacking of a main clock

parent 0704df77
layer function LINE WIDTH/CONTROLLED Impedance
top layer signal layer 6 mils/50 Ohms 5mil differential lines /100 Ohms Impedance
layer 2 GND layer
layer 3 POWER layer
layer 4 signal layer 6 mils/50 Ohms 5mil differential lines /100 Ohms Impedance
layer 5 GND layer
bottom layer signal layer 6 mils/50 Ohms 5mil differential lines /100 Ohms Impedance
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