Compact Universal Timing Endpoint Based on White Rabbit
Introduction
The cute-wr project is a standalone White Rabbit Node implementation on a FPGA Mezzanine Card. The idea is to have a compact, low-cost and common WR NIC for synchronous DAQ frontends and other applications.
Structure Design
cute-wr is originally derived from and keeps firmware compatibly with the SPEC board. The White Rabbit Node Reference Design has detailed information on infrastructure design.
Features:
- Standalone Operation;
- Spartan 6 (XC6SLX45T-3FGG484C);
- 32MBit SPI FLASH (M25P32-VMF6P);
- 64Kbit I2C EEPROM (24AA64T-I/MC);
- FMC LPC interface;
- JTAG and RS232;
- External CLK reference (work in master mode);
- 125MHz CLK and PPS output;
- 3 user LEDs;
Application orientation
Timing distribution for LHAASO Project:
Please refer to:
- The proposed Large High Altitude Air Shower Observatory (LHAASO) project
- Guanghua Gong, Shaomin Chen, Qiang Du, Jianming Li, Yinong Liu, Huihai He, Sub-nanosecond timing system design and development for LHAASO Project , in Proceedings of ICALEPCS2011, Grenoble, France, 2011
Current status
stm.jpg
The first version has been tested on March 5, 2012, and showed a similar
performance comparing with SPEC boards.