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DDR3 controller for Spartan6
DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.
Project ID: 10708
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Tristan Gingold authored
Add an entry for v2.0.1 See merge request be-cem-edl/common/ddr3-sp6-core!1
01a07e1d
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Manifest.py |