library ieee;
use ieee.std_logic_1164.all;

entity diot_hydra2_periph is
  port(
    -- Inputs
    clk_i                               : in  std_logic;
    DEVRST_N                            : in  std_logic;
    HPMS_FIC_0_USER_MASTER_HADDR_M0     : in  std_logic_vector(31 downto 0);
    HPMS_FIC_0_USER_MASTER_HBURST_M0    : in  std_logic_vector(2 downto 0);
    HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0 : in  std_logic;
    HPMS_FIC_0_USER_MASTER_HPROT_M0     : in  std_logic_vector(3 downto 0);
    HPMS_FIC_0_USER_MASTER_HSIZE_M0     : in  std_logic_vector(2 downto 0);
    HPMS_FIC_0_USER_MASTER_HTRANS_M0    : in  std_logic_vector(1 downto 0);
    HPMS_FIC_0_USER_MASTER_HWDATA_M0    : in  std_logic_vector(31 downto 0);
    HPMS_FIC_0_USER_MASTER_HWRITE_M0    : in  std_logic;
    -- Outputs
    HPMS_FIC_0_USER_MASTER_HRDATA_M0    : out std_logic_vector(31 downto 0);
    HPMS_FIC_0_USER_MASTER_HREADY_M0    : out std_logic;
    HPMS_FIC_0_USER_MASTER_HRESP_M0     : out std_logic_vector(1 downto 0);
    POWER_ON_RESET_N                    : out std_logic;

    clk_sys_o : out std_logic;
    clk_cpu1_o : out std_logic;
    clk_cpu2_o : out std_logic;
    clk_cpu3_o : out std_logic
    );
end diot_hydra2_periph;

architecture arch of diot_hydra2_periph is
  component CLKINT is
    port (
      A : in  std_logic;
      Y : out std_logic
    );
  end component;

  signal clk_sys, clk_cpu1, clk_cpu2, clk_cpu3 : std_logic;
  attribute syn_keep : boolean;
  attribute syn_keep of clk_sys : signal is true;
begin
  inst_clk_sys: CLKINT
    port map (
      A => clk_i,
      Y => clk_sys
    );
  inst_clk_cpu1: CLKINT
    port map (
      A => clk_i,
      Y => clk_cpu1
    );
  inst_clk_cpu2: CLKINT
    port map (
      A => clk_i,
      Y => clk_cpu2
    );
  inst_clk_cpu3: CLKINT
    port map (
      A => clk_i,
      Y => clk_cpu3
    );

  clk_sys_o <= clk_sys;
  clk_cpu1_o <= clk_cpu1;
  clk_cpu2_o <= clk_cpu2;
  clk_cpu3_o <= clk_cpu3;

  inst_igl2: entity work.igl2_periph
    port map (
      CLK0                                => clk_sys,
      DEVRST_N                            => DEVRST_N,
      FAB_RESET_N                         => '1',
      HPMS_FIC_0_USER_MASTER_HADDR_M0     => HPMS_FIC_0_USER_MASTER_HADDR_M0,
      HPMS_FIC_0_USER_MASTER_HBURST_M0    => HPMS_FIC_0_USER_MASTER_HBURST_M0,
      HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0 => HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0,       
      HPMS_FIC_0_USER_MASTER_HPROT_M0     => HPMS_FIC_0_USER_MASTER_HPROT_M0,
      HPMS_FIC_0_USER_MASTER_HSIZE_M0     => HPMS_FIC_0_USER_MASTER_HSIZE_M0,
      HPMS_FIC_0_USER_MASTER_HTRANS_M0    => HPMS_FIC_0_USER_MASTER_HTRANS_M0,
      HPMS_FIC_0_USER_MASTER_HWDATA_M0    => HPMS_FIC_0_USER_MASTER_HWDATA_M0,
      HPMS_FIC_0_USER_MASTER_HWRITE_M0    => HPMS_FIC_0_USER_MASTER_HWRITE_M0,
      COMM_BLK_INT                        => open,
      FIC_0_CLK                           => open,
      FIC_0_LOCK                          => open,
      HPMS_FIC_0_USER_MASTER_HRDATA_M0    => HPMS_FIC_0_USER_MASTER_HRDATA_M0,
      HPMS_FIC_0_USER_MASTER_HREADY_M0    => HPMS_FIC_0_USER_MASTER_HREADY_M0,
      HPMS_FIC_0_USER_MASTER_HRESP_M0     => HPMS_FIC_0_USER_MASTER_HRESP_M0,
      HPMS_INT_M2F                        => open,
      HPMS_READY                          => open,
      INIT_DONE                           => open,
      POWER_ON_RESET_N                    => POWER_ON_RESET_N);
end arch;
