from hdlmake.util.shell import *

run_simulation = True
fip_urv_target = "fip_dbg"
stoptime = "100us"
wavefile = "wave.ghw"

action = "simulation"
sim_tool = "ghdl"
top_module = "tb_diot_hydra2"
ghdl_opt = "--std=08"

fetchto = "../../ip_cores"
target = "gen"

fip_urv_path="../../../sw/fip_urv/"

sim_pre_cmd = (
    "$(MAKE) -C " + fip_urv_path + " OUTPUT=" + fip_urv_target + "\n\t\t"
    + copy_command() + " " + fip_urv_path.replace("/", makefile_slash_char()) + fip_urv_target + ".mem fip_urv.mem"
)

if run_simulation:
    sim_post_cmd = (
        "ghdl -r " + ghdl_opt + " " + top_module + " --stop-time=" + stoptime + " --wave=" + wavefile + "\n\t\t"
        "gtkwave " + wavefile + " signals.gtkw"
    )

files = ['tb_diot_hydra2.vhd', 'spi_flash.vhd', "diot_hydra2_periph.vhd",
         'mem_utils.vhd', 'spi_top.vhd',
         'urv.vhd',
         '../../top/diot_hydra2/diot_hydra2_top.vhd',
         '../../top/diot_hydra2/diot_hydra2_core.vhd']

modules = {
    'local': ['../../rtl'],
    "git": [
        "https://ohwr.org/project/general-cores.git",
        "https://ohwr.org/project/urv-core.git",
    ],
}

