# Creating SmartDesign igl2_periph
set sd_name {igl2_periph}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FAB_RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HWRITE_M0} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {COMM_BLK_INT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC_0_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FIC_0_LOCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HREADY_M0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HPMS_READY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {POWER_ON_RESET_N} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HADDR_M0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HBURST_M0} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HPROT_M0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HSIZE_M0} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HTRANS_M0} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HWDATA_M0} -port_direction {IN} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HRDATA_M0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER_HRESP_M0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPMS_INT_M2F} -port_direction {OUT} -port_range {[15:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {HPMS_FIC_0_USER_MASTER} -port_bif_vlnv {AMBA:AMBA2:AHB:r0p0} -port_bif_role {mirroredMaster} -port_bif_mapping {\
"HADDR:HPMS_FIC_0_USER_MASTER_HADDR_M0" \
"HTRANS:HPMS_FIC_0_USER_MASTER_HTRANS_M0" \
"HWRITE:HPMS_FIC_0_USER_MASTER_HWRITE_M0" \
"HSIZE:HPMS_FIC_0_USER_MASTER_HSIZE_M0" \
"HBURST:HPMS_FIC_0_USER_MASTER_HBURST_M0" \
"HPROT:HPMS_FIC_0_USER_MASTER_HPROT_M0" \
"HWDATA:HPMS_FIC_0_USER_MASTER_HWDATA_M0" \
"HLOCK:HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0" \
"HRDATA:HPMS_FIC_0_USER_MASTER_HRDATA_M0" \
"HREADY:HPMS_FIC_0_USER_MASTER_HREADY_M0" \
"HRESP:HPMS_FIC_0_USER_MASTER_HRESP_M0" } 

# Add igl2_periph_sb_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {igl2_periph_sb} -instance_name {igl2_periph_sb_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK0" "igl2_periph_sb_0:CLK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COMM_BLK_INT" "igl2_periph_sb_0:COMM_BLK_INT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVRST_N" "igl2_periph_sb_0:DEVRST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FAB_RESET_N" "igl2_periph_sb_0:FAB_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC_0_CLK" "igl2_periph_sb_0:FIC_0_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC_0_LOCK" "igl2_periph_sb_0:FIC_0_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HPMS_READY" "igl2_periph_sb_0:HPMS_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_DONE" "igl2_periph_sb_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"POWER_ON_RESET_N" "igl2_periph_sb_0:POWER_ON_RESET_N" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"HPMS_INT_M2F" "igl2_periph_sb_0:HPMS_INT_M2F" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"HPMS_FIC_0_USER_MASTER" "igl2_periph_sb_0:HPMS_FIC_0_USER_MASTER" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign igl2_periph
generate_component -component_name ${sd_name}
