----------------------------------------------------------------------
-- Created by SmartDesign Wed May 11 09:36:55 2022
-- Version: v2021.2 2021.2.0.11
----------------------------------------------------------------------

----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

--library smartfusion2;
--use smartfusion2.all;
--library COREAHBLITE_LIB;
--use COREAHBLITE_LIB.all;
--use COREAHBLITE_LIB.components.all;
----------------------------------------------------------------------
-- igl2_periph_sb entity declaration
----------------------------------------------------------------------
entity igl2_periph_sb is
    -- Port list
    port(
        -- Inputs
        CLK0                                : in  std_logic;
        DEVRST_N                            : in  std_logic;
        FAB_RESET_N                         : in  std_logic;
        HPMS_FIC_0_USER_MASTER_HADDR_M0     : in  std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HBURST_M0    : in  std_logic_vector(2 downto 0);
        HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0 : in  std_logic;
        HPMS_FIC_0_USER_MASTER_HPROT_M0     : in  std_logic_vector(3 downto 0);
        HPMS_FIC_0_USER_MASTER_HSIZE_M0     : in  std_logic_vector(2 downto 0);
        HPMS_FIC_0_USER_MASTER_HTRANS_M0    : in  std_logic_vector(1 downto 0);
        HPMS_FIC_0_USER_MASTER_HWDATA_M0    : in  std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HWRITE_M0    : in  std_logic;
        -- Outputs
        COMM_BLK_INT                        : out std_logic;
        FIC_0_CLK                           : out std_logic;
        FIC_0_LOCK                          : out std_logic;
        HPMS_FIC_0_USER_MASTER_HRDATA_M0    : out std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HREADY_M0    : out std_logic;
        HPMS_FIC_0_USER_MASTER_HRESP_M0     : out std_logic_vector(1 downto 0);
        HPMS_INT_M2F                        : out std_logic_vector(15 downto 0);
        HPMS_READY                          : out std_logic;
        INIT_DONE                           : out std_logic;
        POWER_ON_RESET_N                    : out std_logic
        );
end igl2_periph_sb;
----------------------------------------------------------------------
-- igl2_periph_sb architecture body
----------------------------------------------------------------------
architecture RTL of igl2_periph_sb is

-- igl2_periph_sb_HPMS
component igl2_periph_sb_HPMS
    -- Port list
    port(
        -- Inputs
        FIC_0_AHB_S_HADDR      : in  std_logic_vector(31 downto 0);
        FIC_0_AHB_S_HMASTLOCK  : in  std_logic;
        FIC_0_AHB_S_HREADY     : in  std_logic;
        FIC_0_AHB_S_HSEL       : in  std_logic;
        FIC_0_AHB_S_HSIZE      : in  std_logic_vector(1 downto 0);
        FIC_0_AHB_S_HTRANS     : in  std_logic_vector(1 downto 0);
        FIC_0_AHB_S_HWDATA     : in  std_logic_vector(31 downto 0);
        FIC_0_AHB_S_HWRITE     : in  std_logic;
        FIC_2_APB_M_PRDATA     : in  std_logic_vector(31 downto 0);
        FIC_2_APB_M_PREADY     : in  std_logic;
        FIC_2_APB_M_PSLVERR    : in  std_logic;
        M3_RESET_N             : in  std_logic;
        MCCC_CLK_BASE          : in  std_logic;
        MCCC_CLK_BASE_PLL_LOCK : in  std_logic;
        MSS_INT_F2M            : in  std_logic_vector(15 downto 0);
        MSS_RESET_N_F2M        : in  std_logic;
        -- Outputs
        COMM_BLK_INT           : out std_logic;
        FIC_0_AHB_S_HRDATA     : out std_logic_vector(31 downto 0);
        FIC_0_AHB_S_HREADYOUT  : out std_logic;
        FIC_0_AHB_S_HRESP      : out std_logic;
        FIC_2_APB_M_PADDR      : out std_logic_vector(15 downto 2);
        FIC_2_APB_M_PCLK       : out std_logic;
        FIC_2_APB_M_PENABLE    : out std_logic;
        FIC_2_APB_M_PRESET_N   : out std_logic;
        FIC_2_APB_M_PSEL       : out std_logic;
        FIC_2_APB_M_PWDATA     : out std_logic_vector(31 downto 0);
        FIC_2_APB_M_PWRITE     : out std_logic;
        M3_NMI                 : out std_logic;
        MSS_INT_M2F            : out std_logic_vector(15 downto 0);
        MSS_RESET_N_M2F        : out std_logic
        );
end component;
-- SYSRESET
component SYSRESET
    -- Port list
    port(
        -- Inputs
        DEVRST_N         : in  std_logic;
        -- Outputs
        POWER_ON_RESET_N : out std_logic
        );
    end component;
    ----------------------------------------------------------------------
    -- Signal declarations
    ----------------------------------------------------------------------
    signal CoreAHBLite_0_AHBmslave16_HADDR                : std_logic_vector(31 downto 0);
    signal CoreAHBLite_0_AHBmslave16_HBURST               : std_logic_vector(2 downto 0);
    signal CoreAHBLite_0_AHBmslave16_HMASTLOCK            : std_logic;
    signal CoreAHBLite_0_AHBmslave16_HPROT                : std_logic_vector(3 downto 0);
    signal CoreAHBLite_0_AHBmslave16_HRDATA               : std_logic_vector(31 downto 0);
    signal CoreAHBLite_0_AHBmslave16_HREADY               : std_logic;
    signal CoreAHBLite_0_AHBmslave16_HREADYOUT            : std_logic;
    signal CoreAHBLite_0_AHBmslave16_HSELx                : std_logic;
    signal CoreAHBLite_0_AHBmslave16_HTRANS               : std_logic_vector(1 downto 0);
    signal CoreAHBLite_0_AHBmslave16_HWDATA               : std_logic_vector(31 downto 0);
    signal CoreAHBLite_0_AHBmslave16_HWRITE               : std_logic;
    signal por_n                       : std_logic;
    signal POWER_ON_RESET_N_int                           : std_logic;
    signal FIC_2_APB_M_PRESET_N : std_logic;
    signal MSS_RESET_N_M2F : std_logic;

    ----------------------------------------------------------------------
    -- Bus Interface Nets Declarations - Unequal Pin Widths
    ----------------------------------------------------------------------
    signal CoreAHBLite_0_AHBmslave16_HRESP                : std_logic;
    signal CoreAHBLite_0_AHBmslave16_HSIZE                : std_logic_vector(1 downto 0);
begin
   -- out
   HPMS_FIC_0_USER_MASTER_HRDATA_M0 <= CoreAHBLite_0_AHBmslave16_HRDATA;
   HPMS_FIC_0_USER_MASTER_HREADY_M0 <= CoreAHBLite_0_AHBmslave16_HREADYOUT;
   HPMS_FIC_0_USER_MASTER_HRESP_M0(0) <= CoreAHBLite_0_AHBmslave16_HRESP;
   HPMS_FIC_0_USER_MASTER_HRESP_M0(1) <= '1';

   --  in
   CoreAHBLite_0_AHBmslave16_HADDR <= HPMS_FIC_0_USER_MASTER_HADDR_M0;
   CoreAHBLite_0_AHBmslave16_HBURST <= HPMS_FIC_0_USER_MASTER_HBURST_M0;
   CoreAHBLite_0_AHBmslave16_HMASTLOCK <= HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0;
   CoreAHBLite_0_AHBmslave16_HPROT <= HPMS_FIC_0_USER_MASTER_HPROT_M0;
   CoreAHBLite_0_AHBmslave16_HSIZE <= HPMS_FIC_0_USER_MASTER_HSIZE_M0(1 downto 0);
   CoreAHBLite_0_AHBmslave16_HTRANS <= HPMS_FIC_0_USER_MASTER_HTRANS_M0;
   CoreAHBLite_0_AHBmslave16_HWDATA <= HPMS_FIC_0_USER_MASTER_HWDATA_M0;
   CoreAHBLite_0_AHBmslave16_HWRITE <= HPMS_FIC_0_USER_MASTER_HWRITE_M0;

   CoreAHBLite_0_AHBmslave16_HSELx <= HPMS_FIC_0_USER_MASTER_HTRANS_M0(1);
   CoreAHBLite_0_AHBmslave16_HREADY <= CoreAHBLite_0_AHBmslave16_HREADYOUT;


 process(clk0, power_on_reset_n_int)
 begin
    if POWER_ON_RESET_N_int = '0' then
      por_n <= '0';
    elsif rising_edge(clk0) then
      if por_n = '0' then
        if FIC_2_APB_M_PRESET_N = '1' and MSS_RESET_N_M2F = '1' then
          por_n <= '1';
        end if;
       end if;
    end if;
 end process;

 POWER_ON_RESET_N <= por_n;
 

igl2_periph_sb_HPMS_0 : igl2_periph_sb_HPMS
    port map( 
        -- Inputs
        MCCC_CLK_BASE          => CLK0,
        MCCC_CLK_BASE_PLL_LOCK => '1',
        MSS_RESET_N_F2M        => '1',
        M3_RESET_N             => '0',
        FIC_0_AHB_S_HREADY     => CoreAHBLite_0_AHBmslave16_HREADY,
        FIC_0_AHB_S_HWRITE     => CoreAHBLite_0_AHBmslave16_HWRITE,
        FIC_0_AHB_S_HMASTLOCK  => CoreAHBLite_0_AHBmslave16_HMASTLOCK,
        FIC_0_AHB_S_HSEL       => CoreAHBLite_0_AHBmslave16_HSELx,
        FIC_2_APB_M_PREADY     => '1', -- tied to '1' from definition
        FIC_2_APB_M_PSLVERR    => '0', -- tied to '0' from definition
        FIC_0_AHB_S_HADDR      => CoreAHBLite_0_AHBmslave16_HADDR,
        FIC_0_AHB_S_HWDATA     => CoreAHBLite_0_AHBmslave16_HWDATA,
        FIC_0_AHB_S_HSIZE      => CoreAHBLite_0_AHBmslave16_HSIZE,
        FIC_0_AHB_S_HTRANS     => CoreAHBLite_0_AHBmslave16_HTRANS,
        FIC_2_APB_M_PRDATA     => (others => '0'),
        MSS_INT_F2M            => (others => '0'),
        -- Outputs
        MSS_RESET_N_M2F        => MSS_RESET_N_M2F,
        FIC_0_AHB_S_HRESP      => CoreAHBLite_0_AHBmslave16_HRESP,
        FIC_0_AHB_S_HREADYOUT  => CoreAHBLite_0_AHBmslave16_HREADYOUT,
        FIC_2_APB_M_PRESET_N   => FIC_2_APB_M_PRESET_N,
        FIC_2_APB_M_PCLK       => OPEN,
        FIC_2_APB_M_PWRITE     => OPEN,
        FIC_2_APB_M_PENABLE    => OPEN,
        FIC_2_APB_M_PSEL       => OPEN,
        M3_NMI                 => OPEN,
        COMM_BLK_INT           => COMM_BLK_INT,
        FIC_0_AHB_S_HRDATA     => CoreAHBLite_0_AHBmslave16_HRDATA,
        FIC_2_APB_M_PADDR      => OPEN,
        FIC_2_APB_M_PWDATA     => OPEN,
        MSS_INT_M2F            => OPEN
        );
-- SYSRESET_POR
SYSRESET_POR : SYSRESET
    port map( 
        -- Inputs
        DEVRST_N         => DEVRST_N,
        -- Outputs
        POWER_ON_RESET_N => POWER_ON_RESET_N_int
        );

end RTL;
