#ifndef __CHEBY__HYDRA_SUPERVISOR_REGS__H__
#define __CHEBY__HYDRA_SUPERVISOR_REGS__H__
#define HYDRA_SUPERVISOR_REGS_SIZE 100 /* 0x64 */

/* Cause of a reset */
#define HYDRA_SUPERVISOR_REGS_RESET_CAUSE 0x0UL
#define HYDRA_SUPERVISOR_REGS_RESET_CAUSE_CPU 0x1UL
#define HYDRA_SUPERVISOR_REGS_RESET_CAUSE_IRAM_ECC 0x2UL
#define HYDRA_SUPERVISOR_REGS_RESET_CAUSE_DRAM_ECC 0x4UL
#define HYDRA_SUPERVISOR_REGS_RESET_CAUSE_WATCHDOG 0x8UL
#define HYDRA_SUPERVISOR_REGS_RESET_CAUSE_RECOVERY 0x10UL

/* state of cpus */
#define HYDRA_SUPERVISOR_REGS_CPU 0x4UL
#define HYDRA_SUPERVISOR_REGS_CPU_RESET_MASK 0x7UL
#define HYDRA_SUPERVISOR_REGS_CPU_RESET_SHIFT 0
#define HYDRA_SUPERVISOR_REGS_CPU_RECOVERY 0x100UL

/* Each cpu will read a different value from this registers */
#define HYDRA_SUPERVISOR_REGS_FORCE_DIVERGENCE 0x8UL

/* Nbr of cycles before watchdog timeout. */
#define HYDRA_SUPERVISOR_REGS_WD_PERIOD 0xcUL

/* Current counter value (decremented) */
#define HYDRA_SUPERVISOR_REGS_WD_COUNT 0x10UL

/* Write 0xc0423bc9 to restart watchdog counter */
#define HYDRA_SUPERVISOR_REGS_WD_KEY 0x14UL

/* Number of ECC correctable errors for iram */
#define HYDRA_SUPERVISOR_REGS_IRAM_ECC_SE 0x18UL

/* IRAM scrubber cycle number. */
#define HYDRA_SUPERVISOR_REGS_IRAM_SCRUB_CYCLE 0x1cUL

/* Number of ECC corrected errors by scrubber in iram */
#define HYDRA_SUPERVISOR_REGS_IRAM_SCRUB_SE 0x20UL

/* Number of ECC uncorrected errors by scrubber in iram in the current scrubber cycle.  Saturate.
 */
#define HYDRA_SUPERVISOR_REGS_IRAM_SCRUB_DE_CURR 0x24UL

/* Number of ECC uncorrected errors by scrubber in iram during the last scrubber cycle.  Saturate.
 */
#define HYDRA_SUPERVISOR_REGS_IRAM_SCRUB_DE_LAST 0x28UL

/* Number of ECC correctable errors for dram */
#define HYDRA_SUPERVISOR_REGS_DRAM_ECC_SE 0x2cUL

/* DRAM scrubber cycle number. */
#define HYDRA_SUPERVISOR_REGS_DRAM_SCRUB_CYCLE 0x30UL

/* Number of ECC corrected errors by scrubber in dram */
#define HYDRA_SUPERVISOR_REGS_DRAM_SCRUB_SE 0x34UL

/* Number of ECC uncorrected errors by scrubber in dram in the current scrubber cycle.  Saturate.
 */
#define HYDRA_SUPERVISOR_REGS_DRAM_SCRUB_DE_CURR 0x38UL

/* Number of ECC uncorrected errors by scrubber in dram during the last scrubber cycle.  Saturate.
 */
#define HYDRA_SUPERVISOR_REGS_DRAM_SCRUB_DE_LAST 0x3cUL

/* Number of CPU errors on data bus */
#define HYDRA_SUPERVISOR_REGS_CPU_DATA_ERR 0x40UL

/* Number of CPU errors on instruction bus */
#define HYDRA_SUPERVISOR_REGS_CPU_IADDR_ERR 0x44UL

/* Change ECC bits on dram writes for testing */
#define HYDRA_SUPERVISOR_REGS_DRAM_ECC_MASK 0x48UL

/* Address of the last ecc error */
#define HYDRA_SUPERVISOR_REGS_IRAM_ECC_ADDR 0x4cUL

/* Force one error on the address (insn) */
#define HYDRA_SUPERVISOR_REGS_IRAM_ERR_ADDR 0x50UL
#define HYDRA_SUPERVISOR_REGS_IRAM_ERR_ADDR_EN 0x1UL
#define HYDRA_SUPERVISOR_REGS_IRAM_ERR_ADDR_ADDR_MASK 0xfffcUL
#define HYDRA_SUPERVISOR_REGS_IRAM_ERR_ADDR_ADDR_SHIFT 2

/* configuration of scrubbers */
#define HYDRA_SUPERVISOR_REGS_SCRUB_CFG 0x54UL
#define HYDRA_SUPERVISOR_REGS_SCRUB_CFG_IRAM_EN 0x1UL
#define HYDRA_SUPERVISOR_REGS_SCRUB_CFG_DRAM_EN 0x2UL

/* Maximum number of cycles between a scrub */
#define HYDRA_SUPERVISOR_REGS_IRAM_SCRUB_PERIOD 0x58UL
#define HYDRA_SUPERVISOR_REGS_IRAM_SCRUB_PERIOD_PRESET 0x7ffUL

/* Maximum number of cycles between a scrub */
#define HYDRA_SUPERVISOR_REGS_DRAM_SCRUB_PERIOD 0x5cUL
#define HYDRA_SUPERVISOR_REGS_DRAM_SCRUB_PERIOD_PRESET 0x7ffUL

/* Number of cpu faults */
#define HYDRA_SUPERVISOR_REGS_CPU_FAULT_COUNT 0x60UL

#ifndef __ASSEMBLER__
struct hydra_supervisor_regs {
  /* [0x0]: REG (ro) Cause of a reset */
  uint32_t reset_cause;

  /* [0x4]: REG (rw) state of cpus */
  uint32_t cpu;

  /* [0x8]: REG (ro) Each cpu will read a different value from this registers */
  uint32_t force_divergence;

  /* [0xc]: REG (rw) Nbr of cycles before watchdog timeout. */
  uint32_t wd_period;

  /* [0x10]: REG (ro) Current counter value (decremented) */
  uint32_t wd_count;

  /* [0x14]: REG (wo) Write 0xc0423bc9 to restart watchdog counter */
  uint32_t wd_key;

  /* [0x18]: REG (ro) Number of ECC correctable errors for iram */
  uint32_t iram_ecc_se;

  /* [0x1c]: REG (ro) IRAM scrubber cycle number. */
  uint16_t iram_scrub_cycle;

  /* padding to: 32 words */
  uint8_t __padding_0[2];

  /* [0x20]: REG (ro) Number of ECC corrected errors by scrubber in iram */
  uint32_t iram_scrub_se;

  /* [0x24]: REG (ro) Number of ECC uncorrected errors by scrubber in iram in the current scrubber cycle.  Saturate.
 */
  uint16_t iram_scrub_de_curr;

  /* padding to: 40 words */
  uint8_t __padding_1[2];

  /* [0x28]: REG (ro) Number of ECC uncorrected errors by scrubber in iram during the last scrubber cycle.  Saturate.
 */
  uint16_t iram_scrub_de_last;

  /* padding to: 44 words */
  uint8_t __padding_2[2];

  /* [0x2c]: REG (ro) Number of ECC correctable errors for dram */
  uint32_t dram_ecc_se;

  /* [0x30]: REG (ro) DRAM scrubber cycle number. */
  uint16_t dram_scrub_cycle;

  /* padding to: 52 words */
  uint8_t __padding_3[2];

  /* [0x34]: REG (ro) Number of ECC corrected errors by scrubber in dram */
  uint32_t dram_scrub_se;

  /* [0x38]: REG (ro) Number of ECC uncorrected errors by scrubber in dram in the current scrubber cycle.  Saturate.
 */
  uint16_t dram_scrub_de_curr;

  /* padding to: 60 words */
  uint8_t __padding_4[2];

  /* [0x3c]: REG (ro) Number of ECC uncorrected errors by scrubber in dram during the last scrubber cycle.  Saturate.
 */
  uint16_t dram_scrub_de_last;

  /* padding to: 64 words */
  uint8_t __padding_5[2];

  /* [0x40]: REG (ro) Number of CPU errors on data bus */
  uint32_t cpu_data_err;

  /* [0x44]: REG (ro) Number of CPU errors on instruction bus */
  uint32_t cpu_iaddr_err;

  /* [0x48]: REG (rw) Change ECC bits on dram writes for testing */
  uint8_t dram_ecc_mask;

  /* padding to: 76 words */
  uint8_t __padding_6[3];

  /* [0x4c]: REG (ro) Address of the last ecc error */
  uint32_t iram_ecc_addr;

  /* [0x50]: REG (rw) Force one error on the address (insn) */
  uint32_t iram_err_addr;

  /* [0x54]: REG (rw) configuration of scrubbers */
  uint32_t scrub_cfg;

  /* [0x58]: REG (rw) Maximum number of cycles between a scrub */
  uint16_t iram_scrub_period;

  /* padding to: 92 words */
  uint8_t __padding_7[2];

  /* [0x5c]: REG (rw) Maximum number of cycles between a scrub */
  uint16_t dram_scrub_period;

  /* padding to: 96 words */
  uint8_t __padding_8[2];

  /* [0x60]: REG (rw) Number of cpu faults */
  uint32_t cpu_fault_count;
};
#endif /* !__ASSEMBLER__*/

#endif /* __CHEBY__HYDRA_SUPERVISOR_REGS__H__ */
