-- Do not edit.  Generated by cheby 1.6.dev0 using these options:
--  -i fip_urv_regs.cheby --gen-hdl fip_urv_regs.vhd
-- Generated on Wed Apr 19 13:27:09 2023 by tgingold


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

package fip_urv_regs_pkg is
  type t_app_master_out is record
    cr_sys_rst       : std_logic;
    cr_cpu_rst       : std_logic;
    mailboxes_mboxout : std_logic_vector(31 downto 0);
    mailboxes_mboxout_wr : std_logic;
    mailboxes_mboxin_rd : std_logic;
  end record t_app_master_out;
  subtype t_app_slave_in is t_app_master_out;

  type t_app_slave_out is record
    sr_fault         : std_logic;
    reset_cause      : std_logic_vector(31 downto 0);
    iram_ecc_se      : std_logic_vector(31 downto 0);
    iram_scrub_cycle : std_logic_vector(15 downto 0);
    iram_scrub_se    : std_logic_vector(31 downto 0);
    iram_scrub_de_last : std_logic_vector(15 downto 0);
    dram_ecc_se      : std_logic_vector(31 downto 0);
    dram_scrub_cycle : std_logic_vector(15 downto 0);
    dram_scrub_se    : std_logic_vector(31 downto 0);
    dram_scrub_de_last : std_logic_vector(15 downto 0);
    scrub_cfg_iram_en : std_logic;
    scrub_cfg_dram_en : std_logic;
    nbr_cpu_fault    : std_logic_vector(31 downto 0);
    mailboxes_mboxout : std_logic_vector(31 downto 0);
    mailboxes_mboxin : std_logic_vector(31 downto 0);
    mailboxes_status_mbin : std_logic;
    mailboxes_status_mbout : std_logic;
  end record t_app_slave_out;
  subtype t_app_master_in is t_app_slave_out;

  type t_app_master_out_array is array(natural range <>) of
    t_app_master_out;
  subtype t_app_slave_in_array is t_app_master_out_array;

  type t_app_master_in_array is array(natural range <>) of
    t_app_master_in;
  subtype t_app_slave_out_array is t_app_master_in_array;

end fip_urv_regs_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.fip_urv_regs_pkg.all;

entity fip_urv_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- time stamp for versionning
    version_i            : in    std_logic_vector(31 downto 0);

    -- RAM size configuration
    -- IRAM size of app0 cpu (size = 1<<(n+8))
    config_ram_app0_iram_i : in    std_logic_vector(3 downto 0);
    -- DRAM size of app0 cpu (size = 1<<(n+8))
    config_ram_app0_dram_i : in    std_logic_vector(3 downto 0);
    -- IRAM size of mgmt cpu (size = 1<<(n+8))
    config_ram_mgmt_iram_i : in    std_logic_vector(3 downto 0);
    -- DRAM size of mgmt cpu (size = 1<<(n+8))
    config_ram_mgmt_dram_i : in    std_logic_vector(3 downto 0);

    -- NanoFIP variables size
    fip_var_length_o     : out   std_logic_vector(2 downto 0);

    -- Status bits from NanoFIP
    -- Set by HW when var1 is ready to be read.
    -- Cleared when nanofip is receiving it.
    -- Cleared when the software is reading it.
    fip_status_var1_rdy_i : in    std_logic;
    -- Set by HW when var3 can be written.
    -- Cleared when nanofip is transmitting it or when fip_var3.clr is set.
    -- The SW must wait for it before writting var3
    fip_status_var3_rdy_i : in    std_logic;

    -- Set access to var 1
    fip_var1_acc_o       : out   std_logic;

    -- Set access to var 3
    -- Tell nanofip var3 is being written
    fip_var3_acc_o       : out   std_logic;
    -- Clear the sticky var3_rdy
    fip_var3_clr_i       : in    std_logic;
    fip_var3_clr_o       : out   std_logic;
    fip_var3_wr_o        : out   std_logic;

    -- Number of worldfip errors; write to clear
    fip_err_i            : in    std_logic_vector(31 downto 0);
    fip_err_o            : out   std_logic_vector(31 downto 0);
    fip_err_wr_o         : out   std_logic;

    -- led
    leds_val_o           : out   std_logic_vector(3 downto 0);

    -- Value of the servmod lines for boards
    servmod_in_line_i    : in    std_logic_vector(7 downto 0);

    -- Output of the servmod lines for boards (if dir is 1)
    servmod_out_line_o   : out   std_logic_vector(7 downto 0);

    -- Servmod control lines
    -- servmod direction 0: input; 1: output
    servmod_ctrl_dir_o   : out   std_logic;

    -- Status lines for PSU
    psu_stat_pres_i      : in    std_logic_vector(1 downto 0);

    -- Control lines for PSU
    psu_ctrl_pwr_cyc_req_o : out   std_logic_vector(1 downto 0);

    -- Restart the fip urv (write 0x8e51a610)
    restart_o            : out   std_logic_vector(31 downto 0);
    restart_wr_o         : out   std_logic;

    -- RAM initialization on cpu reset
    -- Initialize iram from the source
    restart_cfg_iram_copy_o : out   std_logic;
    -- Clear dram (requires iram_copy).
    restart_cfg_dram_clear_o : out   std_logic;
    -- Add ECC errors on the last four words.  For testing
    restart_cfg_iram_err_o : out   std_logic;
    -- Specify IRAM source (eNVM:0, SPI:1)
    restart_cfg_iram_src_o : out   std_logic;
    -- start page for IRAM
    restart_cfg_iram_page_o : out   std_logic_vector(7 downto 0);
    -- start page for IRAM source
    restart_cfg_src_page_o : out   std_logic_vector(7 downto 0);

    -- Number of reset
    reset_count_i        : in    std_logic_vector(31 downto 0);

    -- Switch off Monimod power
    monimod_shdn_val_o   : out   std_logic;

    -- Fan tray control
    fan_ctrl_io0_o       : out   std_logic;
    fan_ctrl_io1_o       : out   std_logic;
    fan_ctrl_rstn_o      : out   std_logic;

    -- Tie to 0 i2c bus (to prevent powering through io)
    i2c_off_monimod_o    : out   std_logic;
    i2c_off_fantray_o    : out   std_logic;
    app_i                : in    t_app_master_in_array(1 downto 0);
    app_o                : out   t_app_master_out_array(1 downto 0);

    -- REG pins
    boards_0_pins_i      : in    std_logic_vector(31 downto 0);

    -- REG pins
    boards_1_pins_i      : in    std_logic_vector(31 downto 0);

    -- REG pins
    boards_2_pins_i      : in    std_logic_vector(31 downto 0);

    -- REG pins
    boards_3_pins_i      : in    std_logic_vector(31 downto 0);

    -- REG pins
    boards_4_pins_i      : in    std_logic_vector(31 downto 0);

    -- REG pins
    boards_5_pins_i      : in    std_logic_vector(31 downto 0);

    -- REG pins
    boards_6_pins_i      : in    std_logic_vector(31 downto 0);

    -- REG pins
    boards_7_pins_i      : in    std_logic_vector(31 downto 0);

    -- Number of ECC correctable errors for ram
    shmem_regs_ram_ecc_se_i : in    std_logic_vector(31 downto 0);

    -- RAM scrubber cycle number.
    shmem_regs_ram_scrub_cycle_i : in    std_logic_vector(15 downto 0);

    -- Number of ECC corrected errors by scrubber in ram
    shmem_regs_ram_scrub_se_i : in    std_logic_vector(31 downto 0);

    -- Number of ECC uncorrected errors by scrubber in iram during the last scrubber cycle.  Saturate.

    shmem_regs_ram_scrub_de_last_i : in    std_logic_vector(15 downto 0);

    -- configuration of scrubbers
    -- Write 1 to enable ram scrubber (cannot be disabled)
    shmem_regs_scrub_cfg_ram_en_i : in    std_logic;
    shmem_regs_scrub_cfg_ram_en_o : out   std_logic;
    shmem_regs_scrub_cfg_wr_o : out   std_logic;

    -- Maximum number of cycles between a scrub
    shmem_regs_ram_scrub_period_o : out   std_logic_vector(15 downto 0);

    -- ECC bits to corrupt
    shmem_regs_ecc_mask_o : out   std_logic_vector(7 downto 0);

    -- i2c interfaces for monitors
    i2c_i                : in    t_wishbone_master_in;
    i2c_o                : out   t_wishbone_master_out;

    -- flash
    spi_i                : in    t_wishbone_master_in;
    spi_o                : out   t_wishbone_master_out;

    -- NanoFIP internal memory/registers
    fip_reg_i            : in    t_wishbone_master_in;
    fip_reg_o            : out   t_wishbone_master_out;

    -- Shared memory between app and mgmt urv
    sh_mem_i             : in    t_wishbone_master_in;
    sh_mem_o             : out   t_wishbone_master_out;

    -- Memory of the app urv
    app0_mem_i           : in    t_wishbone_master_in;
    app0_mem_o           : out   t_wishbone_master_out;

    -- Memory of the app urv
    app1_mem_i           : in    t_wishbone_master_in;
    app1_mem_o           : out   t_wishbone_master_out;

    -- Igloo2 ENVM
    envm_i               : in    t_wishbone_master_in;
    envm_o               : out   t_wishbone_master_out
  );
end fip_urv_regs;

architecture syn of fip_urv_regs is
  signal adr_int                        : std_logic_vector(20 downto 2);
  signal rd_req_int                     : std_logic;
  signal wr_req_int                     : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal fip_var_length_reg             : std_logic_vector(2 downto 0);
  signal fip_var_wreq                   : std_logic;
  signal fip_var_wack                   : std_logic;
  signal fip_var1_acc_reg               : std_logic;
  signal fip_var1_wreq                  : std_logic;
  signal fip_var1_wack                  : std_logic;
  signal fip_var3_acc_reg               : std_logic;
  signal fip_var3_wreq                  : std_logic;
  signal fip_var3_wack                  : std_logic;
  signal fip_err_wreq                   : std_logic;
  signal leds_val_reg                   : std_logic_vector(3 downto 0);
  signal leds_wreq                      : std_logic;
  signal leds_wack                      : std_logic;
  signal servmod_out_line_reg           : std_logic_vector(7 downto 0);
  signal servmod_out_wreq               : std_logic;
  signal servmod_out_wack               : std_logic;
  signal servmod_ctrl_dir_reg           : std_logic;
  signal servmod_ctrl_wreq              : std_logic;
  signal servmod_ctrl_wack              : std_logic;
  signal psu_ctrl_pwr_cyc_req_reg       : std_logic_vector(1 downto 0);
  signal psu_ctrl_wreq                  : std_logic;
  signal psu_ctrl_wack                  : std_logic;
  signal restart_wreq                   : std_logic;
  signal restart_cfg_iram_copy_reg      : std_logic;
  signal restart_cfg_dram_clear_reg     : std_logic;
  signal restart_cfg_iram_err_reg       : std_logic;
  signal restart_cfg_iram_src_reg       : std_logic;
  signal restart_cfg_iram_page_reg      : std_logic_vector(7 downto 0);
  signal restart_cfg_src_page_reg       : std_logic_vector(7 downto 0);
  signal restart_cfg_wreq               : std_logic;
  signal restart_cfg_wack               : std_logic;
  signal monimod_shdn_val_reg           : std_logic;
  signal monimod_shdn_wreq              : std_logic;
  signal monimod_shdn_wack              : std_logic;
  signal fan_ctrl_io0_reg               : std_logic;
  signal fan_ctrl_io1_reg               : std_logic;
  signal fan_ctrl_rstn_reg              : std_logic;
  signal fan_ctrl_wreq                  : std_logic;
  signal fan_ctrl_wack                  : std_logic;
  signal i2c_off_monimod_reg            : std_logic;
  signal i2c_off_fantray_reg            : std_logic;
  signal i2c_off_wreq                   : std_logic;
  signal i2c_off_wack                   : std_logic;
  signal app_0_cr_sys_rst_reg           : std_logic;
  signal app_0_cr_cpu_rst_reg           : std_logic;
  signal app_0_cr_wreq                  : std_logic;
  signal app_0_cr_wack                  : std_logic;
  signal app_0_mailboxes_mboxout_wreq   : std_logic;
  signal app_1_cr_sys_rst_reg           : std_logic;
  signal app_1_cr_cpu_rst_reg           : std_logic;
  signal app_1_cr_wreq                  : std_logic;
  signal app_1_cr_wack                  : std_logic;
  signal app_1_mailboxes_mboxout_wreq   : std_logic;
  signal shmem_regs_scrub_cfg_wreq      : std_logic;
  signal shmem_regs_ram_scrub_period_reg : std_logic_vector(15 downto 0);
  signal shmem_regs_ram_scrub_period_wreq : std_logic;
  signal shmem_regs_ram_scrub_period_wack : std_logic;
  signal shmem_regs_ecc_mask_reg        : std_logic_vector(7 downto 0);
  signal shmem_regs_ecc_mask_wreq       : std_logic;
  signal shmem_regs_ecc_mask_wack       : std_logic;
  signal i2c_re                         : std_logic;
  signal i2c_we                         : std_logic;
  signal i2c_wt                         : std_logic;
  signal i2c_rt                         : std_logic;
  signal i2c_tr                         : std_logic;
  signal i2c_wack                       : std_logic;
  signal i2c_rack                       : std_logic;
  signal spi_re                         : std_logic;
  signal spi_we                         : std_logic;
  signal spi_wt                         : std_logic;
  signal spi_rt                         : std_logic;
  signal spi_tr                         : std_logic;
  signal spi_wack                       : std_logic;
  signal spi_rack                       : std_logic;
  signal fip_reg_re                     : std_logic;
  signal fip_reg_we                     : std_logic;
  signal fip_reg_wt                     : std_logic;
  signal fip_reg_rt                     : std_logic;
  signal fip_reg_tr                     : std_logic;
  signal fip_reg_wack                   : std_logic;
  signal fip_reg_rack                   : std_logic;
  signal sh_mem_re                      : std_logic;
  signal sh_mem_we                      : std_logic;
  signal sh_mem_wt                      : std_logic;
  signal sh_mem_rt                      : std_logic;
  signal sh_mem_tr                      : std_logic;
  signal sh_mem_wack                    : std_logic;
  signal sh_mem_rack                    : std_logic;
  signal app0_mem_re                    : std_logic;
  signal app0_mem_we                    : std_logic;
  signal app0_mem_wt                    : std_logic;
  signal app0_mem_rt                    : std_logic;
  signal app0_mem_tr                    : std_logic;
  signal app0_mem_wack                  : std_logic;
  signal app0_mem_rack                  : std_logic;
  signal app1_mem_re                    : std_logic;
  signal app1_mem_we                    : std_logic;
  signal app1_mem_wt                    : std_logic;
  signal app1_mem_rt                    : std_logic;
  signal app1_mem_tr                    : std_logic;
  signal app1_mem_wack                  : std_logic;
  signal app1_mem_rack                  : std_logic;
  signal envm_re                        : std_logic;
  signal envm_we                        : std_logic;
  signal envm_wt                        : std_logic;
  signal envm_rt                        : std_logic;
  signal envm_tr                        : std_logic;
  signal envm_wack                      : std_logic;
  signal envm_rack                      : std_logic;
  signal rd_ack_d0                      : std_logic;
  signal rd_dat_d0                      : std_logic_vector(31 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(20 downto 2);
  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
  signal wr_sel_d0                      : std_logic_vector(3 downto 0);
begin

  -- WB decode signals
  adr_int <= wb_i.adr(20 downto 2);
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_req_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- pipelining for wr-in+rd-out
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack_int <= '0';
        wr_req_d0 <= '0';
      else
        rd_ack_int <= rd_ack_d0;
        wb_o.dat <= rd_dat_d0;
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat;
        wr_sel_d0 <= wb_i.sel;
      end if;
    end if;
  end process;

  -- Register version

  -- Register config_ram

  -- Register fip_var
  fip_var_length_o <= fip_var_length_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fip_var_length_reg <= "001";
        fip_var_wack <= '0';
      else
        if fip_var_wreq = '1' then
          fip_var_length_reg <= wr_dat_d0(2 downto 0);
        end if;
        fip_var_wack <= fip_var_wreq;
      end if;
    end if;
  end process;

  -- Register fip_status

  -- Register fip_var1
  fip_var1_acc_o <= fip_var1_acc_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fip_var1_acc_reg <= '0';
        fip_var1_wack <= '0';
      else
        if fip_var1_wreq = '1' then
          fip_var1_acc_reg <= wr_dat_d0(0);
        end if;
        fip_var1_wack <= fip_var1_wreq;
      end if;
    end if;
  end process;

  -- Register fip_var3
  fip_var3_acc_o <= fip_var3_acc_reg;
  fip_var3_clr_o <= wr_dat_d0(1);
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fip_var3_acc_reg <= '0';
        fip_var3_wack <= '0';
      else
        if fip_var3_wreq = '1' then
          fip_var3_acc_reg <= wr_dat_d0(0);
        end if;
        fip_var3_wack <= fip_var3_wreq;
      end if;
    end if;
  end process;
  fip_var3_wr_o <= fip_var3_wack;

  -- Register fip_err
  fip_err_o <= wr_dat_d0;
  fip_err_wr_o <= fip_err_wreq;

  -- Register leds
  leds_val_o <= leds_val_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        leds_val_reg <= "0000";
        leds_wack <= '0';
      else
        if leds_wreq = '1' then
          leds_val_reg <= wr_dat_d0(3 downto 0);
        end if;
        leds_wack <= leds_wreq;
      end if;
    end if;
  end process;

  -- Register servmod_in

  -- Register servmod_out
  servmod_out_line_o <= servmod_out_line_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        servmod_out_line_reg <= "00000000";
        servmod_out_wack <= '0';
      else
        if servmod_out_wreq = '1' then
          servmod_out_line_reg <= wr_dat_d0(7 downto 0);
        end if;
        servmod_out_wack <= servmod_out_wreq;
      end if;
    end if;
  end process;

  -- Register servmod_ctrl
  servmod_ctrl_dir_o <= servmod_ctrl_dir_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        servmod_ctrl_dir_reg <= '0';
        servmod_ctrl_wack <= '0';
      else
        if servmod_ctrl_wreq = '1' then
          servmod_ctrl_dir_reg <= wr_dat_d0(0);
        end if;
        servmod_ctrl_wack <= servmod_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register psu_stat

  -- Register psu_ctrl
  psu_ctrl_pwr_cyc_req_o <= psu_ctrl_pwr_cyc_req_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        psu_ctrl_pwr_cyc_req_reg <= "00";
        psu_ctrl_wack <= '0';
      else
        if psu_ctrl_wreq = '1' then
          psu_ctrl_pwr_cyc_req_reg <= wr_dat_d0(1 downto 0);
        end if;
        psu_ctrl_wack <= psu_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register restart
  restart_o <= wr_dat_d0;
  restart_wr_o <= restart_wreq;

  -- Register restart_cfg
  restart_cfg_iram_copy_o <= restart_cfg_iram_copy_reg;
  restart_cfg_dram_clear_o <= restart_cfg_dram_clear_reg;
  restart_cfg_iram_err_o <= restart_cfg_iram_err_reg;
  restart_cfg_iram_src_o <= restart_cfg_iram_src_reg;
  restart_cfg_iram_page_o <= restart_cfg_iram_page_reg;
  restart_cfg_src_page_o <= restart_cfg_src_page_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        restart_cfg_iram_copy_reg <= '1';
        restart_cfg_dram_clear_reg <= '1';
        restart_cfg_iram_err_reg <= '0';
        restart_cfg_iram_src_reg <= '0';
        restart_cfg_iram_page_reg <= "00000000";
        restart_cfg_src_page_reg <= "00000000";
        restart_cfg_wack <= '0';
      else
        if restart_cfg_wreq = '1' then
          restart_cfg_iram_copy_reg <= wr_dat_d0(0);
          restart_cfg_dram_clear_reg <= wr_dat_d0(1);
          restart_cfg_iram_err_reg <= wr_dat_d0(2);
          restart_cfg_iram_src_reg <= wr_dat_d0(3);
          restart_cfg_iram_page_reg <= wr_dat_d0(15 downto 8);
          restart_cfg_src_page_reg <= wr_dat_d0(23 downto 16);
        end if;
        restart_cfg_wack <= restart_cfg_wreq;
      end if;
    end if;
  end process;

  -- Register reset_count

  -- Register monimod_shdn
  monimod_shdn_val_o <= monimod_shdn_val_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        monimod_shdn_val_reg <= '0';
        monimod_shdn_wack <= '0';
      else
        if monimod_shdn_wreq = '1' then
          monimod_shdn_val_reg <= wr_dat_d0(0);
        end if;
        monimod_shdn_wack <= monimod_shdn_wreq;
      end if;
    end if;
  end process;

  -- Register fan_ctrl
  fan_ctrl_io0_o <= fan_ctrl_io0_reg;
  fan_ctrl_io1_o <= fan_ctrl_io1_reg;
  fan_ctrl_rstn_o <= fan_ctrl_rstn_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fan_ctrl_io0_reg <= '0';
        fan_ctrl_io1_reg <= '0';
        fan_ctrl_rstn_reg <= '1';
        fan_ctrl_wack <= '0';
      else
        if fan_ctrl_wreq = '1' then
          fan_ctrl_io0_reg <= wr_dat_d0(0);
          fan_ctrl_io1_reg <= wr_dat_d0(1);
          fan_ctrl_rstn_reg <= wr_dat_d0(2);
        end if;
        fan_ctrl_wack <= fan_ctrl_wreq;
      end if;
    end if;
  end process;

  -- Register i2c_off
  i2c_off_monimod_o <= i2c_off_monimod_reg;
  i2c_off_fantray_o <= i2c_off_fantray_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        i2c_off_monimod_reg <= '0';
        i2c_off_fantray_reg <= '0';
        i2c_off_wack <= '0';
      else
        if i2c_off_wreq = '1' then
          i2c_off_monimod_reg <= wr_dat_d0(0);
          i2c_off_fantray_reg <= wr_dat_d0(1);
        end if;
        i2c_off_wack <= i2c_off_wreq;
      end if;
    end if;
  end process;

  -- Register app_0_cr
  app_o(0).cr_sys_rst <= app_0_cr_sys_rst_reg;
  app_o(0).cr_cpu_rst <= app_0_cr_cpu_rst_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        app_0_cr_sys_rst_reg <= '0';
        app_0_cr_cpu_rst_reg <= '1';
        app_0_cr_wack <= '0';
      else
        if app_0_cr_wreq = '1' then
          app_0_cr_sys_rst_reg <= wr_dat_d0(0);
          app_0_cr_cpu_rst_reg <= wr_dat_d0(1);
        end if;
        app_0_cr_wack <= app_0_cr_wreq;
      end if;
    end if;
  end process;

  -- Register app_0_sr

  -- Register app_0_reset_cause

  -- Register app_0_iram_ecc_se

  -- Register app_0_iram_scrub_cycle

  -- Register app_0_iram_scrub_se

  -- Register app_0_iram_scrub_de_last

  -- Register app_0_dram_ecc_se

  -- Register app_0_dram_scrub_cycle

  -- Register app_0_dram_scrub_se

  -- Register app_0_dram_scrub_de_last

  -- Register app_0_scrub_cfg

  -- Register app_0_nbr_cpu_fault

  -- Register app_0_mailboxes_mboxout
  app_o(0).mailboxes_mboxout <= wr_dat_d0;
  app_o(0).mailboxes_mboxout_wr <= app_0_mailboxes_mboxout_wreq;

  -- Register app_0_mailboxes_mboxin

  -- Register app_0_mailboxes_status

  -- Register app_1_cr
  app_o(1).cr_sys_rst <= app_1_cr_sys_rst_reg;
  app_o(1).cr_cpu_rst <= app_1_cr_cpu_rst_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        app_1_cr_sys_rst_reg <= '0';
        app_1_cr_cpu_rst_reg <= '1';
        app_1_cr_wack <= '0';
      else
        if app_1_cr_wreq = '1' then
          app_1_cr_sys_rst_reg <= wr_dat_d0(0);
          app_1_cr_cpu_rst_reg <= wr_dat_d0(1);
        end if;
        app_1_cr_wack <= app_1_cr_wreq;
      end if;
    end if;
  end process;

  -- Register app_1_sr

  -- Register app_1_reset_cause

  -- Register app_1_iram_ecc_se

  -- Register app_1_iram_scrub_cycle

  -- Register app_1_iram_scrub_se

  -- Register app_1_iram_scrub_de_last

  -- Register app_1_dram_ecc_se

  -- Register app_1_dram_scrub_cycle

  -- Register app_1_dram_scrub_se

  -- Register app_1_dram_scrub_de_last

  -- Register app_1_scrub_cfg

  -- Register app_1_nbr_cpu_fault

  -- Register app_1_mailboxes_mboxout
  app_o(1).mailboxes_mboxout <= wr_dat_d0;
  app_o(1).mailboxes_mboxout_wr <= app_1_mailboxes_mboxout_wreq;

  -- Register app_1_mailboxes_mboxin

  -- Register app_1_mailboxes_status

  -- Register boards_0_pins

  -- Register boards_1_pins

  -- Register boards_2_pins

  -- Register boards_3_pins

  -- Register boards_4_pins

  -- Register boards_5_pins

  -- Register boards_6_pins

  -- Register boards_7_pins

  -- Register shmem_regs_ram_ecc_se

  -- Register shmem_regs_ram_scrub_cycle

  -- Register shmem_regs_ram_scrub_se

  -- Register shmem_regs_ram_scrub_de_last

  -- Register shmem_regs_scrub_cfg
  shmem_regs_scrub_cfg_ram_en_o <= wr_dat_d0(0);
  shmem_regs_scrub_cfg_wr_o <= shmem_regs_scrub_cfg_wreq;

  -- Register shmem_regs_ram_scrub_period
  shmem_regs_ram_scrub_period_o <= shmem_regs_ram_scrub_period_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        shmem_regs_ram_scrub_period_reg <= "0000011111111111";
        shmem_regs_ram_scrub_period_wack <= '0';
      else
        if shmem_regs_ram_scrub_period_wreq = '1' then
          shmem_regs_ram_scrub_period_reg <= wr_dat_d0(15 downto 0);
        end if;
        shmem_regs_ram_scrub_period_wack <= shmem_regs_ram_scrub_period_wreq;
      end if;
    end if;
  end process;

  -- Register shmem_regs_ecc_mask
  shmem_regs_ecc_mask_o <= shmem_regs_ecc_mask_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        shmem_regs_ecc_mask_reg <= "00000000";
        shmem_regs_ecc_mask_wack <= '0';
      else
        if shmem_regs_ecc_mask_wreq = '1' then
          shmem_regs_ecc_mask_reg <= wr_dat_d0(7 downto 0);
        end if;
        shmem_regs_ecc_mask_wack <= shmem_regs_ecc_mask_wreq;
      end if;
    end if;
  end process;

  -- Interface i2c
  i2c_tr <= i2c_wt or i2c_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        i2c_rt <= '0';
        i2c_wt <= '0';
      else
        i2c_rt <= (i2c_rt or i2c_re) and not i2c_rack;
        i2c_wt <= (i2c_wt or i2c_we) and not i2c_wack;
      end if;
    end if;
  end process;
  i2c_o.cyc <= i2c_tr;
  i2c_o.stb <= i2c_tr;
  i2c_wack <= i2c_i.ack and i2c_wt;
  i2c_rack <= i2c_i.ack and i2c_rt;
  i2c_o.adr <= ((26 downto 0 => '0') & adr_int(4 downto 2)) & (1 downto 0 => '0');
  i2c_o.sel <= wr_sel_d0;
  i2c_o.we <= i2c_wt;
  i2c_o.dat <= wr_dat_d0;

  -- Interface spi
  spi_tr <= spi_wt or spi_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        spi_rt <= '0';
        spi_wt <= '0';
      else
        spi_rt <= (spi_rt or spi_re) and not spi_rack;
        spi_wt <= (spi_wt or spi_we) and not spi_wack;
      end if;
    end if;
  end process;
  spi_o.cyc <= spi_tr;
  spi_o.stb <= spi_tr;
  spi_wack <= spi_i.ack and spi_wt;
  spi_rack <= spi_i.ack and spi_rt;
  spi_o.adr <= ((26 downto 0 => '0') & adr_int(4 downto 2)) & (1 downto 0 => '0');
  spi_o.sel <= wr_sel_d0;
  spi_o.we <= spi_wt;
  spi_o.dat <= wr_dat_d0;

  -- Interface fip_reg
  fip_reg_tr <= fip_reg_wt or fip_reg_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        fip_reg_rt <= '0';
        fip_reg_wt <= '0';
      else
        fip_reg_rt <= (fip_reg_rt or fip_reg_re) and not fip_reg_rack;
        fip_reg_wt <= (fip_reg_wt or fip_reg_we) and not fip_reg_wack;
      end if;
    end if;
  end process;
  fip_reg_o.cyc <= fip_reg_tr;
  fip_reg_o.stb <= fip_reg_tr;
  fip_reg_wack <= fip_reg_i.ack and fip_reg_wt;
  fip_reg_rack <= fip_reg_i.ack and fip_reg_rt;
  fip_reg_o.adr <= ((20 downto 0 => '0') & adr_int(10 downto 2)) & (1 downto 0 => '0');
  fip_reg_o.sel <= wr_sel_d0;
  fip_reg_o.we <= fip_reg_wt;
  fip_reg_o.dat <= wr_dat_d0;

  -- Interface sh_mem
  sh_mem_tr <= sh_mem_wt or sh_mem_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        sh_mem_rt <= '0';
        sh_mem_wt <= '0';
      else
        sh_mem_rt <= (sh_mem_rt or sh_mem_re) and not sh_mem_rack;
        sh_mem_wt <= (sh_mem_wt or sh_mem_we) and not sh_mem_wack;
      end if;
    end if;
  end process;
  sh_mem_o.cyc <= sh_mem_tr;
  sh_mem_o.stb <= sh_mem_tr;
  sh_mem_wack <= sh_mem_i.ack and sh_mem_wt;
  sh_mem_rack <= sh_mem_i.ack and sh_mem_rt;
  sh_mem_o.adr <= ((20 downto 0 => '0') & adr_int(10 downto 2)) & (1 downto 0 => '0');
  sh_mem_o.sel <= wr_sel_d0;
  sh_mem_o.we <= sh_mem_wt;
  sh_mem_o.dat <= wr_dat_d0;

  -- Interface app0_mem
  app0_mem_tr <= app0_mem_wt or app0_mem_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        app0_mem_rt <= '0';
        app0_mem_wt <= '0';
      else
        app0_mem_rt <= (app0_mem_rt or app0_mem_re) and not app0_mem_rack;
        app0_mem_wt <= (app0_mem_wt or app0_mem_we) and not app0_mem_wack;
      end if;
    end if;
  end process;
  app0_mem_o.cyc <= app0_mem_tr;
  app0_mem_o.stb <= app0_mem_tr;
  app0_mem_wack <= app0_mem_i.ack and app0_mem_wt;
  app0_mem_rack <= app0_mem_i.ack and app0_mem_rt;
  app0_mem_o.adr <= ((18 downto 0 => '0') & adr_int(12 downto 2)) & (1 downto 0 => '0');
  app0_mem_o.sel <= wr_sel_d0;
  app0_mem_o.we <= app0_mem_wt;
  app0_mem_o.dat <= wr_dat_d0;

  -- Interface app1_mem
  app1_mem_tr <= app1_mem_wt or app1_mem_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        app1_mem_rt <= '0';
        app1_mem_wt <= '0';
      else
        app1_mem_rt <= (app1_mem_rt or app1_mem_re) and not app1_mem_rack;
        app1_mem_wt <= (app1_mem_wt or app1_mem_we) and not app1_mem_wack;
      end if;
    end if;
  end process;
  app1_mem_o.cyc <= app1_mem_tr;
  app1_mem_o.stb <= app1_mem_tr;
  app1_mem_wack <= app1_mem_i.ack and app1_mem_wt;
  app1_mem_rack <= app1_mem_i.ack and app1_mem_rt;
  app1_mem_o.adr <= ((18 downto 0 => '0') & adr_int(12 downto 2)) & (1 downto 0 => '0');
  app1_mem_o.sel <= wr_sel_d0;
  app1_mem_o.we <= app1_mem_wt;
  app1_mem_o.dat <= wr_dat_d0;

  -- Interface envm
  envm_tr <= envm_wt or envm_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        envm_rt <= '0';
        envm_wt <= '0';
      else
        envm_rt <= (envm_rt or envm_re) and not envm_rack;
        envm_wt <= (envm_wt or envm_we) and not envm_wack;
      end if;
    end if;
  end process;
  envm_o.cyc <= envm_tr;
  envm_o.stb <= envm_tr;
  envm_wack <= envm_i.ack and envm_wt;
  envm_rack <= envm_i.ack and envm_rt;
  envm_o.adr <= ((11 downto 0 => '0') & adr_int(19 downto 2)) & (1 downto 0 => '0');
  envm_o.sel <= wr_sel_d0;
  envm_o.we <= envm_wt;
  envm_o.dat <= wr_dat_d0;

  -- Process for write requests.
  process (wr_adr_d0, wr_req_d0, fip_var_wack, fip_var1_wack, fip_var3_wack,
           leds_wack, servmod_out_wack, servmod_ctrl_wack, psu_ctrl_wack,
           restart_cfg_wack, monimod_shdn_wack, fan_ctrl_wack, i2c_off_wack,
           app_0_cr_wack, app_1_cr_wack, shmem_regs_ram_scrub_period_wack,
           shmem_regs_ecc_mask_wack, i2c_wack, spi_wack, fip_reg_wack, sh_mem_wack,
           app0_mem_wack, app1_mem_wack, envm_wack) begin
    fip_var_wreq <= '0';
    fip_var1_wreq <= '0';
    fip_var3_wreq <= '0';
    fip_err_wreq <= '0';
    leds_wreq <= '0';
    servmod_out_wreq <= '0';
    servmod_ctrl_wreq <= '0';
    psu_ctrl_wreq <= '0';
    restart_wreq <= '0';
    restart_cfg_wreq <= '0';
    monimod_shdn_wreq <= '0';
    fan_ctrl_wreq <= '0';
    i2c_off_wreq <= '0';
    app_0_cr_wreq <= '0';
    app_0_mailboxes_mboxout_wreq <= '0';
    app_1_cr_wreq <= '0';
    app_1_mailboxes_mboxout_wreq <= '0';
    shmem_regs_scrub_cfg_wreq <= '0';
    shmem_regs_ram_scrub_period_wreq <= '0';
    shmem_regs_ecc_mask_wreq <= '0';
    i2c_we <= '0';
    spi_we <= '0';
    fip_reg_we <= '0';
    sh_mem_we <= '0';
    app0_mem_we <= '0';
    app1_mem_we <= '0';
    envm_we <= '0';
    case wr_adr_d0(20 downto 20) is
    when "0" =>
      case wr_adr_d0(19 downto 13) is
      when "0000000" =>
        case wr_adr_d0(12 downto 11) is
        when "00" =>
          case wr_adr_d0(10 downto 5) is
          when "000000" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg version
              wr_ack_int <= wr_req_d0;
            when "001" =>
              -- Reg config_ram
              wr_ack_int <= wr_req_d0;
            when "010" =>
              -- Reg fip_var
              fip_var_wreq <= wr_req_d0;
              wr_ack_int <= fip_var_wack;
            when "011" =>
              -- Reg fip_status
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg fip_var1
              fip_var1_wreq <= wr_req_d0;
              wr_ack_int <= fip_var1_wack;
            when "101" =>
              -- Reg fip_var3
              fip_var3_wreq <= wr_req_d0;
              wr_ack_int <= fip_var3_wack;
            when "110" =>
              -- Reg fip_err
              fip_err_wreq <= wr_req_d0;
              wr_ack_int <= wr_req_d0;
            when "111" =>
              -- Reg leds
              leds_wreq <= wr_req_d0;
              wr_ack_int <= leds_wack;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "000001" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg servmod_in
              wr_ack_int <= wr_req_d0;
            when "001" =>
              -- Reg servmod_out
              servmod_out_wreq <= wr_req_d0;
              wr_ack_int <= servmod_out_wack;
            when "010" =>
              -- Reg servmod_ctrl
              servmod_ctrl_wreq <= wr_req_d0;
              wr_ack_int <= servmod_ctrl_wack;
            when "011" =>
              -- Reg psu_stat
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg psu_ctrl
              psu_ctrl_wreq <= wr_req_d0;
              wr_ack_int <= psu_ctrl_wack;
            when "101" =>
              -- Reg restart
              restart_wreq <= wr_req_d0;
              wr_ack_int <= wr_req_d0;
            when "110" =>
              -- Reg restart_cfg
              restart_cfg_wreq <= wr_req_d0;
              wr_ack_int <= restart_cfg_wack;
            when "111" =>
              -- Reg reset_count
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "000010" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg monimod_shdn
              monimod_shdn_wreq <= wr_req_d0;
              wr_ack_int <= monimod_shdn_wack;
            when "001" =>
              -- Reg fan_ctrl
              fan_ctrl_wreq <= wr_req_d0;
              wr_ack_int <= fan_ctrl_wack;
            when "010" =>
              -- Reg i2c_off
              i2c_off_wreq <= wr_req_d0;
              wr_ack_int <= i2c_off_wack;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "001000" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg app_0_cr
              app_0_cr_wreq <= wr_req_d0;
              wr_ack_int <= app_0_cr_wack;
            when "001" =>
              -- Reg app_0_sr
              wr_ack_int <= wr_req_d0;
            when "010" =>
              -- Reg app_0_reset_cause
              wr_ack_int <= wr_req_d0;
            when "011" =>
              -- Reg app_0_iram_ecc_se
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg app_0_iram_scrub_cycle
              wr_ack_int <= wr_req_d0;
            when "101" =>
              -- Reg app_0_iram_scrub_se
              wr_ack_int <= wr_req_d0;
            when "110" =>
              -- Reg app_0_iram_scrub_de_last
              wr_ack_int <= wr_req_d0;
            when "111" =>
              -- Reg app_0_dram_ecc_se
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "001001" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg app_0_dram_scrub_cycle
              wr_ack_int <= wr_req_d0;
            when "001" =>
              -- Reg app_0_dram_scrub_se
              wr_ack_int <= wr_req_d0;
            when "010" =>
              -- Reg app_0_dram_scrub_de_last
              wr_ack_int <= wr_req_d0;
            when "011" =>
              -- Reg app_0_scrub_cfg
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg app_0_nbr_cpu_fault
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "001010" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg app_0_mailboxes_mboxout
              app_0_mailboxes_mboxout_wreq <= wr_req_d0;
              wr_ack_int <= wr_req_d0;
            when "001" =>
              -- Reg app_0_mailboxes_mboxin
              wr_ack_int <= wr_req_d0;
            when "010" =>
              -- Reg app_0_mailboxes_status
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg app_1_cr
              app_1_cr_wreq <= wr_req_d0;
              wr_ack_int <= app_1_cr_wack;
            when "101" =>
              -- Reg app_1_sr
              wr_ack_int <= wr_req_d0;
            when "110" =>
              -- Reg app_1_reset_cause
              wr_ack_int <= wr_req_d0;
            when "111" =>
              -- Reg app_1_iram_ecc_se
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "001011" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg app_1_iram_scrub_cycle
              wr_ack_int <= wr_req_d0;
            when "001" =>
              -- Reg app_1_iram_scrub_se
              wr_ack_int <= wr_req_d0;
            when "010" =>
              -- Reg app_1_iram_scrub_de_last
              wr_ack_int <= wr_req_d0;
            when "011" =>
              -- Reg app_1_dram_ecc_se
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg app_1_dram_scrub_cycle
              wr_ack_int <= wr_req_d0;
            when "101" =>
              -- Reg app_1_dram_scrub_se
              wr_ack_int <= wr_req_d0;
            when "110" =>
              -- Reg app_1_dram_scrub_de_last
              wr_ack_int <= wr_req_d0;
            when "111" =>
              -- Reg app_1_scrub_cfg
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "001100" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg app_1_nbr_cpu_fault
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg app_1_mailboxes_mboxout
              app_1_mailboxes_mboxout_wreq <= wr_req_d0;
              wr_ack_int <= wr_req_d0;
            when "101" =>
              -- Reg app_1_mailboxes_mboxin
              wr_ack_int <= wr_req_d0;
            when "110" =>
              -- Reg app_1_mailboxes_status
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "010000" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg boards_0_pins
              wr_ack_int <= wr_req_d0;
            when "001" =>
              -- Reg boards_1_pins
              wr_ack_int <= wr_req_d0;
            when "010" =>
              -- Reg boards_2_pins
              wr_ack_int <= wr_req_d0;
            when "011" =>
              -- Reg boards_3_pins
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg boards_4_pins
              wr_ack_int <= wr_req_d0;
            when "101" =>
              -- Reg boards_5_pins
              wr_ack_int <= wr_req_d0;
            when "110" =>
              -- Reg boards_6_pins
              wr_ack_int <= wr_req_d0;
            when "111" =>
              -- Reg boards_7_pins
              wr_ack_int <= wr_req_d0;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "010001" =>
            case wr_adr_d0(4 downto 2) is
            when "000" =>
              -- Reg shmem_regs_ram_ecc_se
              wr_ack_int <= wr_req_d0;
            when "001" =>
              -- Reg shmem_regs_ram_scrub_cycle
              wr_ack_int <= wr_req_d0;
            when "010" =>
              -- Reg shmem_regs_ram_scrub_se
              wr_ack_int <= wr_req_d0;
            when "011" =>
              -- Reg shmem_regs_ram_scrub_de_last
              wr_ack_int <= wr_req_d0;
            when "100" =>
              -- Reg shmem_regs_scrub_cfg
              shmem_regs_scrub_cfg_wreq <= wr_req_d0;
              wr_ack_int <= wr_req_d0;
            when "101" =>
              -- Reg shmem_regs_ram_scrub_period
              shmem_regs_ram_scrub_period_wreq <= wr_req_d0;
              wr_ack_int <= shmem_regs_ram_scrub_period_wack;
            when "110" =>
              -- Reg shmem_regs_ecc_mask
              shmem_regs_ecc_mask_wreq <= wr_req_d0;
              wr_ack_int <= shmem_regs_ecc_mask_wack;
            when others =>
              wr_ack_int <= wr_req_d0;
            end case;
          when "010010" =>
            -- Submap i2c
            i2c_we <= wr_req_d0;
            wr_ack_int <= i2c_wack;
          when "010011" =>
            -- Submap spi
            spi_we <= wr_req_d0;
            wr_ack_int <= spi_wack;
          when others =>
            wr_ack_int <= wr_req_d0;
          end case;
        when "01" =>
          -- Submap fip_reg
          fip_reg_we <= wr_req_d0;
          wr_ack_int <= fip_reg_wack;
        when "10" =>
          -- Submap sh_mem
          sh_mem_we <= wr_req_d0;
          wr_ack_int <= sh_mem_wack;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
      when "0000001" =>
        -- Submap app0_mem
        app0_mem_we <= wr_req_d0;
        wr_ack_int <= app0_mem_wack;
      when "0000010" =>
        -- Submap app1_mem
        app1_mem_we <= wr_req_d0;
        wr_ack_int <= app1_mem_wack;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when "1" =>
      -- Submap envm
      envm_we <= wr_req_d0;
      wr_ack_int <= envm_wack;
    when others =>
      wr_ack_int <= wr_req_d0;
    end case;
  end process;

  -- Process for read requests.
  process (adr_int, rd_req_int, version_i, config_ram_app0_iram_i,
           config_ram_app0_dram_i, config_ram_mgmt_iram_i,
           config_ram_mgmt_dram_i, fip_var_length_reg, fip_status_var1_rdy_i,
           fip_status_var3_rdy_i, fip_var1_acc_reg, fip_var3_acc_reg,
           fip_var3_clr_i, fip_err_i, leds_val_reg, servmod_in_line_i,
           servmod_ctrl_dir_reg, psu_stat_pres_i, psu_ctrl_pwr_cyc_req_reg,
           restart_cfg_iram_copy_reg, restart_cfg_dram_clear_reg,
           restart_cfg_iram_err_reg, restart_cfg_iram_src_reg,
           restart_cfg_iram_page_reg, restart_cfg_src_page_reg, reset_count_i,
           monimod_shdn_val_reg, fan_ctrl_io0_reg, fan_ctrl_io1_reg,
           fan_ctrl_rstn_reg, i2c_off_monimod_reg, i2c_off_fantray_reg,
           app_0_cr_sys_rst_reg, app_0_cr_cpu_rst_reg, app_i(0).sr_fault,
           app_i(0).reset_cause, app_i(0).iram_ecc_se,
           app_i(0).iram_scrub_cycle, app_i(0).iram_scrub_se,
           app_i(0).iram_scrub_de_last, app_i(0).dram_ecc_se,
           app_i(0).dram_scrub_cycle, app_i(0).dram_scrub_se,
           app_i(0).dram_scrub_de_last, app_i(0).scrub_cfg_iram_en,
           app_i(0).scrub_cfg_dram_en, app_i(0).nbr_cpu_fault,
           app_i(0).mailboxes_mboxout, app_i(0).mailboxes_mboxin,
           app_i(0).mailboxes_status_mbin, app_i(0).mailboxes_status_mbout,
           app_1_cr_sys_rst_reg, app_1_cr_cpu_rst_reg, app_i(1).sr_fault,
           app_i(1).reset_cause, app_i(1).iram_ecc_se,
           app_i(1).iram_scrub_cycle, app_i(1).iram_scrub_se,
           app_i(1).iram_scrub_de_last, app_i(1).dram_ecc_se,
           app_i(1).dram_scrub_cycle, app_i(1).dram_scrub_se,
           app_i(1).dram_scrub_de_last, app_i(1).scrub_cfg_iram_en,
           app_i(1).scrub_cfg_dram_en, app_i(1).nbr_cpu_fault,
           app_i(1).mailboxes_mboxout, app_i(1).mailboxes_mboxin,
           app_i(1).mailboxes_status_mbin, app_i(1).mailboxes_status_mbout,
           boards_0_pins_i, boards_1_pins_i, boards_2_pins_i, boards_3_pins_i,
           boards_4_pins_i, boards_5_pins_i, boards_6_pins_i, boards_7_pins_i,
           shmem_regs_ram_ecc_se_i, shmem_regs_ram_scrub_cycle_i,
           shmem_regs_ram_scrub_se_i, shmem_regs_ram_scrub_de_last_i,
           shmem_regs_scrub_cfg_ram_en_i, shmem_regs_ram_scrub_period_reg,
           shmem_regs_ecc_mask_reg, i2c_i.dat, i2c_rack, spi_i.dat, spi_rack,
           fip_reg_i.dat, fip_reg_rack, sh_mem_i.dat, sh_mem_rack, app0_mem_i.dat,
           app0_mem_rack, app1_mem_i.dat, app1_mem_rack, envm_i.dat, envm_rack) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    app_o(0).mailboxes_mboxin_rd <= '0';
    app_o(1).mailboxes_mboxin_rd <= '0';
    i2c_re <= '0';
    spi_re <= '0';
    fip_reg_re <= '0';
    sh_mem_re <= '0';
    app0_mem_re <= '0';
    app1_mem_re <= '0';
    envm_re <= '0';
    case adr_int(20 downto 20) is
    when "0" =>
      case adr_int(19 downto 13) is
      when "0000000" =>
        case adr_int(12 downto 11) is
        when "00" =>
          case adr_int(10 downto 5) is
          when "000000" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg version
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= version_i;
            when "001" =>
              -- Reg config_ram
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(3 downto 0) <= config_ram_app0_iram_i;
              rd_dat_d0(7 downto 4) <= config_ram_app0_dram_i;
              rd_dat_d0(23 downto 8) <= (others => '0');
              rd_dat_d0(27 downto 24) <= config_ram_mgmt_iram_i;
              rd_dat_d0(31 downto 28) <= config_ram_mgmt_dram_i;
            when "010" =>
              -- Reg fip_var
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(2 downto 0) <= fip_var_length_reg;
              rd_dat_d0(31 downto 3) <= (others => '0');
            when "011" =>
              -- Reg fip_status
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= fip_status_var1_rdy_i;
              rd_dat_d0(1) <= fip_status_var3_rdy_i;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when "100" =>
              -- Reg fip_var1
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= fip_var1_acc_reg;
              rd_dat_d0(31 downto 1) <= (others => '0');
            when "101" =>
              -- Reg fip_var3
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= fip_var3_acc_reg;
              rd_dat_d0(1) <= fip_var3_clr_i;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when "110" =>
              -- Reg fip_err
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= fip_err_i;
            when "111" =>
              -- Reg leds
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(3 downto 0) <= leds_val_reg;
              rd_dat_d0(31 downto 4) <= (others => '0');
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "000001" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg servmod_in
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(7 downto 0) <= servmod_in_line_i;
              rd_dat_d0(31 downto 8) <= (others => '0');
            when "001" =>
              -- Reg servmod_out
              rd_ack_d0 <= rd_req_int;
            when "010" =>
              -- Reg servmod_ctrl
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= servmod_ctrl_dir_reg;
              rd_dat_d0(31 downto 1) <= (others => '0');
            when "011" =>
              -- Reg psu_stat
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(1 downto 0) <= psu_stat_pres_i;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when "100" =>
              -- Reg psu_ctrl
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(1 downto 0) <= psu_ctrl_pwr_cyc_req_reg;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when "101" =>
              -- Reg restart
              rd_ack_d0 <= rd_req_int;
            when "110" =>
              -- Reg restart_cfg
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= restart_cfg_iram_copy_reg;
              rd_dat_d0(1) <= restart_cfg_dram_clear_reg;
              rd_dat_d0(2) <= restart_cfg_iram_err_reg;
              rd_dat_d0(3) <= restart_cfg_iram_src_reg;
              rd_dat_d0(7 downto 4) <= (others => '0');
              rd_dat_d0(15 downto 8) <= restart_cfg_iram_page_reg;
              rd_dat_d0(23 downto 16) <= restart_cfg_src_page_reg;
              rd_dat_d0(31 downto 24) <= (others => '0');
            when "111" =>
              -- Reg reset_count
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= reset_count_i;
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "000010" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg monimod_shdn
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= monimod_shdn_val_reg;
              rd_dat_d0(31 downto 1) <= (others => '0');
            when "001" =>
              -- Reg fan_ctrl
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= fan_ctrl_io0_reg;
              rd_dat_d0(1) <= fan_ctrl_io1_reg;
              rd_dat_d0(2) <= fan_ctrl_rstn_reg;
              rd_dat_d0(31 downto 3) <= (others => '0');
            when "010" =>
              -- Reg i2c_off
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= i2c_off_monimod_reg;
              rd_dat_d0(1) <= i2c_off_fantray_reg;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "001000" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg app_0_cr
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= app_0_cr_sys_rst_reg;
              rd_dat_d0(1) <= app_0_cr_cpu_rst_reg;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when "001" =>
              -- Reg app_0_sr
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= app_i(0).sr_fault;
              rd_dat_d0(31 downto 1) <= (others => '0');
            when "010" =>
              -- Reg app_0_reset_cause
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(0).reset_cause;
            when "011" =>
              -- Reg app_0_iram_ecc_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(0).iram_ecc_se;
            when "100" =>
              -- Reg app_0_iram_scrub_cycle
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= app_i(0).iram_scrub_cycle;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "101" =>
              -- Reg app_0_iram_scrub_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(0).iram_scrub_se;
            when "110" =>
              -- Reg app_0_iram_scrub_de_last
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= app_i(0).iram_scrub_de_last;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "111" =>
              -- Reg app_0_dram_ecc_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(0).dram_ecc_se;
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "001001" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg app_0_dram_scrub_cycle
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= app_i(0).dram_scrub_cycle;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "001" =>
              -- Reg app_0_dram_scrub_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(0).dram_scrub_se;
            when "010" =>
              -- Reg app_0_dram_scrub_de_last
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= app_i(0).dram_scrub_de_last;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "011" =>
              -- Reg app_0_scrub_cfg
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= app_i(0).scrub_cfg_iram_en;
              rd_dat_d0(1) <= app_i(0).scrub_cfg_dram_en;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when "100" =>
              -- Reg app_0_nbr_cpu_fault
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(0).nbr_cpu_fault;
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "001010" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg app_0_mailboxes_mboxout
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(0).mailboxes_mboxout;
            when "001" =>
              -- Reg app_0_mailboxes_mboxin
              app_o(0).mailboxes_mboxin_rd <= rd_req_int;
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(0).mailboxes_mboxin;
            when "010" =>
              -- Reg app_0_mailboxes_status
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= app_i(0).mailboxes_status_mbin;
              rd_dat_d0(1) <= app_i(0).mailboxes_status_mbout;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when "100" =>
              -- Reg app_1_cr
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= app_1_cr_sys_rst_reg;
              rd_dat_d0(1) <= app_1_cr_cpu_rst_reg;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when "101" =>
              -- Reg app_1_sr
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= app_i(1).sr_fault;
              rd_dat_d0(31 downto 1) <= (others => '0');
            when "110" =>
              -- Reg app_1_reset_cause
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(1).reset_cause;
            when "111" =>
              -- Reg app_1_iram_ecc_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(1).iram_ecc_se;
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "001011" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg app_1_iram_scrub_cycle
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= app_i(1).iram_scrub_cycle;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "001" =>
              -- Reg app_1_iram_scrub_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(1).iram_scrub_se;
            when "010" =>
              -- Reg app_1_iram_scrub_de_last
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= app_i(1).iram_scrub_de_last;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "011" =>
              -- Reg app_1_dram_ecc_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(1).dram_ecc_se;
            when "100" =>
              -- Reg app_1_dram_scrub_cycle
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= app_i(1).dram_scrub_cycle;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "101" =>
              -- Reg app_1_dram_scrub_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(1).dram_scrub_se;
            when "110" =>
              -- Reg app_1_dram_scrub_de_last
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= app_i(1).dram_scrub_de_last;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "111" =>
              -- Reg app_1_scrub_cfg
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= app_i(1).scrub_cfg_iram_en;
              rd_dat_d0(1) <= app_i(1).scrub_cfg_dram_en;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "001100" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg app_1_nbr_cpu_fault
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(1).nbr_cpu_fault;
            when "100" =>
              -- Reg app_1_mailboxes_mboxout
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(1).mailboxes_mboxout;
            when "101" =>
              -- Reg app_1_mailboxes_mboxin
              app_o(1).mailboxes_mboxin_rd <= rd_req_int;
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= app_i(1).mailboxes_mboxin;
            when "110" =>
              -- Reg app_1_mailboxes_status
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= app_i(1).mailboxes_status_mbin;
              rd_dat_d0(1) <= app_i(1).mailboxes_status_mbout;
              rd_dat_d0(31 downto 2) <= (others => '0');
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "010000" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg boards_0_pins
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= boards_0_pins_i;
            when "001" =>
              -- Reg boards_1_pins
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= boards_1_pins_i;
            when "010" =>
              -- Reg boards_2_pins
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= boards_2_pins_i;
            when "011" =>
              -- Reg boards_3_pins
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= boards_3_pins_i;
            when "100" =>
              -- Reg boards_4_pins
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= boards_4_pins_i;
            when "101" =>
              -- Reg boards_5_pins
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= boards_5_pins_i;
            when "110" =>
              -- Reg boards_6_pins
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= boards_6_pins_i;
            when "111" =>
              -- Reg boards_7_pins
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= boards_7_pins_i;
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "010001" =>
            case adr_int(4 downto 2) is
            when "000" =>
              -- Reg shmem_regs_ram_ecc_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= shmem_regs_ram_ecc_se_i;
            when "001" =>
              -- Reg shmem_regs_ram_scrub_cycle
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= shmem_regs_ram_scrub_cycle_i;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "010" =>
              -- Reg shmem_regs_ram_scrub_se
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0 <= shmem_regs_ram_scrub_se_i;
            when "011" =>
              -- Reg shmem_regs_ram_scrub_de_last
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= shmem_regs_ram_scrub_de_last_i;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "100" =>
              -- Reg shmem_regs_scrub_cfg
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(0) <= shmem_regs_scrub_cfg_ram_en_i;
              rd_dat_d0(31 downto 1) <= (others => '0');
            when "101" =>
              -- Reg shmem_regs_ram_scrub_period
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(15 downto 0) <= shmem_regs_ram_scrub_period_reg;
              rd_dat_d0(31 downto 16) <= (others => '0');
            when "110" =>
              -- Reg shmem_regs_ecc_mask
              rd_ack_d0 <= rd_req_int;
              rd_dat_d0(7 downto 0) <= shmem_regs_ecc_mask_reg;
              rd_dat_d0(31 downto 8) <= (others => '0');
            when others =>
              rd_ack_d0 <= rd_req_int;
            end case;
          when "010010" =>
            -- Submap i2c
            i2c_re <= rd_req_int;
            rd_dat_d0 <= i2c_i.dat;
            rd_ack_d0 <= i2c_rack;
          when "010011" =>
            -- Submap spi
            spi_re <= rd_req_int;
            rd_dat_d0 <= spi_i.dat;
            rd_ack_d0 <= spi_rack;
          when others =>
            rd_ack_d0 <= rd_req_int;
          end case;
        when "01" =>
          -- Submap fip_reg
          fip_reg_re <= rd_req_int;
          rd_dat_d0 <= fip_reg_i.dat;
          rd_ack_d0 <= fip_reg_rack;
        when "10" =>
          -- Submap sh_mem
          sh_mem_re <= rd_req_int;
          rd_dat_d0 <= sh_mem_i.dat;
          rd_ack_d0 <= sh_mem_rack;
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;
      when "0000001" =>
        -- Submap app0_mem
        app0_mem_re <= rd_req_int;
        rd_dat_d0 <= app0_mem_i.dat;
        rd_ack_d0 <= app0_mem_rack;
      when "0000010" =>
        -- Submap app1_mem
        app1_mem_re <= rd_req_int;
        rd_dat_d0 <= app1_mem_i.dat;
        rd_ack_d0 <= app1_mem_rack;
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when "1" =>
      -- Submap envm
      envm_re <= rd_req_int;
      rd_dat_d0 <= envm_i.dat;
      rd_ack_d0 <= envm_rack;
    when others =>
      rd_ack_d0 <= rd_req_int;
    end case;
  end process;
end syn;
