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-- Created by SmartDesign Thu May 12 11:52:52 2022
-- Version: v2021.2 2021.2.0.11
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----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library smartfusion2;
use smartfusion2.all;
----------------------------------------------------------------------
-- igl2_periph entity declaration
----------------------------------------------------------------------
entity igl2_periph is
    -- Port list
    port(
        -- Inputs
        CLK0                                : in  std_logic;
        DEVRST_N                            : in  std_logic;
        FAB_RESET_N                         : in  std_logic;
        HPMS_FIC_0_USER_MASTER_HADDR_M0     : in  std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HBURST_M0    : in  std_logic_vector(2 downto 0);
        HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0 : in  std_logic;
        HPMS_FIC_0_USER_MASTER_HPROT_M0     : in  std_logic_vector(3 downto 0);
        HPMS_FIC_0_USER_MASTER_HSIZE_M0     : in  std_logic_vector(2 downto 0);
        HPMS_FIC_0_USER_MASTER_HTRANS_M0    : in  std_logic_vector(1 downto 0);
        HPMS_FIC_0_USER_MASTER_HWDATA_M0    : in  std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HWRITE_M0    : in  std_logic;
        -- Outputs
        COMM_BLK_INT                        : out std_logic;
        FIC_0_CLK                           : out std_logic;
        FIC_0_LOCK                          : out std_logic;
        HPMS_FIC_0_USER_MASTER_HRDATA_M0    : out std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HREADY_M0    : out std_logic;
        HPMS_FIC_0_USER_MASTER_HRESP_M0     : out std_logic_vector(1 downto 0);
        HPMS_INT_M2F                        : out std_logic_vector(15 downto 0);
        HPMS_READY                          : out std_logic;
        INIT_DONE                           : out std_logic;
        POWER_ON_RESET_N                    : out std_logic
        );
end igl2_periph;
----------------------------------------------------------------------
-- igl2_periph architecture body
----------------------------------------------------------------------
architecture RTL of igl2_periph is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- igl2_periph_sb
component igl2_periph_sb
    -- Port list
    port(
        -- Inputs
        CLK0                                : in  std_logic;
        DEVRST_N                            : in  std_logic;
        FAB_RESET_N                         : in  std_logic;
        HPMS_FIC_0_USER_MASTER_HADDR_M0     : in  std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HBURST_M0    : in  std_logic_vector(2 downto 0);
        HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0 : in  std_logic;
        HPMS_FIC_0_USER_MASTER_HPROT_M0     : in  std_logic_vector(3 downto 0);
        HPMS_FIC_0_USER_MASTER_HSIZE_M0     : in  std_logic_vector(2 downto 0);
        HPMS_FIC_0_USER_MASTER_HTRANS_M0    : in  std_logic_vector(1 downto 0);
        HPMS_FIC_0_USER_MASTER_HWDATA_M0    : in  std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HWRITE_M0    : in  std_logic;
        -- Outputs
        COMM_BLK_INT                        : out std_logic;
        FIC_0_CLK                           : out std_logic;
        FIC_0_LOCK                          : out std_logic;
        HPMS_FIC_0_USER_MASTER_HRDATA_M0    : out std_logic_vector(31 downto 0);
        HPMS_FIC_0_USER_MASTER_HREADY_M0    : out std_logic;
        HPMS_FIC_0_USER_MASTER_HRESP_M0     : out std_logic_vector(1 downto 0);
        HPMS_INT_M2F                        : out std_logic_vector(15 downto 0);
        HPMS_READY                          : out std_logic;
        INIT_DONE                           : out std_logic;
        POWER_ON_RESET_N                    : out std_logic
        );
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal COMM_BLK_INT_net_0                  : std_logic;
signal FIC_0_CLK_net_0                     : std_logic;
signal FIC_0_LOCK_net_0                    : std_logic;
signal HPMS_FIC_0_USER_MASTER_HRDATA       : std_logic_vector(31 downto 0);
signal HPMS_FIC_0_USER_MASTER_HREADY       : std_logic;
signal HPMS_FIC_0_USER_MASTER_HRESP        : std_logic_vector(1 downto 0);
signal HPMS_INT_M2F_net_0                  : std_logic_vector(15 downto 0);
signal HPMS_READY_net_0                    : std_logic;
signal INIT_DONE_net_0                     : std_logic;
signal POWER_ON_RESET_N_net_0              : std_logic;
signal HPMS_FIC_0_USER_MASTER_HRDATA_net_0 : std_logic_vector(31 downto 0);
signal HPMS_FIC_0_USER_MASTER_HREADY_net_0 : std_logic;
signal HPMS_FIC_0_USER_MASTER_HRESP_net_0  : std_logic_vector(1 downto 0);
signal POWER_ON_RESET_N_net_1              : std_logic;
signal HPMS_READY_net_1                    : std_logic;
signal FIC_0_CLK_net_1                     : std_logic;
signal FIC_0_LOCK_net_1                    : std_logic;
signal COMM_BLK_INT_net_1                  : std_logic;
signal HPMS_INT_M2F_net_1                  : std_logic_vector(15 downto 0);
signal INIT_DONE_net_1                     : std_logic;

begin
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
 HPMS_FIC_0_USER_MASTER_HRDATA_net_0           <= HPMS_FIC_0_USER_MASTER_HRDATA;
 HPMS_FIC_0_USER_MASTER_HRDATA_M0(31 downto 0) <= HPMS_FIC_0_USER_MASTER_HRDATA_net_0;
 HPMS_FIC_0_USER_MASTER_HREADY_net_0           <= HPMS_FIC_0_USER_MASTER_HREADY;
 HPMS_FIC_0_USER_MASTER_HREADY_M0              <= HPMS_FIC_0_USER_MASTER_HREADY_net_0;
 HPMS_FIC_0_USER_MASTER_HRESP_net_0            <= HPMS_FIC_0_USER_MASTER_HRESP;
 HPMS_FIC_0_USER_MASTER_HRESP_M0(1 downto 0)   <= HPMS_FIC_0_USER_MASTER_HRESP_net_0;
 POWER_ON_RESET_N_net_1                        <= POWER_ON_RESET_N_net_0;
 POWER_ON_RESET_N                              <= POWER_ON_RESET_N_net_1;
 HPMS_READY_net_1                              <= HPMS_READY_net_0;
 HPMS_READY                                    <= HPMS_READY_net_1;
 FIC_0_CLK_net_1                               <= FIC_0_CLK_net_0;
 FIC_0_CLK                                     <= FIC_0_CLK_net_1;
 FIC_0_LOCK_net_1                              <= FIC_0_LOCK_net_0;
 FIC_0_LOCK                                    <= FIC_0_LOCK_net_1;
 COMM_BLK_INT_net_1                            <= COMM_BLK_INT_net_0;
 COMM_BLK_INT                                  <= COMM_BLK_INT_net_1;
 HPMS_INT_M2F_net_1                            <= HPMS_INT_M2F_net_0;
 HPMS_INT_M2F(15 downto 0)                     <= HPMS_INT_M2F_net_1;
 INIT_DONE_net_1                               <= INIT_DONE_net_0;
 INIT_DONE                                     <= INIT_DONE_net_1;
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- igl2_periph_sb_0
igl2_periph_sb_0 : igl2_periph_sb
    port map( 
        -- Inputs
        FAB_RESET_N                         => FAB_RESET_N,
        HPMS_FIC_0_USER_MASTER_HADDR_M0     => HPMS_FIC_0_USER_MASTER_HADDR_M0,
        HPMS_FIC_0_USER_MASTER_HTRANS_M0    => HPMS_FIC_0_USER_MASTER_HTRANS_M0,
        HPMS_FIC_0_USER_MASTER_HWRITE_M0    => HPMS_FIC_0_USER_MASTER_HWRITE_M0,
        HPMS_FIC_0_USER_MASTER_HSIZE_M0     => HPMS_FIC_0_USER_MASTER_HSIZE_M0,
        HPMS_FIC_0_USER_MASTER_HBURST_M0    => HPMS_FIC_0_USER_MASTER_HBURST_M0,
        HPMS_FIC_0_USER_MASTER_HPROT_M0     => HPMS_FIC_0_USER_MASTER_HPROT_M0,
        HPMS_FIC_0_USER_MASTER_HWDATA_M0    => HPMS_FIC_0_USER_MASTER_HWDATA_M0,
        HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0 => HPMS_FIC_0_USER_MASTER_HMASTLOCK_M0,
        DEVRST_N                            => DEVRST_N,
        CLK0                                => CLK0,
        -- Outputs
        POWER_ON_RESET_N                    => POWER_ON_RESET_N_net_0,
        INIT_DONE                           => INIT_DONE_net_0,
        FIC_0_CLK                           => FIC_0_CLK_net_0,
        FIC_0_LOCK                          => FIC_0_LOCK_net_0,
        HPMS_READY                          => HPMS_READY_net_0,
        HPMS_FIC_0_USER_MASTER_HRDATA_M0    => HPMS_FIC_0_USER_MASTER_HRDATA,
        HPMS_FIC_0_USER_MASTER_HREADY_M0    => HPMS_FIC_0_USER_MASTER_HREADY,
        HPMS_FIC_0_USER_MASTER_HRESP_M0     => HPMS_FIC_0_USER_MASTER_HRESP,
        COMM_BLK_INT                        => COMM_BLK_INT_net_0,
        HPMS_INT_M2F                        => HPMS_INT_M2F_net_0 
        );

end RTL;
