-- Do not edit.  Generated by cheby 1.6.dev0 using these options:
--  -i app_urv_regs.cheby --gen-hdl app_urv_regs.vhd
-- Generated on Tue Feb 28 17:21:43 2023 by tgingold


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

entity app_urv_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- shared memory between mgmt and app cpus
    sh_mem_i             : in    t_wishbone_master_in;
    sh_mem_o             : out   t_wishbone_master_out;

    -- Mailbox to the fip urv
    mailboxes_mboxout_i  : in    std_logic_vector(31 downto 0);
    mailboxes_mboxout_o  : out   std_logic_vector(31 downto 0);
    mailboxes_mboxout_wr_o : out   std_logic;

    -- Mailbox from the fip urv
    mailboxes_mboxin_i   : in    std_logic_vector(31 downto 0);
    mailboxes_mboxin_rd_o : out   std_logic;

    -- Status for mailboxes
    mailboxes_status_mbin_i : in    std_logic;
    mailboxes_status_mbout_i : in    std_logic;

    -- presence lines for boards
    presence_en_i        : in    std_logic_vector(7 downto 0);

    -- REG pins
    loops_0_pins_i       : in    std_logic_vector(31 downto 0);

    -- REG pins
    loops_1_pins_i       : in    std_logic_vector(31 downto 0);

    -- REG pins
    loops_2_pins_i       : in    std_logic_vector(31 downto 0);

    -- REG pins
    loops_3_pins_i       : in    std_logic_vector(31 downto 0);

    -- REG pins
    loops_4_pins_i       : in    std_logic_vector(31 downto 0);

    -- REG pins
    loops_5_pins_i       : in    std_logic_vector(31 downto 0);

    -- REG pins
    loops_6_pins_i       : in    std_logic_vector(31 downto 0);

    -- REG pins
    loops_7_pins_i       : in    std_logic_vector(31 downto 0);

    -- REG pins
    relays_0_pins_o      : out   std_logic_vector(31 downto 0);

    -- REG pins
    relays_1_pins_o      : out   std_logic_vector(31 downto 0);

    -- REG pins
    relays_2_pins_o      : out   std_logic_vector(31 downto 0);

    -- REG pins
    relays_3_pins_o      : out   std_logic_vector(31 downto 0);

    -- REG pins
    relays_4_pins_o      : out   std_logic_vector(31 downto 0);

    -- REG pins
    relays_5_pins_o      : out   std_logic_vector(31 downto 0);

    -- REG pins
    relays_6_pins_o      : out   std_logic_vector(31 downto 0);

    -- REG pins
    relays_7_pins_o      : out   std_logic_vector(31 downto 0)
  );
end app_urv_regs;

architecture syn of app_urv_regs is
  signal adr_int                        : std_logic_vector(11 downto 2);
  signal rd_req_int                     : std_logic;
  signal wr_req_int                     : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal sh_mem_re                      : std_logic;
  signal sh_mem_we                      : std_logic;
  signal sh_mem_wt                      : std_logic;
  signal sh_mem_rt                      : std_logic;
  signal sh_mem_tr                      : std_logic;
  signal sh_mem_wack                    : std_logic;
  signal sh_mem_rack                    : std_logic;
  signal mailboxes_mboxout_wreq         : std_logic;
  signal relays_0_pins_reg              : std_logic_vector(31 downto 0);
  signal relays_0_pins_wreq             : std_logic;
  signal relays_0_pins_wack             : std_logic;
  signal relays_1_pins_reg              : std_logic_vector(31 downto 0);
  signal relays_1_pins_wreq             : std_logic;
  signal relays_1_pins_wack             : std_logic;
  signal relays_2_pins_reg              : std_logic_vector(31 downto 0);
  signal relays_2_pins_wreq             : std_logic;
  signal relays_2_pins_wack             : std_logic;
  signal relays_3_pins_reg              : std_logic_vector(31 downto 0);
  signal relays_3_pins_wreq             : std_logic;
  signal relays_3_pins_wack             : std_logic;
  signal relays_4_pins_reg              : std_logic_vector(31 downto 0);
  signal relays_4_pins_wreq             : std_logic;
  signal relays_4_pins_wack             : std_logic;
  signal relays_5_pins_reg              : std_logic_vector(31 downto 0);
  signal relays_5_pins_wreq             : std_logic;
  signal relays_5_pins_wack             : std_logic;
  signal relays_6_pins_reg              : std_logic_vector(31 downto 0);
  signal relays_6_pins_wreq             : std_logic;
  signal relays_6_pins_wack             : std_logic;
  signal relays_7_pins_reg              : std_logic_vector(31 downto 0);
  signal relays_7_pins_wreq             : std_logic;
  signal relays_7_pins_wack             : std_logic;
  signal rd_ack_d0                      : std_logic;
  signal rd_dat_d0                      : std_logic_vector(31 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(11 downto 2);
  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
  signal wr_sel_d0                      : std_logic_vector(3 downto 0);
begin

  -- WB decode signals
  adr_int <= wb_i.adr(11 downto 2);
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_req_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- pipelining for wr-in+rd-out
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack_int <= '0';
        wr_req_d0 <= '0';
      else
        rd_ack_int <= rd_ack_d0;
        wb_o.dat <= rd_dat_d0;
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat;
        wr_sel_d0 <= wb_i.sel;
      end if;
    end if;
  end process;

  -- Interface sh_mem
  sh_mem_tr <= sh_mem_wt or sh_mem_rt;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        sh_mem_rt <= '0';
        sh_mem_wt <= '0';
      else
        sh_mem_rt <= (sh_mem_rt or sh_mem_re) and not sh_mem_rack;
        sh_mem_wt <= (sh_mem_wt or sh_mem_we) and not sh_mem_wack;
      end if;
    end if;
  end process;
  sh_mem_o.cyc <= sh_mem_tr;
  sh_mem_o.stb <= sh_mem_tr;
  sh_mem_wack <= sh_mem_i.ack and sh_mem_wt;
  sh_mem_rack <= sh_mem_i.ack and sh_mem_rt;
  sh_mem_o.adr <= ((20 downto 0 => '0') & adr_int(10 downto 2)) & (1 downto 0 => '0');
  sh_mem_o.sel <= wr_sel_d0;
  sh_mem_o.we <= sh_mem_wt;
  sh_mem_o.dat <= wr_dat_d0;

  -- Register mailboxes_mboxout
  mailboxes_mboxout_o <= wr_dat_d0;
  mailboxes_mboxout_wr_o <= mailboxes_mboxout_wreq;

  -- Register mailboxes_mboxin

  -- Register mailboxes_status

  -- Register presence

  -- Register loops_0_pins

  -- Register loops_1_pins

  -- Register loops_2_pins

  -- Register loops_3_pins

  -- Register loops_4_pins

  -- Register loops_5_pins

  -- Register loops_6_pins

  -- Register loops_7_pins

  -- Register relays_0_pins
  relays_0_pins_o <= relays_0_pins_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        relays_0_pins_reg <= "00000000000000000000000000000000";
        relays_0_pins_wack <= '0';
      else
        if relays_0_pins_wreq = '1' then
          relays_0_pins_reg <= wr_dat_d0;
        end if;
        relays_0_pins_wack <= relays_0_pins_wreq;
      end if;
    end if;
  end process;

  -- Register relays_1_pins
  relays_1_pins_o <= relays_1_pins_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        relays_1_pins_reg <= "00000000000000000000000000000000";
        relays_1_pins_wack <= '0';
      else
        if relays_1_pins_wreq = '1' then
          relays_1_pins_reg <= wr_dat_d0;
        end if;
        relays_1_pins_wack <= relays_1_pins_wreq;
      end if;
    end if;
  end process;

  -- Register relays_2_pins
  relays_2_pins_o <= relays_2_pins_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        relays_2_pins_reg <= "00000000000000000000000000000000";
        relays_2_pins_wack <= '0';
      else
        if relays_2_pins_wreq = '1' then
          relays_2_pins_reg <= wr_dat_d0;
        end if;
        relays_2_pins_wack <= relays_2_pins_wreq;
      end if;
    end if;
  end process;

  -- Register relays_3_pins
  relays_3_pins_o <= relays_3_pins_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        relays_3_pins_reg <= "00000000000000000000000000000000";
        relays_3_pins_wack <= '0';
      else
        if relays_3_pins_wreq = '1' then
          relays_3_pins_reg <= wr_dat_d0;
        end if;
        relays_3_pins_wack <= relays_3_pins_wreq;
      end if;
    end if;
  end process;

  -- Register relays_4_pins
  relays_4_pins_o <= relays_4_pins_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        relays_4_pins_reg <= "00000000000000000000000000000000";
        relays_4_pins_wack <= '0';
      else
        if relays_4_pins_wreq = '1' then
          relays_4_pins_reg <= wr_dat_d0;
        end if;
        relays_4_pins_wack <= relays_4_pins_wreq;
      end if;
    end if;
  end process;

  -- Register relays_5_pins
  relays_5_pins_o <= relays_5_pins_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        relays_5_pins_reg <= "00000000000000000000000000000000";
        relays_5_pins_wack <= '0';
      else
        if relays_5_pins_wreq = '1' then
          relays_5_pins_reg <= wr_dat_d0;
        end if;
        relays_5_pins_wack <= relays_5_pins_wreq;
      end if;
    end if;
  end process;

  -- Register relays_6_pins
  relays_6_pins_o <= relays_6_pins_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        relays_6_pins_reg <= "00000000000000000000000000000000";
        relays_6_pins_wack <= '0';
      else
        if relays_6_pins_wreq = '1' then
          relays_6_pins_reg <= wr_dat_d0;
        end if;
        relays_6_pins_wack <= relays_6_pins_wreq;
      end if;
    end if;
  end process;

  -- Register relays_7_pins
  relays_7_pins_o <= relays_7_pins_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        relays_7_pins_reg <= "00000000000000000000000000000000";
        relays_7_pins_wack <= '0';
      else
        if relays_7_pins_wreq = '1' then
          relays_7_pins_reg <= wr_dat_d0;
        end if;
        relays_7_pins_wack <= relays_7_pins_wreq;
      end if;
    end if;
  end process;

  -- Process for write requests.
  process (wr_adr_d0, wr_req_d0, sh_mem_wack, relays_0_pins_wack,
           relays_1_pins_wack, relays_2_pins_wack, relays_3_pins_wack,
           relays_4_pins_wack, relays_5_pins_wack, relays_6_pins_wack,
           relays_7_pins_wack) begin
    sh_mem_we <= '0';
    mailboxes_mboxout_wreq <= '0';
    relays_0_pins_wreq <= '0';
    relays_1_pins_wreq <= '0';
    relays_2_pins_wreq <= '0';
    relays_3_pins_wreq <= '0';
    relays_4_pins_wreq <= '0';
    relays_5_pins_wreq <= '0';
    relays_6_pins_wreq <= '0';
    relays_7_pins_wreq <= '0';
    case wr_adr_d0(11 downto 11) is
    when "0" =>
      -- Submap sh_mem
      sh_mem_we <= wr_req_d0;
      wr_ack_int <= sh_mem_wack;
    when "1" =>
      case wr_adr_d0(10 downto 2) is
      when "000000000" =>
        -- Reg mailboxes_mboxout
        mailboxes_mboxout_wreq <= wr_req_d0;
        wr_ack_int <= wr_req_d0;
      when "000000001" =>
        -- Reg mailboxes_mboxin
        wr_ack_int <= wr_req_d0;
      when "000000010" =>
        -- Reg mailboxes_status
        wr_ack_int <= wr_req_d0;
      when "000000100" =>
        -- Reg presence
        wr_ack_int <= wr_req_d0;
      when "000001000" =>
        -- Reg loops_0_pins
        wr_ack_int <= wr_req_d0;
      when "000001001" =>
        -- Reg loops_1_pins
        wr_ack_int <= wr_req_d0;
      when "000001010" =>
        -- Reg loops_2_pins
        wr_ack_int <= wr_req_d0;
      when "000001011" =>
        -- Reg loops_3_pins
        wr_ack_int <= wr_req_d0;
      when "000001100" =>
        -- Reg loops_4_pins
        wr_ack_int <= wr_req_d0;
      when "000001101" =>
        -- Reg loops_5_pins
        wr_ack_int <= wr_req_d0;
      when "000001110" =>
        -- Reg loops_6_pins
        wr_ack_int <= wr_req_d0;
      when "000001111" =>
        -- Reg loops_7_pins
        wr_ack_int <= wr_req_d0;
      when "000010000" =>
        -- Reg relays_0_pins
        relays_0_pins_wreq <= wr_req_d0;
        wr_ack_int <= relays_0_pins_wack;
      when "000010001" =>
        -- Reg relays_1_pins
        relays_1_pins_wreq <= wr_req_d0;
        wr_ack_int <= relays_1_pins_wack;
      when "000010010" =>
        -- Reg relays_2_pins
        relays_2_pins_wreq <= wr_req_d0;
        wr_ack_int <= relays_2_pins_wack;
      when "000010011" =>
        -- Reg relays_3_pins
        relays_3_pins_wreq <= wr_req_d0;
        wr_ack_int <= relays_3_pins_wack;
      when "000010100" =>
        -- Reg relays_4_pins
        relays_4_pins_wreq <= wr_req_d0;
        wr_ack_int <= relays_4_pins_wack;
      when "000010101" =>
        -- Reg relays_5_pins
        relays_5_pins_wreq <= wr_req_d0;
        wr_ack_int <= relays_5_pins_wack;
      when "000010110" =>
        -- Reg relays_6_pins
        relays_6_pins_wreq <= wr_req_d0;
        wr_ack_int <= relays_6_pins_wack;
      when "000010111" =>
        -- Reg relays_7_pins
        relays_7_pins_wreq <= wr_req_d0;
        wr_ack_int <= relays_7_pins_wack;
      when others =>
        wr_ack_int <= wr_req_d0;
      end case;
    when others =>
      wr_ack_int <= wr_req_d0;
    end case;
  end process;

  -- Process for read requests.
  process (adr_int, rd_req_int, sh_mem_i.dat, sh_mem_rack, mailboxes_mboxout_i,
           mailboxes_mboxin_i, mailboxes_status_mbin_i,
           mailboxes_status_mbout_i, presence_en_i, loops_0_pins_i,
           loops_1_pins_i, loops_2_pins_i, loops_3_pins_i, loops_4_pins_i,
           loops_5_pins_i, loops_6_pins_i, loops_7_pins_i, relays_0_pins_reg,
           relays_1_pins_reg, relays_2_pins_reg, relays_3_pins_reg,
           relays_4_pins_reg, relays_5_pins_reg, relays_6_pins_reg,
           relays_7_pins_reg) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    sh_mem_re <= '0';
    mailboxes_mboxin_rd_o <= '0';
    case adr_int(11 downto 11) is
    when "0" =>
      -- Submap sh_mem
      sh_mem_re <= rd_req_int;
      rd_dat_d0 <= sh_mem_i.dat;
      rd_ack_d0 <= sh_mem_rack;
    when "1" =>
      case adr_int(10 downto 2) is
      when "000000000" =>
        -- Reg mailboxes_mboxout
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= mailboxes_mboxout_i;
      when "000000001" =>
        -- Reg mailboxes_mboxin
        mailboxes_mboxin_rd_o <= rd_req_int;
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= mailboxes_mboxin_i;
      when "000000010" =>
        -- Reg mailboxes_status
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(0) <= mailboxes_status_mbin_i;
        rd_dat_d0(1) <= mailboxes_status_mbout_i;
        rd_dat_d0(31 downto 2) <= (others => '0');
      when "000000100" =>
        -- Reg presence
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(7 downto 0) <= presence_en_i;
        rd_dat_d0(31 downto 8) <= (others => '0');
      when "000001000" =>
        -- Reg loops_0_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= loops_0_pins_i;
      when "000001001" =>
        -- Reg loops_1_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= loops_1_pins_i;
      when "000001010" =>
        -- Reg loops_2_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= loops_2_pins_i;
      when "000001011" =>
        -- Reg loops_3_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= loops_3_pins_i;
      when "000001100" =>
        -- Reg loops_4_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= loops_4_pins_i;
      when "000001101" =>
        -- Reg loops_5_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= loops_5_pins_i;
      when "000001110" =>
        -- Reg loops_6_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= loops_6_pins_i;
      when "000001111" =>
        -- Reg loops_7_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= loops_7_pins_i;
      when "000010000" =>
        -- Reg relays_0_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= relays_0_pins_reg;
      when "000010001" =>
        -- Reg relays_1_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= relays_1_pins_reg;
      when "000010010" =>
        -- Reg relays_2_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= relays_2_pins_reg;
      when "000010011" =>
        -- Reg relays_3_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= relays_3_pins_reg;
      when "000010100" =>
        -- Reg relays_4_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= relays_4_pins_reg;
      when "000010101" =>
        -- Reg relays_5_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= relays_5_pins_reg;
      when "000010110" =>
        -- Reg relays_6_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= relays_6_pins_reg;
      when "000010111" =>
        -- Reg relays_7_pins
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0 <= relays_7_pins_reg;
      when others =>
        rd_ack_d0 <= rd_req_int;
      end case;
    when others =>
      rd_ack_d0 <= rd_req_int;
    end case;
  end process;
end syn;
