#ifndef __CHEBY__FIP_URV_REGS__H__
#define __CHEBY__FIP_URV_REGS__H__

#include "mbox_regs.h"
#define FIP_URV_REGS_SIZE 2097152 /* 0x200000 = 2048KB */

/* time stamp for versionning */
#define FIP_URV_REGS_VERSION 0x0UL

/* RAM size configuration */
#define FIP_URV_REGS_CONFIG_RAM 0x4UL
#define FIP_URV_REGS_CONFIG_RAM_APP0_IRAM_MASK 0xfUL
#define FIP_URV_REGS_CONFIG_RAM_APP0_IRAM_SHIFT 0
#define FIP_URV_REGS_CONFIG_RAM_APP0_DRAM_MASK 0xf0UL
#define FIP_URV_REGS_CONFIG_RAM_APP0_DRAM_SHIFT 4
#define FIP_URV_REGS_CONFIG_RAM_MGMT_IRAM_MASK 0xf000000UL
#define FIP_URV_REGS_CONFIG_RAM_MGMT_IRAM_SHIFT 24
#define FIP_URV_REGS_CONFIG_RAM_MGMT_DRAM_MASK 0xf0000000UL
#define FIP_URV_REGS_CONFIG_RAM_MGMT_DRAM_SHIFT 28

/* NanoFIP variables size */
#define FIP_URV_REGS_FIP_VAR 0x8UL
#define FIP_URV_REGS_FIP_VAR_LENGTH_MASK 0x7UL
#define FIP_URV_REGS_FIP_VAR_LENGTH_SHIFT 0

/* Status bits from NanoFIP */
#define FIP_URV_REGS_FIP_STATUS 0xcUL
#define FIP_URV_REGS_FIP_STATUS_VAR1_RDY 0x1UL
#define FIP_URV_REGS_FIP_STATUS_VAR3_RDY 0x2UL

/* Set access to var 1 */
#define FIP_URV_REGS_FIP_VAR1 0x10UL
#define FIP_URV_REGS_FIP_VAR1_ACC 0x1UL

/* Set access to var 3 */
#define FIP_URV_REGS_FIP_VAR3 0x14UL
#define FIP_URV_REGS_FIP_VAR3_ACC 0x1UL
#define FIP_URV_REGS_FIP_VAR3_CLR 0x2UL

/* Number of worldfip errors; write to clear */
#define FIP_URV_REGS_FIP_ERR 0x18UL

/* led */
#define FIP_URV_REGS_LEDS 0x1cUL
#define FIP_URV_REGS_LEDS_VAL_MASK 0xfUL
#define FIP_URV_REGS_LEDS_VAL_SHIFT 0

/* Value of the servmod lines for boards */
#define FIP_URV_REGS_SERVMOD_IN 0x20UL
#define FIP_URV_REGS_SERVMOD_IN_LINE_MASK 0xffUL
#define FIP_URV_REGS_SERVMOD_IN_LINE_SHIFT 0

/* Output of the servmod lines for boards (if dir is 1) */
#define FIP_URV_REGS_SERVMOD_OUT 0x24UL
#define FIP_URV_REGS_SERVMOD_OUT_LINE_MASK 0xffUL
#define FIP_URV_REGS_SERVMOD_OUT_LINE_SHIFT 0

/* Servmod control lines */
#define FIP_URV_REGS_SERVMOD_CTRL 0x28UL
#define FIP_URV_REGS_SERVMOD_CTRL_DIR 0x1UL

/* Status lines for PSU */
#define FIP_URV_REGS_PSU_STAT 0x2cUL
#define FIP_URV_REGS_PSU_STAT_PRES_MASK 0x3UL
#define FIP_URV_REGS_PSU_STAT_PRES_SHIFT 0

/* Control lines for PSU */
#define FIP_URV_REGS_PSU_CTRL 0x30UL
#define FIP_URV_REGS_PSU_CTRL_PWR_CYC_REQ_MASK 0x3UL
#define FIP_URV_REGS_PSU_CTRL_PWR_CYC_REQ_SHIFT 0

/* Restart the fip urv (write 0x8e51a610) */
#define FIP_URV_REGS_RESTART 0x34UL

/* RAM initialization on cpu reset */
#define FIP_URV_REGS_RESTART_CFG 0x38UL
#define FIP_URV_REGS_RESTART_CFG_IRAM_COPY 0x1UL
#define FIP_URV_REGS_RESTART_CFG_DRAM_CLEAR 0x2UL
#define FIP_URV_REGS_RESTART_CFG_IRAM_ERR 0x4UL
#define FIP_URV_REGS_RESTART_CFG_IRAM_SRC 0x8UL
#define FIP_URV_REGS_RESTART_CFG_IRAM_PAGE_MASK 0xff00UL
#define FIP_URV_REGS_RESTART_CFG_IRAM_PAGE_SHIFT 8
#define FIP_URV_REGS_RESTART_CFG_SRC_PAGE_MASK 0xff0000UL
#define FIP_URV_REGS_RESTART_CFG_SRC_PAGE_SHIFT 16

/* Number of reset */
#define FIP_URV_REGS_RESET_COUNT 0x3cUL

/* Switch off Monimod power */
#define FIP_URV_REGS_MONIMOD_SHDN 0x40UL
#define FIP_URV_REGS_MONIMOD_SHDN_VAL 0x1UL

/* Fan tray control */
#define FIP_URV_REGS_FAN_CTRL 0x44UL
#define FIP_URV_REGS_FAN_CTRL_IO0 0x1UL
#define FIP_URV_REGS_FAN_CTRL_IO1 0x2UL
#define FIP_URV_REGS_FAN_CTRL_RSTN 0x4UL

/* Tie to 0 i2c bus (to prevent powering through io) */
#define FIP_URV_REGS_I2C_OFF 0x48UL
#define FIP_URV_REGS_I2C_OFF_MONIMOD 0x1UL
#define FIP_URV_REGS_I2C_OFF_FANTRAY 0x2UL

/* Registers for app control and status */
#define FIP_URV_REGS_APP 0x100UL
#define FIP_URV_REGS_APP_SIZE 80 /* 0x50 */

/* app processor control */
#define FIP_URV_REGS_APP_CR 0x0UL
#define FIP_URV_REGS_APP_CR_SYS_RST 0x1UL
#define FIP_URV_REGS_APP_CR_CPU_RST 0x2UL

/* app processor status */
#define FIP_URV_REGS_APP_SR 0x4UL
#define FIP_URV_REGS_APP_SR_FAULT 0x1UL

/* Reason of the last reset */
#define FIP_URV_REGS_APP_RESET_CAUSE 0x8UL

/* Number of ECC correctable errors for iram */
#define FIP_URV_REGS_APP_IRAM_ECC_SE 0xcUL

/* IRAM scrubber cycle number. */
#define FIP_URV_REGS_APP_IRAM_SCRUB_CYCLE 0x10UL

/* Number of ECC corrected errors by scrubber in iram */
#define FIP_URV_REGS_APP_IRAM_SCRUB_SE 0x14UL

/* Number of ECC uncorrected errors by scrubber in iram in the current scrubber cycle.  Saturate.
 */
#define FIP_URV_REGS_APP_IRAM_SCRUB_DE_LAST 0x18UL

/* Number of ECC correctable errors for dram */
#define FIP_URV_REGS_APP_DRAM_ECC_SE 0x1cUL

/* DRAM scrubber cycle number. */
#define FIP_URV_REGS_APP_DRAM_SCRUB_CYCLE 0x20UL

/* Number of ECC corrected errors by scrubber in dram */
#define FIP_URV_REGS_APP_DRAM_SCRUB_SE 0x24UL

/* Number of ECC uncorrected errors by scrubber in dram during the last scrubber cycle.  Saturate.
 */
#define FIP_URV_REGS_APP_DRAM_SCRUB_DE_LAST 0x28UL

/* configuration of scrubbers */
#define FIP_URV_REGS_APP_SCRUB_CFG 0x2cUL
#define FIP_URV_REGS_APP_SCRUB_CFG_IRAM_EN 0x1UL
#define FIP_URV_REGS_APP_SCRUB_CFG_DRAM_EN 0x2UL

/* Number of cpu faults */
#define FIP_URV_REGS_APP_NBR_CPU_FAULT 0x30UL

/* None */
#define FIP_URV_REGS_APP_MAILBOXES 0x40UL
#define ADDR_MASK_FIP_URV_REGS_APP_MAILBOXES 0xf0UL
#define FIP_URV_REGS_APP_MAILBOXES_SIZE 16 /* 0x10 */

/* None */
#define FIP_URV_REGS_BOARDS 0x200UL
#define FIP_URV_REGS_BOARDS_SIZE 4 /* 0x4 */

/* None */
#define FIP_URV_REGS_BOARDS_PINS 0x0UL

/* None */
#define FIP_URV_REGS_SHMEM_REGS 0x220UL
#define FIP_URV_REGS_SHMEM_REGS_SIZE 32 /* 0x20 */

/* Number of ECC correctable errors for ram */
#define FIP_URV_REGS_SHMEM_REGS_RAM_ECC_SE 0x220UL

/* RAM scrubber cycle number. */
#define FIP_URV_REGS_SHMEM_REGS_RAM_SCRUB_CYCLE 0x224UL

/* Number of ECC corrected errors by scrubber in ram */
#define FIP_URV_REGS_SHMEM_REGS_RAM_SCRUB_SE 0x228UL

/* Number of ECC uncorrected errors by scrubber in iram during the last scrubber cycle.  Saturate.
 */
#define FIP_URV_REGS_SHMEM_REGS_RAM_SCRUB_DE_LAST 0x22cUL

/* configuration of scrubbers */
#define FIP_URV_REGS_SHMEM_REGS_SCRUB_CFG 0x230UL
#define FIP_URV_REGS_SHMEM_REGS_SCRUB_CFG_RAM_EN 0x1UL

/* Maximum number of cycles between a scrub */
#define FIP_URV_REGS_SHMEM_REGS_RAM_SCRUB_PERIOD 0x234UL
#define FIP_URV_REGS_SHMEM_REGS_RAM_SCRUB_PERIOD_PRESET 0x7ffUL

/* ECC bits to corrupt */
#define FIP_URV_REGS_SHMEM_REGS_ECC_MASK 0x238UL

/* i2c interfaces for monitors */
#define FIP_URV_REGS_I2C 0x240UL
#define ADDR_MASK_FIP_URV_REGS_I2C 0x1fffe0UL
#define FIP_URV_REGS_I2C_SIZE 32 /* 0x20 */

/* flash */
#define FIP_URV_REGS_SPI 0x260UL
#define ADDR_MASK_FIP_URV_REGS_SPI 0x1fffe0UL
#define FIP_URV_REGS_SPI_SIZE 32 /* 0x20 */

/* NanoFIP internal memory/registers */
#define FIP_URV_REGS_FIP_REG 0x800UL
#define ADDR_MASK_FIP_URV_REGS_FIP_REG 0x1ff800UL
#define FIP_URV_REGS_FIP_REG_SIZE 2048 /* 0x800 = 2KB */

/* Shared memory between app and mgmt urv */
#define FIP_URV_REGS_SH_MEM 0x1000UL
#define ADDR_MASK_FIP_URV_REGS_SH_MEM 0x1ff800UL
#define FIP_URV_REGS_SH_MEM_SIZE 2048 /* 0x800 = 2KB */

/* Memory of the app urv */
#define FIP_URV_REGS_APP0_MEM 0x2000UL
#define ADDR_MASK_FIP_URV_REGS_APP0_MEM 0x1fe000UL
#define FIP_URV_REGS_APP0_MEM_SIZE 8192 /* 0x2000 = 8KB */

/* Memory of the app urv */
#define FIP_URV_REGS_APP1_MEM 0x4000UL
#define ADDR_MASK_FIP_URV_REGS_APP1_MEM 0x1fe000UL
#define FIP_URV_REGS_APP1_MEM_SIZE 8192 /* 0x2000 = 8KB */

/* Igloo2 ENVM */
#define FIP_URV_REGS_ENVM 0x100000UL
#define ADDR_MASK_FIP_URV_REGS_ENVM 0x100000UL
#define FIP_URV_REGS_ENVM_SIZE 1048576 /* 0x100000 = 1024KB */

#ifndef __ASSEMBLER__
struct fip_urv_regs {
  /* [0x0]: REG (ro) time stamp for versionning */
  uint32_t version;

  /* [0x4]: REG (ro) RAM size configuration */
  uint32_t config_ram;

  /* [0x8]: REG (rw) NanoFIP variables size */
  uint32_t fip_var;

  /* [0xc]: REG (ro) Status bits from NanoFIP */
  uint32_t fip_status;

  /* [0x10]: REG (rw) Set access to var 1 */
  uint32_t fip_var1;

  /* [0x14]: REG (rw) Set access to var 3 */
  uint32_t fip_var3;

  /* [0x18]: REG (rw) Number of worldfip errors; write to clear */
  uint32_t fip_err;

  /* [0x1c]: REG (rw) led */
  uint32_t leds;

  /* [0x20]: REG (ro) Value of the servmod lines for boards */
  uint32_t servmod_in;

  /* [0x24]: REG (wo) Output of the servmod lines for boards (if dir is 1) */
  uint32_t servmod_out;

  /* [0x28]: REG (rw) Servmod control lines */
  uint32_t servmod_ctrl;

  /* [0x2c]: REG (ro) Status lines for PSU */
  uint32_t psu_stat;

  /* [0x30]: REG (rw) Control lines for PSU */
  uint32_t psu_ctrl;

  /* [0x34]: REG (wo) Restart the fip urv (write 0x8e51a610) */
  uint32_t restart;

  /* [0x38]: REG (rw) RAM initialization on cpu reset */
  uint32_t restart_cfg;

  /* [0x3c]: REG (ro) Number of reset */
  uint32_t reset_count;

  /* [0x40]: REG (rw) Switch off Monimod power */
  uint32_t monimod_shdn;

  /* [0x44]: REG (rw) Fan tray control */
  uint32_t fan_ctrl;

  /* [0x48]: REG (rw) Tie to 0 i2c bus (to prevent powering through io) */
  uint32_t i2c_off;

  /* padding to: 64 words */
  uint32_t __padding_0[45];

  /* [0x100]: REPEAT Registers for app control and status */
  struct app {
    /* [0x0]: REG (rw) app processor control */
    uint32_t cr;

    /* [0x4]: REG (ro) app processor status */
    uint32_t sr;

    /* [0x8]: REG (ro) Reason of the last reset */
    uint32_t reset_cause;

    /* [0xc]: REG (ro) Number of ECC correctable errors for iram */
    uint32_t iram_ecc_se;

    /* [0x10]: REG (ro) IRAM scrubber cycle number. */
    uint16_t iram_scrub_cycle;

    /* padding to: 20 words */
    uint8_t __padding_0[2];

    /* [0x14]: REG (ro) Number of ECC corrected errors by scrubber in iram */
    uint32_t iram_scrub_se;

    /* [0x18]: REG (ro) Number of ECC uncorrected errors by scrubber in iram in the current scrubber cycle.  Saturate.
 */
    uint16_t iram_scrub_de_last;

    /* padding to: 28 words */
    uint8_t __padding_1[2];

    /* [0x1c]: REG (ro) Number of ECC correctable errors for dram */
    uint32_t dram_ecc_se;

    /* [0x20]: REG (ro) DRAM scrubber cycle number. */
    uint16_t dram_scrub_cycle;

    /* padding to: 36 words */
    uint8_t __padding_2[2];

    /* [0x24]: REG (ro) Number of ECC corrected errors by scrubber in dram */
    uint32_t dram_scrub_se;

    /* [0x28]: REG (ro) Number of ECC uncorrected errors by scrubber in dram during the last scrubber cycle.  Saturate.
 */
    uint16_t dram_scrub_de_last;

    /* padding to: 44 words */
    uint8_t __padding_3[2];

    /* [0x2c]: REG (ro) configuration of scrubbers */
    uint32_t scrub_cfg;

    /* [0x30]: REG (ro) Number of cpu faults */
    uint32_t nbr_cpu_fault;

    /* padding to: 16 words */
    uint32_t __padding_4[3];

    /* [0x40]: SUBMAP (no description) */
    struct mbox_regs mailboxes;

    /* padding to: 16 words */
    uint32_t __padding_5[1];
  } app[2];

  /* padding to: 64 words */
  uint32_t __padding_1[24];

  /* [0x200]: REPEAT (no description) */
  struct boards {
    /* [0x0]: REG (ro) (no description) */
    uint32_t pins;
  } boards[8];

  /* [0x220]: BLOCK (no description) */
  struct shmem_regs {
    /* [0x0]: REG (ro) Number of ECC correctable errors for ram */
    uint32_t ram_ecc_se;

    /* [0x4]: REG (ro) RAM scrubber cycle number. */
    uint16_t ram_scrub_cycle;

    /* padding to: 8 words */
    uint8_t __padding_0[2];

    /* [0x8]: REG (ro) Number of ECC corrected errors by scrubber in ram */
    uint32_t ram_scrub_se;

    /* [0xc]: REG (ro) Number of ECC uncorrected errors by scrubber in iram during the last scrubber cycle.  Saturate.
 */
    uint16_t ram_scrub_de_last;

    /* padding to: 16 words */
    uint8_t __padding_1[2];

    /* [0x10]: REG (rw) configuration of scrubbers */
    uint32_t scrub_cfg;

    /* [0x14]: REG (rw) Maximum number of cycles between a scrub */
    uint16_t ram_scrub_period;

    /* padding to: 24 words */
    uint8_t __padding_2[2];

    /* [0x18]: REG (rw) ECC bits to corrupt */
    uint8_t ecc_mask;

    /* padding to: 24 words */
    uint8_t __padding_3[7];
  } shmem_regs;

  /* [0x240]: SUBMAP i2c interfaces for monitors */
  uint32_t i2c[8];

  /* [0x260]: SUBMAP flash */
  uint32_t spi[8];

  /* padding to: 512 words */
  uint32_t __padding_2[352];

  /* [0x800]: SUBMAP NanoFIP internal memory/registers */
  uint32_t fip_reg[512];

  /* [0x1000]: SUBMAP Shared memory between app and mgmt urv */
  uint32_t sh_mem[512];

  /* padding to: 2048 words */
  uint32_t __padding_3[512];

  /* [0x2000]: SUBMAP Memory of the app urv */
  uint32_t app0_mem[2048];

  /* [0x4000]: SUBMAP Memory of the app urv */
  uint32_t app1_mem[2048];

  /* padding to: 262144 words */
  uint32_t __padding_4[256000];

  /* [0x100000]: SUBMAP Igloo2 ENVM */
  uint32_t envm[262144];
};
#endif /* !__ASSEMBLER__*/

#endif /* __CHEBY__FIP_URV_REGS__H__ */
