Remove leftovers from previous routing + cleanup some traces at vias
-
SLOT5.LVDS_10 (L1 X:186mm Y:65mm) -
L1: X:133mm Y:19mm - pad connection to via under FPGA -
L1: X:135mm Y:16.5mm -
L1: X:140.5mm Y:28mm -
L12: X:217mm Y:69mm -
L12: X:120mm Y:15mm -
L12: X:81mm Y:20mm -
L1: X:112mm Y:40mm - keepout region -
L7: X:132mm Y:36mm - SLOT3.LVDS_6 can be centered better between vias