Main features and components
FPGA
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
IGLOO2 M2GL090T | M2GL090T-FGG676I | 1 | QPS, CMS HF FE |
The Igloo2 FPGAs have been are almost identical to the radiation-tested Smartfusion2 devices and, as such, should exhibit similar behavior under radiation. Additionally, they provide a 5Gbps SERDES that might be experimentally used with
Memories
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
512Kb SPI Flash | AT25DN512C | 1 | uQDS | radiation test |
The Igloo2 FPGA provides 256KB of non-volatile memory but an external SPI Flash is also provided for applications that need to store larger amounts of persistent data. An external SRAM with ECC may also be provided.
Power
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
FEAST-based modules | FEASTMP | 2 | GEFE, many others | |
3A LDO Linear regulator | LT3083 | 1 | uQDS VDP | radiation test, either this or the LHC3913 |
3A LDO Linear regulator | LHC4913 | 1 | GEFE | Rad-hard by design (radiation test), developed by CERN |
As a DC/DC converter that works reliably under radiation, the CERN-developed FEAST comes up as the obvious solution. One 1.2V FEASTMP module can be used for the FPGA Vcore and a 3.3V one for the FMC and the backplane I/O power rail.1
Each FEASTMP module is approximately 17mm x 37mm so in total these would occupy an area of about 17mm x 75mm which should be easily available in a sparsely populated board. The fully assembled, shielded modules have a height of 14.37mm, which is just under the 14.5mm afforded to us by the CPCI-S specification.
Power monitoring
Implemented by integrating MoniMod functionality for:
- P12V
- P1V2
- P3V3
- PPERIPH (selection between: P1V8, P2V5, P3V3)
Other components
Type | Component | How many | Other designs | Comments |
---|---|---|---|---|
Dual-supply 2b bus transceiver | SN74LVC2T45 | GEFE | radiation test | |
Dual-supply 16b bus transceiver | SN74LVC16T245 | radiation test | ||
Dual rail-to-rail opamp | OPA2192 | QPS | radiation test | |
1-wire temperature sensor | DS18B20 | radiation test |
The board will also have the ability to be powered from a single 4-pin MOLEX 12V connector for added flexibility in testing and development.
There are no clock fan-out drivers on this list as the Igloo2 FPGA will implement the clock distribution functionality.
LPC FMC slot with 4 MGTs
- One out of the four MGTs of the Igloo2 will be routed to the LPC FMC mezzanine
- Almost fully populated: the 68 user I/Os, I2C, JTAG, clocks, presence are all connected; VREF is unused.
- Vadj and I/Os fixed at 2.5V (supported by the new nanoFIP design)
Mechanics
- Identical to the Zynq Ultrascale-based system board except for the SFP cage, which here is missing.
- Board dimensions: 100mm x 220mm
- EDA-03828 to be used as a reference and mechanical template
- Mechanics of the board shall be compliant with section 3.5.1 of CPCI-S.0 specification.
- Mechanics of the front panel shall be compliant with sections 3.5.5, 3.5.7 of CPCI-S.0 specification.
- FMC connector in the front to host a communication mezzanine
- CPCIs backplane connectors P1 - P6 in the back
- ESD strips on both sides of the board, along the bottom edge of the PCB with discharge resistors according to section 3.5.10 of CPCI-S.0 specification.
- The length of ESD strip segment 2 shall be 115mm.
Compact PCI Serial backplane connectors
- 287 FPGA I/Os in total (23 for control and monitoring, then for each peripheral board: 15 data diff pairs, 1 clock diff pair, 1 SERVMOD_N / presence line)
- The _P pins of the five lowermost differential pairs are used to extend the system board's JTAG chain with that of a peripheral board when we drive the SERVMOD_N signal high (as described here).
- I2C SCL and SDA (P1.B2; P1.C2) shall be pulled-up to 3.3V and ESD-protected
- PS_ON# (P1.E2) shall be connected to an external watchdog/self-reset circuit for remote power-cycling the whole crate, and ESD-protected
- RST# (P1.F2) pulled-up to 3.3V, and ESD-protected
- PRST# (P1.H2) - ESD-protected through 3.3V TVS diode
- PWRBTN# (P1.C3) - ESD-protected through 3.3V TVS diode
- Monitoring I/Os (PS_ON#, PWRFAIL, P_PRES, M_SDA, M_SCL, P_RST, P_IO0-2, F_RST, F_IO0-1) - ESD-protected through 3.3V TVS diode P_PRES0, P_PRES1, M_SDA, M_SCL pulled-up to 3.3V
- SHARED_BUS0-4 (P1.I2; P1.G3; P1.H3; P1.J3; P1.K3) - shall be pulled-up to 3.3V and ESD-protected
-
The voltage level of the backplane I/Os will be selectable with a jumper between 3.3V and 2.5V, an LDO will use the 3.3V to provide the 2.5V.
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