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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit a292404f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch '257-first-gateware-version' into 'master' 

Resolve "first-gateware-version"

Closes #257

See merge request !1
parents bd1726df 77bd121b
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      .gitlab-ci.yml
      View file @ a292404f
      variables: variables:
      GIT_SUBMODULE_STRATEGY: normal GIT_SUBMODULE_STRATEGY: normal
      # Define stages
      stages: stages:
      - compile - gateware
      - bootbin
      - release
      job_sw_compile: # Built bistream job
      stage: compile .build-gw:
      stage: gateware
      variables:
      XILINX_PATH: /opt/Xilinx
      XILINX_VERSION: "2019.2"
      tags: tags:
      - petalinux_2019.2 - vivado-2019.2
      # only: before_script:
      # - schedules - source $XILINX_PATH/Vivado/$XILINX_VERSION/settings64.sh
      script: script:
      - git config --global user.email "OHWR_CI@somewhere.com" - cd gw && make $PROJECT.build
      - git config --global user.name "OHWR_CI"
      - cd sw && export SB_VER=2 && make -j 4
      artifacts: artifacts:
      name: DIOT_SB_CI_$CI_JOB_ID when: on_success
      when: always paths:
      - gw/output_files/$PROJECT/$PROJECT.bit
      - gw/output_files/$PROJECT/$PROJECT.xsa
      expire_in: 7d
      # Build bitstream for each project
      build_diot_v1:
      extends: .build-gw
      variables:
      PROJECT: diot_v1
      artifacts:
      name: diot_v1-gw-$CI_JOB_ID
      build_diot_v2:
      extends: .build-gw
      variables:
      PROJECT: diot_v2
      artifacts:
      name: diot_v2-gw-$CI_JOB_ID
      # Build OS
      .build-image:
      stage: bootbin
      tags:
      - petalinux-2019.2
      script:
      - git config --global user.email "OHWR_CI@somewhere.com"
      - git config --global user.name "OHWR_CI"
      - cd sw && make -j 4 SB_VER=$BOARD_VERSION
      artifacts:
      when: on_success
      paths: paths:
      - sw/artifacts/BOOT.BIN - sw/artifacts/BOOT.BIN
      - sw/artifacts/image.ub - sw/artifacts/image.ub
      - sw/artifacts/fsbl.elf - sw/artifacts/fsbl.elf
      - sw/log/* - sw/log/*
      - gw/output_files/$PROJECT/diot_v$BOARD_VERSION.xsa
      expire_in: 7d
      # Build OS for each project
      build-diot-v1-img:
      extends: .build-image
      variables:
      PROJECT: diot_v1
      BOARD_VERSION: 1
      artifacts:
      name: diot_v1-linux-$CI_JOB_ID
      # Build OS for each project
      build-diot-v2-img:
      extends: .build-image
      variables:
      PROJECT: diot_v2
      BOARD_VERSION: 2
      artifacts:
      name: diot_v2-linux-$CI_JOB_ID
      # Define job for release
      release_job:
      stage: release
      image: registry.gitlab.com/gitlab-org/release-cli:latest
      tags:
      - petalinux-2019.2
      script:
      - gitlab-release --zip "diot_v1-${CI_COMMIT_TAG}.zip" gw/output_files/diot_v1 sw/artifacts/BOOT.BIN sw/artifacts/image.ub sw/artifacts/fsbl.elf sw/log/* --link-in-desc --description "Bootable Image V1"
      - gitlab-release --zip "diot_v2-${CI_COMMIT_TAG}.zip" gw/output_files/diot_v2 sw/artifacts/BOOT.BIN sw/artifacts/image.ub sw/artifacts/fsbl.elf sw/log/* --link-in-desc --description "Bootable Image V2"
      only:
      - /^v[0-9]+\.[0-9]+\.[0-9]+$/
      gw/.gitignore 0 → 100644
      View file @ a292404f
      # cache
      .Xil
      # Generated files
      output_files
      # vivado
      *.log
      *.jou
      gw/Makefile 0 → 100644
      View file @ a292404f
      #!/usr/bin/make
      # ##############################################################################
      # Settings
      DOCKER_NAME=vivado-template
      DOCKERFILE_PATH=docker
      XILINX_TOOLS=/opt/Xilinx
      XIL_VER?=2019.2
      SETUP_XIL_ENV=source ${XILINX_TOOLS}/Vivado/${XIL_VER}/settings64.sh
      CALL_VIVADO_DEF=vivado -source build_project.tcl -mode batch -nolog -nojournal -notrace -tclargs
      docker_build:
      docker build -f ${DOCKERFILE_PATH}/Dockerfile -t ${DOCKER_NAME} ${DOCKERFILE_PATH}
      CALL_DOCKER?=docker run -w${CURDIR} \
      -v${CURDIR}:${CURDIR} \
      -v ${HOME}:${HOME} \
      -v /etc/passwd:/etc/passwd:ro \
      -v /etc/shadow:/etc/shadow:ro \
      -v /etc/group:/etc/group:ro \
      -v /tmp:/tmp \
      -v /tmp/.X11-unix:/tmp/.X11-unix \
      -v ${XILINX_TOOLS}:${XILINX_TOOLS} \
      -v /var/run/dbus:/var/run/dbus \
      -e DISPLAY=${DISPLAY} \
      -u $$(id -u):$$(id -g) \
      --privileged \
      -t ${DOCKER_NAME} /bin/bash -c
      ifdef GITLAB_CI
      CMD_DOCKER=eval
      CALL_VIVADO=${CALL_VIVADO_DEF}
      else
      CMD_DOCKER=${CALL_DOCKER}
      CALL_VIVADO=${SETUP_XIL_ENV} && ${CALL_VIVADO_DEF}
      endif
      # ##############################################################################
      # Define project list
      TARGET_LIST:=$(shell ls projects)
      TARGET_BUILD_LIST:=$(addsuffix .build, ${TARGET_LIST})
      TARGET_BD_LIST:=$(addsuffix .bd, ${TARGET_LIST})
      TARGET_CLEAN_LIST:=$(addsuffix .clean, ${TARGET_LIST})
      # ##############################################################################
      # Build Steps
      OUTPUT_PATH=output_files
      ${OUTPUT_PATH}:
      mkdir -p @
      ${TARGET_BUILD_LIST}:
      ${CMD_DOCKER} '${CALL_VIVADO} projects/$(basename $@) build ${OUTPUT_PATH}'
      ${TARGET_BD_LIST}:
      ${CMD_DOCKER} '${CALL_VIVADO} projects/$(basename $@) bd ${OUTPUT_PATH}'
      ${TARGET_CLEAN_LIST}:
      rm -rf ${OUTPUT_PATH}/$(basename $@)
      # ##############################################################################
      # Clean rule
      # ##############################################################################
      clean:
      rm -rf ${OUTPUT_PATH}
      rm -rf *.log *.jou
      gw/README.md 0 → 100644
      View file @ a292404f
      # Gateware
      This repository folder allows you to build the bitstream/XSA file for the DIOT system board version 1 & 2 which based on Xilinx Zynq Ultrascale+ (**xczu7cg-ffvf1517-1-e**)
      ## Requirements Linux
      - Docker:
      - [Install Docker Debian](https://docs.docker.com/engine/install/debian/)
      - [Install Docker Ubuntu](https://docs.docker.com/engine/install/ubuntu/)
      - [Install Docker CentOS](https://docs.docker.com/engine/install/centos/)
      - Vitis **v2019.2**:
      - [Download Vitis 2019.2](https://www.xilinx.com/member/forms/download/xef-vitis.html?filename=Xilinx_Vitis_2019.2_1106_2127.tar.gz)
      - [Install Vitis](https://docs.xilinx.com/v/u/2019.2-English/ug1400-vitis-embedded)
      - Install make Debian/Ubuntu:
      ```console
      sudo apt install -y make
      ```
      - Install make CentOS:
      ```console
      yum install -y make
      ```
      ## Requirements Windows
      Unfortunately Windows is not supported yet
      ## Build Container
      ```console
      make docker_build
      ```
      ## Build Design
      - Build bitstream:
      ```console
      make <project>.build
      ```
      - Build just the block design:
      ```console
      make <project>.bd
      ```
      In both cases the project options are:
      - diot_v1
      - diot_v2
      ## Maintainers
      - [Alén Arias Vázquez](mailto:alen.arias.vazquez@cern.ch)
      - [Greg Daniluk](mailto:grzegorz.daniluk@cern.ch)
      gw/build_project.tcl 0 → 100644
      View file @ a292404f
      ################################################################################
      #
      # Main Script to buil any project in the repository
      #
      ################################################################################
      source functions.tcl -notrace
      write_msg "INFO: Launching Vivado TCL mode" "1"
      if { $::argc == 3 } {
      set target_path [lindex $argv 0]
      set run_type [lindex $argv 1]
      set output_path [lindex $argv 2]
      } else {
      write_msg "ERROR: Bad call to tcl script build_project.tcl" "3"
      return 1
      }
      # Loading project specific config
      source ${target_path}/tcl/project_cfg.tcl -notrace
      set_param general.maxThreads ${max_threads}
      # Set the project name
      set _xil_proj_name_ ${project_name}
      source ${target_path}/tcl/create_bd.tcl -notrace
      # Create project
      create_project ${_xil_proj_name_} ${output_path}/${_xil_proj_name_} -part ${reference_part}
      # Source TCL FPGA Device
      source common-ip/fpga_device/tcl/fpga_device.tcl
      create_fpga_version "${_xil_proj_name_}" "common-ip/fpga_device/src/fpga_device.v" "${output_path}/${_xil_proj_name_}/fpga_device.v"
      add_files -norecurse common-ip/fpga_device/src/dna_reader.v
      add_files -norecurse ${output_path}/${_xil_proj_name_}/fpga_device.v
      # Set Properties from the list
      if [ info exist ::user_list(PROP_NAME) ] {
      set curr_project [ current_project ]
      set list_names [ get_list PROP_NAME ]
      set list_values [ get_list PROP_VAL ]
      set list_names_max_i [ get_list_size PROP_NAME ]
      for { set i 0 } { $i < ${list_names_max_i} } { incr i } {
      set lname [ lindex ${list_names} ${i} ]
      set lvalue [ lindex ${list_values} ${i} ]
      write_msg "INFO: Set property $lname to $lvalue" "1"
      set_property -name $lname -value $lvalue -objects $curr_project
      }
      }
      # Add VHDL
      if [ info exist ::user_list(SRC_VHDL) ] {
      set list_vhdl [ get_list SRC_VHDL ]
      set list_lib [ get_list LIB_VHDL ]
      set list_vhdl_max_i [ get_list_size SRC_VHDL ]
      for { set i 0 } { $i < ${list_vhdl_max_i} } { incr i } {
      set vhdl_src [ lindex ${list_vhdl} ${i} ]
      set vhdl_lib [ lindex ${list_lib} ${i} ]
      write_msg "INFO: Adding VHLD file ${vhdl_src}" "1"
      read_vhdl -library ${vhdl_lib} ${target_path}/src/${vhdl_src}
      }
      }
      # Add VHDL08
      if [ info exist ::user_list(SRC_VHDL08) ] {
      set list_vhdl [ get_list SRC_VHDL08 ]
      set list_lib [ get_list LIB_VHDL08 ]
      set list_vhdl_max_i [ get_list_size SRC_VHDL08 ]
      for { set i 0 } { $i < ${list_vhdl_max_i} } { incr i } {
      set vhdl_src [ lindex ${list_vhdl} ${i} ]
      set vhdl_lib [ lindex ${list_lib} ${i} ]
      write_msg "INFO: Adding VHLD 2008 file ${vhdl_src}" "1"
      read_vhdl -library ${vhdl_lib} -2008 ${target_path}/src/${vhdl_src}
      }
      }
      # Add Verilog/SystemVerilog sources
      if [ info exist ::user_list(SRC_VERILOG) ] {
      set list_ver [ get_list SRC_VERILOG ]
      set list_ver_max_i [ get_list_size SRC_VERILOG ]
      for { set i 0 } { $i < ${list_ver_max_i} } { incr i } {
      set ver_src [ lindex ${list_ver} ${i} ]
      if { [ enable_sv_compilation ${ver_src} ] == 1 } {
      write_msg "INFO: Adding SystemVerilog file ${ver_src}" "1"
      read_verilog -library ${lib_default} -sv ${target_path}/src/${ver_src}
      } else {
      write_msg "INFO: Adding Verilog file ${ver_src}" "1"
      read_verilog -library ${lib_default} ${target_path}/src/${ver_src}
      }
      }
      }
      # Add XDC Files
      if [ info exist ::user_list(CONSTRAINT) ] {
      set list_xdc [ get_list CONSTRAINT ]
      set list_names_max_i [ get_list_size CONSTRAINT ]
      for { set i 0 } { $i < ${list_names_max_i} } { incr i } {
      set file_xdc [ lindex ${list_xdc} ${i} ]
      write_msg "INFO: Adding XDC file ${file_xdc}" "1"
      read_xdc ${target_path}/constraints/${file_xdc}
      }
      }
      # Set the directory path for the new project
      set proj_dir [get_property directory [current_project]]
      # Create 'sources_1' fileset (if not found)
      if {[string equal [get_filesets -quiet sources_1] ""]} {
      create_fileset -srcset sources_1
      }
      update_ip_catalog -rebuild
      set obj [get_filesets sources_1]
      set_property -name "top" -value ${entity_top} -objects $obj
      # ##############################################################################
      # Create Block Design
      # ##############################################################################
      write_msg "INFO: Generating block design" "1"
      create_block_design "" ${_xil_proj_name_} ${target_path}
      update_compile_order -fileset sources_1
      set_property IS_ENABLED "1" [ get_files ${_xil_proj_name_}.bd ]
      set_property REGISTERED_WITH_MANAGER "1" [ get_files ${_xil_proj_name_}.bd ]
      set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [ get_files ${_xil_proj_name_}.bd ]
      # ##############################################################################
      # Launch synthesis & implementation
      # ##############################################################################
      if { [ string equal ${run_type} "build" ] } {
      # Launch Synthesis
      write_msg "INFO: Launch Synthesis" "1"
      launch_runs synth_1 -jobs ${max_threads}
      wait_on_run synth_1
      set status_synth [ get_property STATUS [ get_runs synth_1 ] ]
      if { [ string equal ${status_synth} "synth_design Complete!" ] } {
      write_msg "INFO: ${status_synth}" "1"
      } else {
      write_msg "ERROR: Synthesis run failed" "3"
      write_msg "ERROR: ${status_synth}" "3"
      exit 1
      }
      # Set Implementation Properties
      set obj [ get_runs impl_1 ]
      set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
      # Launch Implementation & Bitstream
      write_msg "INFO: Launch Implementation & Bistream generation" "1"
      launch_runs impl_1 -to_step write_bitstream -jobs ${max_threads}
      wait_on_run impl_1
      set status_impl_1 [ get_property STATUS [ get_runs impl_1 ] ]
      if { [ string equal ${status_impl_1} "write_bitstream Complete!" ] } {
      write_msg "INFO: ${status_impl_1}" "1"
      } else {
      write_msg "ERROR: Implementation run failed" "3"
      write_msg "ERROR: ${status_impl_1}" "3"
      exit 1
      }
      # Copy Bitstream
      if { [ file exists ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.runs/impl_1/${entity_top}.bit ] } {
      write_msg "INFO: Copy Bistream" "1"
      file copy ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.runs/impl_1/${entity_top}.bit ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.bit
      write_msg "INFO: Generating XSA with bitstream ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa" "1"
      write_hw_platform -force ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa -fixed -include_bit
      } else {
      write_msg "ERROR: Failed Bistream Generation" "3"
      exit 1
      }
      } else {
      # Generate XSA without bistream
      write_msg "INFO: Target Hardware Platform" "1"
      generate_target {synthesis implementation} [get_files ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${_xil_proj_name_}/${_xil_proj_name_}.bd]
      write_msg "INFO: Generating XSA file ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa" "1"
      write_hw_platform -force ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa -fixed
      }
      exit 0
      gw/common-ip/fpga_device/src/dna_reader.v 0 → 100644
      View file @ a292404f
      //==============================================================================
      //! @file dna_reader.v
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - DNA Reader Xilinx FPGA --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: DNA Reader Xilinx FPGA
      //
      //! @brief DNA Reader Xilinx FPGA
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 11/05/2022
      //
      //! @details
      //! PL DNA is 96bits width in the Ultrascale/Ultrascale+
      //
      //------------------------------------------------------------------------------
      module dna_reader # (
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      )
      (
      input clk_i,
      input rst_n_i,
      output dna_rdy_o,
      output [95:0] dna_o
      );
      //! Status
      localparam [1:0] SET = 2'b00;
      localparam [1:0] UNSET = 2'b01;
      localparam [1:0] COUNT = 2'b11;
      localparam [1:0] DONE = 2'b10;
      (* fsm_encoding = "gray" *) reg [1:0] s_state;
      //! Constants
      localparam [6:0] c_MAX_CTR = 7'd96;
      //! Signals
      reg s_read;
      reg s_shift;
      reg s_dna_rdy;
      reg [6:0] s_shift_c;
      reg [95:0] s_dna;
      wire s_data;
      //! FSM
      always @(posedge clk_i, negedge rst_n_i)
      begin : p_fsm
      if(! rst_n_i) begin
      s_read <= 1'b0;
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b0;
      s_state <= SET;
      end
      else begin
      case (s_state)
      //! State SET
      SET:
      begin
      s_shift_c <= 'h0;
      s_read <= 1'b1;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      s_state <= UNSET;
      end
      //! State UNSET
      UNSET:
      begin
      s_shift_c <= 'h0;
      s_read <= 1'b0;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      s_state <= COUNT;
      end
      //! State COUNT
      COUNT:
      begin
      s_read <= 1'b0;
      if (s_shift_c < c_MAX_CTR) begin
      s_shift_c <= s_shift_c + 'd1;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      end
      else begin
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b1;
      s_state <= DONE;
      end
      end
      //! State DONE
      DONE:
      begin
      s_read <= 1'b0;
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b1;
      s_state <= DONE;
      end
      endcase
      end
      end : p_fsm
      //! Shift Register
      always @(posedge clk_i, negedge rst_n_i)
      begin : p_shift
      if (! rst_n_i)
      s_dna <= 'h0;
      else begin
      if (s_shift)
      s_dna <= {s_data, s_dna[95:1]};
      end
      end : p_shift
      assign dna_rdy_o = s_dna_rdy;
      assign dna_o = s_dna;
      //! Instance Xilinx Macro
      DNA_PORTE2 # (
      .SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_DNA_PORTE2 (
      .CLK (clk_i),
      .DIN ('h0),
      .READ (s_read), //! input: load DNA
      .SHIFT (s_shift), //! input: shift enable input
      .DOUT (s_data) //! output: DNA output bit
      );
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/src/fpga_device.v 0 → 100644
      View file @ a292404f
      //==============================================================================
      //! @file fpga_device.v
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - FPGA Version Device --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: fpga_device
      //
      //! @brief FPGA Version Device
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 06/05/2022
      //
      //! @details
      //
      //! @URL: https://ohwr.org/project/fpga-dev-id/wikis
      //
      //------------------------------------------------------------------------------
      module fpga_device # (
      parameter g_VENDOR_ID = 32'h0,
      parameter g_DEVICE_ID = 32'h0,
      parameter g_VERSION = 32'h0,
      parameter g_BYTE_ORD_MARK = 32'h0,
      parameter g_SOURCE_ID = 128'h0,
      parameter g_CAP_MASK = 32'h0,
      parameter g_VENDOR_UUID = 128'h0,
      parameter g_CORE_ID = 32'h0,
      parameter g_NAME = 64'h0,
      parameter g_BUILD_DATE = 32'd0,
      parameter g_HASH = 160'h0,
      parameter g_TAG = 64'h0,
      parameter g_S_AXI_DATA_WIDTH = 32,
      parameter g_S_AXI_ADDR_WIDTH = 8,
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      )
      (
      // Clock && RESET
      input S_AXI_ARESETN,
      input S_AXI_ACLK,
      //! Slave Interface Write Address Ports
      input [g_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
      input [2:0] S_AXI_AWPROT,
      input S_AXI_AWVALID,
      output S_AXI_AWREADY,
      //! Slave Interface Write Data Ports
      input [g_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
      input [(g_S_AXI_DATA_WIDTH/8)-1:0] S_AXI_WSTRB,
      input S_AXI_WVALID,
      output S_AXI_WREADY,
      //! Slave Interface Write Response Ports
      output [1:0] S_AXI_BRESP,
      output S_AXI_BVALID,
      input S_AXI_BREADY,
      //! Slave Interface Read Address Ports
      input [g_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
      input [2:0] S_AXI_ARPROT,
      input S_AXI_ARVALID,
      output S_AXI_ARREADY,
      //! Slave Interface Read Data Ports
      output [g_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
      output [1:0] S_AXI_RRESP,
      output S_AXI_RVALID,
      input S_AXI_RREADY
      );
      //! Unused lines WRITE
      assign S_AXI_AWREADY = 1'b0;
      assign S_AXI_WREADY = 1'b0;
      assign S_AXI_BRESP = 2'b0;
      assign S_AXI_BVALID = 1'b0;
      //! Unused lines READ
      assign S_AXI_RRESP = 2'b00;
      //! Constants
      localparam c_ZEROS = {g_S_AXI_DATA_WIDTH{1'b0}};
      localparam c_LSB_ADDR = (g_S_AXI_DATA_WIDTH / 32) + 1;
      localparam c_ADDR_VENDOR_ID = 'h00;
      localparam c_ADDR_DEVICE_ID = 'h01;
      localparam c_ADDR_VERSION = 'h02;
      localparam c_ADDR_BYTE_ORD_MARK = 'h03;
      localparam c_ADDR_SOURCE_ID_0 = 'h04;
      localparam c_ADDR_SOURCE_ID_1 = 'h05;
      localparam c_ADDR_SOURCE_ID_2 = 'h06;
      localparam c_ADDR_SOURCE_ID_3 = 'h07;
      localparam c_ADDR_CAP_MASK = 'h08;
      localparam c_ADDR_VENDOR_UUID_0 = 'h0C;
      localparam c_ADDR_VENDOR_UUID_1 = 'h0D;
      localparam c_ADDR_VENDOR_UUID_2 = 'h0E;
      localparam c_ADDR_VENDOR_UUID_3 = 'h0F;
      localparam c_ADDR_CORE_ID = 'h10;
      localparam c_ADDR_NAME_LSB = 'h11;
      localparam c_ADDR_NAME_MSB = 'h12;
      localparam c_ADDR_BUILD_T = 'h13;
      localparam c_ADDR_HASH_0 = 'h14;
      localparam c_ADDR_HASH_1 = 'h15;
      localparam c_ADDR_HASH_2 = 'h16;
      localparam c_ADDR_HASH_3 = 'h17;
      localparam c_ADDR_HASH_4 = 'h18;
      localparam c_ADDR_DNA_0 = 'h19;
      localparam c_ADDR_DNA_1 = 'h1A;
      localparam c_ADDR_DNA_2 = 'h1B;
      localparam c_ADDR_TAG_LSB = 'h1C;
      localparam c_ADDR_TAG_MSB = 'h1D;
      //! Axi lite auxiliary regs
      reg [g_S_AXI_ADDR_WIDTH-1:0] s_araddr;
      reg s_arready;
      reg s_rvalid;
      //! User lines
      reg [g_S_AXI_DATA_WIDTH-1:0] s_RDATA;
      wire [g_S_AXI_ADDR_WIDTH-c_LSB_ADDR-1:0] s_RADDR;
      wire s_REN;
      //! DNA
      wire [95:0] s_dna;
      //--------------------------------------------------------------------------
      //! ARREADY LOGIC & ARADDR Latch
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      begin : p_arready
      if (! S_AXI_ARESETN) begin
      s_araddr <= 'h0;
      s_arready <= 1'b0;
      end
      else begin
      if (!s_arready && S_AXI_ARVALID) begin
      s_araddr <= S_AXI_ARADDR;
      s_arready <= 1'b1;
      end
      else begin
      s_araddr <= s_araddr;
      s_arready <= 1'b0;
      end
      end
      end : p_arready
      assign S_AXI_ARREADY = s_arready;
      //! RVALID
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      begin : p_rvalid
      if (! S_AXI_ARESETN)
      s_rvalid <= 1'b0;
      else begin
      if (~(s_rvalid) & s_arready & S_AXI_ARVALID)
      s_rvalid <= 1'b1;
      else if (s_rvalid & S_AXI_RREADY)
      s_rvalid <= 1'b0;
      end
      end : p_rvalid
      //! Read assignment
      assign s_RADDR = s_araddr[g_S_AXI_ADDR_WIDTH-1:c_LSB_ADDR];
      assign s_REN = ~(s_rvalid) & s_arready & S_AXI_ARVALID;
      //! Register Access
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      begin : p_read
      if (! S_AXI_ARESETN)
      s_RDATA <= 'h0;
      else begin
      if (s_REN) begin
      case(s_RADDR)
      c_ADDR_VENDOR_ID : s_RDATA <= g_VENDOR_ID;
      c_ADDR_DEVICE_ID : s_RDATA <= g_DEVICE_ID;
      c_ADDR_VERSION : s_RDATA <= g_VERSION;
      c_ADDR_BYTE_ORD_MARK : s_RDATA <= g_BYTE_ORD_MARK;
      c_ADDR_SOURCE_ID_0 : s_RDATA <= g_SOURCE_ID[31:0];
      c_ADDR_SOURCE_ID_1 : s_RDATA <= g_SOURCE_ID[63:32];
      c_ADDR_SOURCE_ID_2 : s_RDATA <= g_SOURCE_ID[95:64];
      c_ADDR_SOURCE_ID_3 : s_RDATA <= g_SOURCE_ID[127:96];
      c_ADDR_CAP_MASK : s_RDATA <= g_CAP_MASK;
      c_ADDR_VENDOR_UUID_0 : s_RDATA <= s_dna[31:0];
      c_ADDR_VENDOR_UUID_1 : s_RDATA <= {g_VENDOR_UUID[63:48],s_dna[47:32]};
      c_ADDR_VENDOR_UUID_2 : s_RDATA <= g_VENDOR_UUID[95:64];
      c_ADDR_VENDOR_UUID_3 : s_RDATA <= g_VENDOR_UUID[127:96];
      c_ADDR_CORE_ID : s_RDATA <= g_CORE_ID;
      c_ADDR_NAME_LSB : s_RDATA <= g_NAME[31:0];
      c_ADDR_NAME_MSB : s_RDATA <= g_NAME[63:32];
      c_ADDR_BUILD_T : s_RDATA <= g_BUILD_DATE;
      c_ADDR_HASH_0 : s_RDATA <= g_HASH[31:0];
      c_ADDR_HASH_1 : s_RDATA <= g_HASH[63:32];
      c_ADDR_HASH_2 : s_RDATA <= g_HASH[95:64];
      c_ADDR_HASH_3 : s_RDATA <= g_HASH[127:96];
      c_ADDR_HASH_4 : s_RDATA <= g_HASH[159:128];
      c_ADDR_DNA_0 : s_RDATA <= s_dna[31:0];
      c_ADDR_DNA_1 : s_RDATA <= s_dna[63:32];
      c_ADDR_DNA_2 : s_RDATA <= s_dna[95:64];
      c_ADDR_TAG_LSB : s_RDATA <= g_TAG[31:0];
      c_ADDR_TAG_MSB : s_RDATA <= g_TAG[63:32];
      default : s_RDATA <= c_ZEROS;
      endcase
      end
      end
      end : p_read
      //! Assign outputs
      assign S_AXI_RDATA = s_RDATA;
      assign S_AXI_RVALID = s_rvalid;
      //--------------------------------------------------------------------------
      dna_reader # (
      .g_SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_dna_reader (
      .clk_i (S_AXI_ACLK),
      .rst_n_i (S_AXI_ARESETN),
      .dna_rdy_o (),
      .dna_o (s_dna)
      );
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/tb/dna_reader_tb.sv 0 → 100644
      View file @ a292404f
      //==============================================================================
      //! @file dna_reader_tb.sv
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - TestBench DNA Reader Xilinx FPGA --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: TestBench DNA Reader Xilinx FPGA
      //
      //! @brief TestBench DNA Reader Xilinx FPGA
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 12/05/2022
      //
      //------------------------------------------------------------------------------
      module dna_reader_tb # (
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      );
      //! Define time units
      timeunit 1ns;
      //! Define stimulus
      wire [95:0] s_dna;
      reg s_clk;
      reg s_rst_n;
      wire s_dna_rdy;
      dna_reader # (
      .g_SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_dna_reader (
      .clk_i (s_clk),
      .rst_n_i (s_rst_n),
      .dna_rdy_o (s_dna_rdy),
      .dna_o (s_dna)
      );
      //! Initial block
      initial
      begin : p_initial
      s_rst_n = 1'b0;
      s_clk = 1'b0;
      end : p_initial
      //! Clock generator
      always
      begin : p_clock
      #5 s_clk = 1'b1;
      #5 s_clk = 1'b0;
      end : p_clock
      //! Clock generator
      always
      begin : p_rst
      #25 s_rst_n = 1'b1;
      end : p_rst
      //! Check Result
      initial
      begin : p_result
      @(posedge s_dna_rdy)
      assert (s_dna == g_SIM_DNA_VALUE) $display("Result is correct");
      else begin
      $error("Failure in simulation");
      $error("Generic value: %X", g_SIM_DNA_VALUE);
      $error("Expecter Valuer: %X", s_dna);
      end
      end : p_result
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/tcl/fpga_device.tcl 0 → 100644
      View file @ a292404f
      ################################################################################
      #
      # Author: alen.arias.vazquez@cern.ch
      # Date: 10/05/2022
      #
      ################################################################################
      # Get Git Hash
      proc get_git_hash {} {
      return [ exec git rev-parse --short=40 HEAD ]
      }
      # Get Git Tag
      proc get_git_tag {} {
      set git_tag_check [ catch { exec git describe --tags --abbrev=0 --dirty=D } msg ]
      if { $git_tag_check == 1 } {
      write_yellow "Any tag has not been defined yet in the current repository"
      return "v0.0.0"
      } else {
      return $msg
      }
      }
      # Conver Git Tag to number:
      # bits 31-24: major number
      # bits 23-16: minor number
      # bits 15-00: patch number
      proc convert_tag_to_number { tag } {
      # Highest v255.255.65535
      if { [ string range $tag 0 0 ] == "v" } {
      # Remove v
      set tag [ string range $tag 1 end ]
      if { [ string range $tag end end ] == "D" } {
      # Remove Dirty
      set tag [ string range $tag 0 end-1 ]
      }
      set list_num [ split $tag {.} ]
      if { [ llength $list_num ] == 3 } {
      set major [ format %02X [ lindex $list_num 0 ] ]
      set minor [ format %02X [ lindex $list_num 1 ] ]
      set patch [ format %04X [ lindex $list_num 2 ] ]
      return [ concat $major$minor$patch ]
      } else {
      return 0
      }
      } else {
      return 0
      }
      }
      # Convert String to Hex String
      proc convert_string_to_hex { str size } {
      while { $size > [ string length $str ] } {
      set str [ concat -$str ]
      }
      binary scan $str H* hex
      return $hex
      }
      # Generate UUID
      proc generate_uuid {} {
      set str [ info hostname ]
      binary scan $str H* hex_value
      set uuid [ format %2.2x [ clock seconds ]]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 0 3 ]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 2 5 ]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 4 7 ]
      append uuid [ string range $hex_value 0 11]
      return $uuid
      }
      proc print_uuid { hex_uuid } {
      return [ concat [ string range $hex_uuid 0 7 ]-[ string range $hex_uuid 8 11 ]-[ string range $hex_uuid 12 15 ]-[ string range $hex_uuid 16 19 ]-[ string range $hex_uuid 20 end ] ]
      }
      proc create_fpga_version { name ref target } {
      # Parameters that are Constants:
      set vendor_id "FF000000"
      set device_id "44494F5A"
      set byte_ord "FFFE0000"
      set cap_mask "AAAAAAAA"
      # IP CORE ID
      set core_id "46504741"
      # Get git parameters
      set git_hash [ get_git_hash ]
      set git_tag [ get_git_tag ]
      # Get DATE
      set build_date [ clock seconds ]
      # Cut Commit hash
      set source_id [ string range $git_hash 8 end ]
      # UUID
      set uuid [ generate_uuid ]
      # Convert string to hex
      set name_hex [ convert_string_to_hex $name 8 ]
      set git_tag_hex [ convert_string_to_hex $git_tag 8 ]
      set num_version [ convert_tag_to_number $git_tag ]
      # Open input and output file
      set r_file [open $ref r]
      set w_file [open $target w]
      # Map for replace strings
      set map {}
      lappend map "parameter g_VENDOR_ID = 32'h0," "parameter g_VENDOR_ID = 32'h$vendor_id,"
      lappend map "parameter g_DEVICE_ID = 32'h0," "parameter g_DEVICE_ID = 32'h$device_id,"
      lappend map "parameter g_VERSION = 32'h0," "parameter g_VERSION = 32'h$num_version,"
      lappend map "parameter g_BYTE_ORD_MARK = 32'h0," "parameter g_BYTE_ORD_MARK = 32'h$byte_ord,"
      lappend map "parameter g_SOURCE_ID = 128'h0," "parameter g_SOURCE_ID = 128'h$source_id,"
      lappend map "parameter g_CAP_MASK = 32'h0," "parameter g_CAP_MASK = 32'h$cap_mask,"
      lappend map "parameter g_VENDOR_UUID = 128'h0," "parameter g_VENDOR_UUID = 128'h$uuid,"
      lappend map "parameter g_CORE_ID = 32'h0," "parameter g_CORE_ID = 32'h$core_id,"
      lappend map "parameter g_NAME = 64'h0," "parameter g_NAME = 64'h$name_hex,"
      lappend map "parameter g_BUILD_DATE = 32'd0," "parameter g_BUILD_DATE = 32'd$build_date,"
      lappend map "parameter g_HASH = 160'h0," "parameter g_HASH = 160'h$git_hash,"
      lappend map "parameter g_TAG = 64'h0," "parameter g_TAG = 64'h$git_tag_hex,"
      write_green ""
      write_green "Fpga Device Generation:"
      write_green "Vendor ID: 0x$vendor_id"
      write_green "Device ID: 0x$device_id"
      write_green "Number Version: 0x$num_version"
      write_green "Byte Order Mark: 0x$byte_ord"
      write_green "Source ID: $source_id"
      write_green "Capability Mask: 0x$cap_mask"
      write_green "Vendor UUID: [ print_uuid $uuid ]"
      write_green "IP Core ID: 0x$core_id"
      write_green "Project name: $name"
      write_green "Build Date: [ clock format $build_date -format "%Y-%m-%d %H:%M:%S" ]"
      write_green "Git Hash: $git_hash"
      write_green "Git Tag: $git_tag"
      write_green ""
      # Copy files
      while { [ gets $r_file r_line ] >= 0 } {
      set w_line [ string map $map $r_line]
      puts $w_file $w_line
      }
      # Closes files
      close $r_file
      close $w_file
      }
      gw/docker/Dockerbuild.sh 0 → 100644
      View file @ a292404f
      #!/bin/sh
      docker build -f Dockerfile -t vivado .
      gw/docker/Dockerfile 0 → 100644
      View file @ a292404f
      FROM ubuntu:18.04
      ENV TERM xterm
      RUN dpkg --add-architecture i386
      RUN echo 'APT::Install-Recommends "0";\nAPT::Install-Suggests "0";' > /etc/apt/apt.conf.d/01norecommend
      RUN apt-get update
      ENV DEBIAN_FRONTEND=noninteractive
      RUN apt-get -y install locales
      RUN export LC_ALL=en_US.UTF-8
      RUN export LANG=en_US.UTF-8
      RUN locale-gen en_US.UTF-8
      RUN apt-get -y install bzip2 \
      libc6-i386 \
      libprotobuf-dev \
      libxtst6 \
      libxrender-dev \
      libxext6 \
      libx11-6 \
      libfontconfig1 \
      libglib2.0-0 \
      libxext6 \
      libxrender1 \
      libxtst6 \
      libgtk2.0-0 \
      build-essential \
      net-tools \
      pkg-config \
      xauth \
      xvfb \
      bash-completion \
      ssh \
      bc \
      tmux \
      x11-utils \
      dbus-x11 \
      ca-certificates \
      libswt-gtk-4-java \
      libswt-gtk-4-jni \
      gcc-multilib \
      g++-multilib \
      git \
      vim
      RUN apt-get -y install libstdc++6:i386
      RUN apt-get -y install libgtk2.0-0:i386
      RUN apt-get -y install dpkg-dev:i386
      RUN apt-get -y install libtinfo5 libncurses5
      RUN apt-get clean autoclean
      RUN apt-get autoremove -y
      RUN ln -s /usr/bin/make /usr/bin/gmake
      gw/docker/docker_run.sh 0 → 100644
      View file @ a292404f
      #!/usr/bin/env sh
      XILINX_TOOLS=/opt/Xilinx
      docker run \
      -v "$HOME":"$HOME" \
      -v /etc/passwd:/etc/passwd:ro \
      -v /etc/shadow:/etc/shadow:ro \
      -v /etc/group:/etc/group:ro \
      -v ${XILINX_TOOLS}:${XILINX_TOOLS} \
      -v /tmp/.X11-unix:/tmp/.X11-unix \
      -v /tmp:/tmp \
      -e DISPLAY=$DISPLAY \
      --privileged \
      --net=host \
      -i -w "$PWD" -u $(id -u):$(id -g) -t --rm \
      vivado bash
      gw/functions.tcl 0 → 100644
      View file @ a292404f
      ################################################################################
      #
      # Common functions for different projects
      #
      ################################################################################
      # Write console message in red
      proc write_red { msg } {
      puts -nonewline "\033\[1;31m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_green { msg } {
      puts -nonewline "\033\[1;32m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_yellow { msg } {
      puts -nonewline "\033\[1;33m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_blue { msg } {
      puts -nonewline "\033\[1;34m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in different colors
      proc write_msg { msg severity } {
      switch ${severity} {
      "1" {
      write_green $msg
      }
      "2" {
      write_yellow $msg
      }
      "3" {
      write_red $msg
      }
      default {
      write_blue $msg
      }
      }
      }
      # Returns the number of CPUs for the build
      # To set the build number of threads in Vivado
      proc get_number_cpus {} {
      global tcl_platform env
      switch ${tcl_platform(platform)} {
      "windows" {
      return $env(NUMBER_OF_PROCESSORS)
      }
      "unix" {
      if {![catch {open "/proc/cpuinfo"} f]} {
      set cores [regexp -all -line {^processor\s} [read $f]]
      close $f
      if {$cores > 0} {
      return $cores
      }
      }
      }
      default {
      write_msg "Unknown System" "3"
      return 1
      }
      }
      }
      # Define Vhdl src
      proc add_vhdl_src { lib src} {
      lappend ::user_list(SRC_VHDL) ${src}
      lappend ::user_list(LIB_VHDL) ${lib}
      }
      # Define Vhdl08 src
      proc add_vhdl08_src { lib src} {
      lappend ::user_list(SRC_VHDL08) ${src}
      lappend ::user_list(LIB_VHDL08) ${lib}
      }
      # Define Verilog/SystemVerilog src
      proc add_source { src } {
      lappend ::user_list(SRC_VERILOG) ${src}
      }
      # Define Constraint files
      proc add_constraint { file } {
      lappend ::user_list(CONSTRAINT) ${file}
      }
      # Define array property
      proc set_user_property { name value } {
      lappend ::user_list(PROP_NAME) ${name}
      lappend ::user_list(PROP_VAL) ${value}
      }
      # Return list
      proc get_list { list_name } {
      return [ set ::user_list(${list_name}) ]
      }
      # Return list size
      proc get_list_size { list_name } {
      return [ llength [ get_list ${list_name} ] ]
      }
      # Check if verilog source is SystemVerilog
      proc enable_sv_compilation { filename } {
      set extension [ file extension $filename ]
      if { [ string equal ${extension} ".sv" ] } {
      return 1
      } else {
      return 0
      }
      }
      gw/projects/diot_v1/constraints/diot_v1.xdc 0 → 100644
      View file @ a292404f
      ################################################################################
      #
      # Constraints for DIOT System Board Version 1
      #
      ################################################################################
      set_property PACKAGE_PIN AJ4 [get_ports sfp_rxp]
      set_property PACKAGE_PIN AJ3 [get_ports sfp_rxn]
      set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
      set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
      set_property PACKAGE_PIN K22 [get_ports {emio_i2c_scl[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {emio_i2c_scl[0]}]
      set_property PACKAGE_PIN J20 [get_ports {emio_i2c_sda[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {emio_i2c_sda[0]}]
      #gtref_clock
      set_property PACKAGE_PIN AH10 [get_ports gtrefclk_in_clk_p]
      #125 MHz
      create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports gtrefclk_in_clk_p]
      set_property IOSTANDARD LVCMOS18 [get_ports *led]
      #GPIO_LED[1]
      #From SFP_ACT_LED from schematic
      set_property PACKAGE_PIN J30 [get_ports {link_status_led[0]}]
      #GPIO_LED[2]
      #From SFP_LINK_LED from schematic
      #GPIO_LED[4]
      #From USER_LED2 from schematic
      set_property PACKAGE_PIN AL26 [get_ports pl_reset_led]
      #GPIO_LED[5]
      #From USER_LED1 from schematic
      set_property PACKAGE_PIN AT27 [get_ports {mdc_clk_led[0]}]
      set_property PACKAGE_PIN K27 [get_ports {link_sync_led[0]}]
      set_property PACKAGE_PIN A11 [get_ports {M_SCL_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {M_SCL_0[0]}]
      set_property PACKAGE_PIN A12 [get_ports {M_SDA_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {M_SDA_0[0]}]
      set_property PACKAGE_PIN H14 [get_ports {p_pres_i_0[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {p_pres_i_0[1]}]
      set_property PACKAGE_PIN G14 [get_ports {p_pres_i_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {p_pres_i_0[0]}]
      set_property PACKAGE_PIN A31 [get_ports pwr_cycle_req_o_0]
      set_property IOSTANDARD LVCMOS18 [get_ports pwr_cycle_req_o_0]
      set_property PACKAGE_PIN AL12 [get_ports {wrflash_scl[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {wrflash_scl[0]}]
      set_property PACKAGE_PIN AT15 [get_ports {wrflash_sda[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {wrflash_sda[0]}]
      set_property PACKAGE_PIN B15 [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN A13 [get_ports {bckpl_servmod_b[1]}]
      set_property PACKAGE_PIN B13 [get_ports {bckpl_servmod_b[2]}]
      set_property PACKAGE_PIN B14 [get_ports {bckpl_servmod_b[3]}]
      set_property PACKAGE_PIN C14 [get_ports {bckpl_servmod_b[4]}]
      set_property PACKAGE_PIN C13 [get_ports {bckpl_servmod_b[5]}]
      set_property PACKAGE_PIN D14 [get_ports {bckpl_servmod_b[6]}]
      set_property PACKAGE_PIN A15 [get_ports {bckpl_servmod_b[7]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[7]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[6]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[5]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[4]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[3]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[2]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN H11 [get_ports bckpl_rst_n_o]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_rst_n_o]
      set_property PACKAGE_PIN AR8 [get_ports psu_alert_i]
      set_property IOSTANDARD LVCMOS18 [get_ports psu_alert_i]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_scl]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_sda]
      set_property PACKAGE_PIN F15 [get_ports bckpl_scl]
      set_property PACKAGE_PIN G15 [get_ports bckpl_sda]
      set_property PULLUP true [get_ports {bckpl_servmod_b[7]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[6]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[5]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[4]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[3]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[2]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[1]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN AW5 [get_ports {clk_src_sel_o[1]}]
      set_property PACKAGE_PIN AH17 [get_ports {clk_src_sel_o[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {clk_src_sel_o[1]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {clk_src_sel_o[0]}]
      set_property PACKAGE_PIN J10 [get_ports f_rst]
      set_property IOSTANDARD LVCMOS33 [get_ports f_rst]
      gw/projects/diot_v1/src/constants.vhd 0 → 100644
      View file @ a292404f
      ----------------------------------------------------------------------------------
      -- Company:
      -- Engineer:
      --
      -- Create Date: 06/28/2021 04:30:23 PM
      -- Design Name:
      -- Module Name: constants - Behavioral
      -- Project Name:
      -- Target Devices:
      -- Tool Versions:
      -- Description:
      --
      -- Dependencies:
      --
      -- Revision:
      -- Revision 0.01 - File Created
      -- Additional Comments:
      --
      ----------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      -- Uncomment the following library declaration if instantiating
      -- any Xilinx leaf cells in this code.
      --library UNISIM;
      --use UNISIM.VComponents.all;
      entity constants is
      generic (
      g_phyaddr : integer := 9;
      g_config_vector : integer := 0;
      g_config_valid : integer := 0;
      g_signal_detect : integer := 1);
      Port (
      pl_clk_i : in std_logic;
      -- Vector indicating status. We need bits 0 and 1 of the vector
      status_vector : in std_logic_vector(15 downto 0);
      -- Management clock, (<= 2.5MHz)
      mdc_i : in std_logic;
      mdc_clk_led : out std_logic;
      -- Reset of the module, coming from PS
      pl_resetn_i : in std_logic;
      reset_o : out std_logic;
      -- Autoneg
      an_config_o : out std_logic;
      an_config_vec_o : out std_logic_vector(15 downto 0);
      -- EMIO GPIOs
      p_pres_i : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      psu_alert_i : in std_logic;
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t_o : out std_logic;
      ps_emio_o : out std_logic_vector(15 downto 0);
      ps_emio_i : in std_logic_vector(15 downto 0);
      ps_emio_t_i : in std_logic_vector(15 downto 0);
      -- I2C busses
      wrflash_i2c_irq_i : in std_logic;
      m_i2c_irq_i : in std_logic;
      bckpl_i2c_irq_i : in std_logic;
      ps_irq_o : out std_logic_vector(2 downto 0);
      -- Constants module
      -- Addr of the PHY device(slave). A constant number
      phyaddr : out std_logic_vector(4 downto 0);
      configuration_vector : out std_logic_vector(4 downto 0);
      configuration_valid : out std_logic_vector(0 downto 0);
      --'1' (if not connected to an optical module), otherwise, default is '0'
      signal_detect : out std_logic_vector(0 downto 0);
      -- Slices module
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0));
      end constants;
      architecture Behavioral of constants is
      -- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
      signal s_cnt : unsigned(11 downto 0);
      signal s_mdc_led_o : std_logic;
      type t_pwr_state is (IDLE, RST);
      signal pwr_state : t_pwr_state;
      signal ps_emio2_d0 : std_logic;
      signal ps_emio2_p : std_logic;
      begin
      an_config_o <= '0';
      an_config_vec_o <= x"D801";
      phyaddr <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr'length));
      configuration_vector <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector'length));
      configuration_valid <= std_logic_vector(to_unsigned(g_config_valid, configuration_valid'length));
      signal_detect <= std_logic_vector(to_unsigned(g_signal_detect, signal_detect'length));
      reset_o <= '1' when (pl_resetn_i = '0') else
      '0';
      link_status_led <= status_vector(0);
      link_sync_led <= status_vector(1);
      clk_src_sel_o <= "11";
      calc_mdc:process(mdc_i, pl_resetn_i)
      begin
      if (pl_resetn_i = '0') then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '0';
      elsif (rising_edge(mdc_i)) then
      if (s_cnt = 4096-2) then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '1';
      else
      s_mdc_led_o <= '0';
      s_cnt <= s_cnt + 1;
      end if;
      end if;
      end process;
      mdc_clk_led <= s_mdc_led_o;
      -- EMIO -> PL GPIO
      ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
      ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else
      '0';
      process(pl_clk_i)
      begin
      if rising_edge(pl_clk_i) then
      ps_emio2_d0 <= ps_emio_i(2);
      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
      pwr_state <= IDLE;
      pwr_cycle_req_o <= '0';
      else
      if pwr_state = IDLE then
      pwr_cycle_req_o <= '0';
      if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
      pwr_state <= RST;
      end if;
      elsif pwr_state = RST then
      pwr_cycle_req_o <= '1';
      end if;
      end if;
      end if;
      end process;
      -- EMIO 83..90
      ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
      bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
      bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
      -- EMIO 91
      ps_emio_o(13) <= ps_emio_i(13);
      bckpl_rst_n_o <= ps_emio_i(13);
      -- EMIO 92
      ps_emio_o(14) <= psu_alert_i;
      -- EMIO 93
      ps_emio_o(15) <= f_rst_i;
      f_rst_o <= ps_emio_i(15);
      f_rst_t_o <= ps_emio_t_i(15);
      -- I2C irqs
      ps_irq_o(2 downto 0) <= bckpl_i2c_irq_i & m_i2c_irq_i & wrflash_i2c_irq_i;
      end Behavioral;
      gw/projects/diot_v1/src/diot_v1_top.vhd 0 → 100644
      View file @ a292404f
      --==============================================================================
      --! @file diot_v1_top.vhd
      --==============================================================================
      --------------------------------------------------------------------------------
      -- --
      -- CERN - DIOT V1 --
      -- --
      --------------------------------------------------------------------------------
      --
      -- unit name: diot_v1_top
      --
      --! @brief top level DIOT system board Version 1 based in ZynqMP+
      --
      --! @author alen.arias.vazquez@cern.ch
      --
      --! @date 05/04/2022
      --
      --------------------------------------------------------------------------------
      library ieee;
      library unisim;
      use ieee.std_logic_1164.all;
      use unisim.vcomponents.all;
      --==============================================================================
      --! Entity declaration for diot_v1_top
      --==============================================================================
      entity diot_v1_top is
      port (
      emio_i2c_scl : inout std_logic_vector(0 downto 0);
      emio_i2c_sda : inout std_logic_vector(0 downto 0);
      M_SCL_0 : inout std_logic_vector(0 downto 0);
      M_SDA_0 : inout std_logic_vector(0 downto 0);
      wrflash_scl : inout std_logic_vector(0 downto 0);
      wrflash_sda : inout std_logic_vector(0 downto 0);
      gtrefclk_in_clk_n : in std_logic;
      gtrefclk_in_clk_p : in std_logic;
      link_status_led : out std_logic_vector(0 downto 0);
      link_sync_led : out std_logic_vector(0 downto 0);
      mdc_clk_led : out std_logic_vector(0 downto 0);
      pl_reset_led : out std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      bckpl_servmod_b : inout std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      bckpl_scl : inout std_logic;
      bckpl_sda : inout std_logic;
      psu_alert_i : in std_logic;
      f_rst : inout std_logic;
      sfp_rxn : in std_logic;
      sfp_rxp : in std_logic;
      sfp_txn : out std_logic;
      sfp_txp : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end diot_v1_top;
      --==============================================================================
      --! Architecture declaration
      --==============================================================================
      architecture structure of diot_v1_top is
      component diot_v1 is
      port (
      link_status_led : out std_logic_vector(0 downto 0);
      link_sync_led : out std_logic_vector(0 downto 0);
      mdc_clk_led : out std_logic_vector(0 downto 0);
      emio_i2c_sda : inout std_logic_vector(0 downto 0);
      emio_i2c_scl : inout std_logic_vector(0 downto 0);
      M_SDA_0 : inout std_logic_vector(0 downto 0);
      M_SCL_0 : inout std_logic_vector(0 downto 0);
      wrflash_scl : inout std_logic_vector(0 downto 0);
      wrflash_sda : inout std_logic_vector(0 downto 0);
      pl_reset_led : out std_logic;
      gtrefclk_in_clk_n : in std_logic;
      gtrefclk_in_clk_p : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      bckpl_servmod_b : inout std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      bckpl_scl : inout std_logic_vector(0 downto 0);
      bckpl_sda : inout std_logic_vector(0 downto 0);
      psu_alert_i : in std_logic;
      f_rst : inout std_logic_vector(0 downto 0);
      sfp_rxn : in std_logic;
      sfp_rxp : in std_logic;
      sfp_txn : out std_logic;
      sfp_txp : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end component diot_v1;
      --==============================================================================
      --! Architecture begin
      --==============================================================================
      begin
      design_1_i: component diot_v1
      port map (
      emio_i2c_scl(0) => emio_i2c_scl(0),
      emio_i2c_sda(0) => emio_i2c_sda(0),
      M_SCL_0(0) => M_SCL_0(0),
      M_SDA_0(0) => M_SDA_0(0),
      wrflash_scl(0) => wrflash_scl(0),
      wrflash_sda(0) => wrflash_sda(0),
      gtrefclk_in_clk_n => gtrefclk_in_clk_n,
      gtrefclk_in_clk_p => gtrefclk_in_clk_p,
      link_status_led(0) => link_status_led(0),
      link_sync_led(0) => link_sync_led(0),
      mdc_clk_led(0) => mdc_clk_led(0),
      pl_reset_led => pl_reset_led,
      p_pres_i_0 => p_pres_i_0,
      pwr_cycle_req_o_0 => pwr_cycle_req_o_0,
      bckpl_servmod_b => bckpl_servmod_b,
      bckpl_rst_n_o => bckpl_rst_n_o,
      bckpl_scl(0) => bckpl_scl,
      bckpl_sda(0) => bckpl_sda,
      psu_alert_i => psu_alert_i,
      f_rst(0) => f_rst,
      sfp_rxn => sfp_rxn,
      sfp_rxp => sfp_rxp,
      sfp_txn => sfp_txn,
      sfp_txp => sfp_txp,
      clk_src_sel_o => clk_src_sel_o
      );
      end architecture structure;
      --==============================================================================
      -- architecture end
      --==============================================================================
      gw/projects/diot_v1/tcl/create_bd.tcl 0 → 100644
      View file @ a292404f
      # Proc to create Block Design
      proc create_block_design { parentCell design_name target_path } {
      # Define design name
      set block_design_name $design_name
      write_msg "INFO: Creating block design $block_design_name" "1"
      create_bd_design $block_design_name
      # Get object for parentCell
      set parentObj [get_bd_cells $parentCell]
      # Save current instance; Restore later
      set oldCurInst [current_bd_instance .]
      # Set parent object as current
      current_bd_instance $parentObj
      # Create interface ports
      set gtrefclk_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gtrefclk_in ]
      set_property -dict [ list \
      CONFIG.FREQ_HZ {100000000} \
      ] $gtrefclk_in
      # Create interface SFP
      set sfp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 sfp ]
      # Create ports
      set M_SCL_0 [ create_bd_port -dir IO -from 0 -to 0 M_SCL_0 ]
      set M_SDA_0 [ create_bd_port -dir IO -from 0 -to 0 M_SDA_0 ]
      set bckpl_rst_n_o [ create_bd_port -dir O bckpl_rst_n_o ]
      set bckpl_scl [ create_bd_port -dir IO -from 0 -to 0 bckpl_scl ]
      set bckpl_sda [ create_bd_port -dir IO -from 0 -to 0 bckpl_sda ]
      set bckpl_servmod_b [ create_bd_port -dir IO -from 7 -to 0 bckpl_servmod_b ]
      set clk_src_sel_o [ create_bd_port -dir O -from 1 -to 0 clk_src_sel_o ]
      set emio_i2c_scl [ create_bd_port -dir IO -from 0 -to 0 emio_i2c_scl ]
      set emio_i2c_sda [ create_bd_port -dir IO -from 0 -to 0 emio_i2c_sda ]
      set f_rst [ create_bd_port -dir IO -from 0 -to 0 f_rst ]
      set link_status_led [ create_bd_port -dir O -from 0 -to 0 link_status_led ]
      set link_sync_led [ create_bd_port -dir O -from 0 -to 0 link_sync_led ]
      set mdc_clk_led [ create_bd_port -dir O -from 0 -to 0 mdc_clk_led ]
      set p_pres_i_0 [ create_bd_port -dir I -from 1 -to 0 p_pres_i_0 ]
      set pl_reset_led [ create_bd_port -dir O -type rst pl_reset_led ]
      set psu_alert_i [ create_bd_port -dir I psu_alert_i ]
      set pwr_cycle_req_o_0 [ create_bd_port -dir O pwr_cycle_req_o_0 ]
      set wrflash_scl [ create_bd_port -dir IO -from 0 -to 0 wrflash_scl ]
      set wrflash_sda [ create_bd_port -dir IO -from 0 -to 0 wrflash_sda ]
      # Create instance: axi_iic_0, and set properties
      set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic axi_iic_0 ]
      # Create instance: axi_iic_1, and set properties
      set axi_iic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic axi_iic_1 ]
      set_property -dict [ list \
      CONFIG.IIC_FREQ_KHZ {100} \
      ] $axi_iic_1
      # Create instance: axi_iic_2, and set properties
      set axi_iic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic axi_iic_2 ]
      set_property -dict [ list \
      CONFIG.IIC_FREQ_KHZ {100} \
      ] $axi_iic_2
      # Create instance: constants_and_slices, and set properties
      set constants_and_slices [ create_bd_cell -type module -reference constants constants_and_slices ]
      set_property -dict [ list \
      CONFIG.POLARITY {ACTIVE_HIGH} \
      ] [ get_bd_pins /constants_and_slices/reset_o ]
      # Create instance: gig_ethernet_pcs_pma_0, and set properties
      set gig_ethernet_pcs_pma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:gig_ethernet_pcs_pma gig_ethernet_pcs_pma_0 ]
      set_property -dict [ list \
      CONFIG.Auto_Negotiation {true} \
      CONFIG.EMAC_IF_TEMAC {GEM} \
      CONFIG.Ext_Management_Interface {false} \
      CONFIG.GT_Location {X0Y3} \
      CONFIG.GTinEx {false} \
      CONFIG.LvdsRefClk {125} \
      CONFIG.Physical_Interface {Transceiver} \
      CONFIG.RefClkRate {125} \
      CONFIG.Standard {1000BASEX} \
      CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
      CONFIG.TransceiverControl {false} \
      ] $gig_ethernet_pcs_pma_0
      # Create instance: ps8_0_axi_periph, and set properties
      set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect ps8_0_axi_periph ]
      set_property -dict [ list \
      CONFIG.NUM_MI {3} \
      ] $ps8_0_axi_periph
      # Create instance: rst_ps8_0_50M, and set properties
      set rst_ps8_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset rst_ps8_0_50M ]
      # Create instance: util_ds_buf_0, and set properties
      set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_0 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_0
      # Create instance: util_ds_buf_1, and set properties
      set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_1 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_1
      # Create instance: util_ds_buf_2, and set properties
      set util_ds_buf_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_2 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_2
      # Create instance: util_ds_buf_3, and set properties
      set util_ds_buf_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_3 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_3
      # Create instance: util_ds_buf_4, and set properties
      set util_ds_buf_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_4 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_4
      # Create instance: util_ds_buf_5, and set properties
      set util_ds_buf_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_5 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_5
      # Create instance: util_ds_buf_6, and set properties
      set util_ds_buf_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_6 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      CONFIG.C_SIZE {8} \
      ] $util_ds_buf_6
      # Create instance: util_ds_buf_7, and set properties
      set util_ds_buf_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_7 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_7
      # Create instance: util_ds_buf_8, and set properties
      set util_ds_buf_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_8 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_8
      # Create instance: util_ds_buf_9, and set properties
      set util_ds_buf_9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf util_ds_buf_9 ]
      set_property -dict [ list \
      CONFIG.C_BUF_TYPE {IOBUF} \
      ] $util_ds_buf_9
      source $target_path/tcl/ps_cfg.tcl
      # Create interface connections
      connect_bd_intf_net -intf_net diff_clock_rtl_0_1 [get_bd_intf_ports gtrefclk_in] [get_bd_intf_pins gig_ethernet_pcs_pma_0/gtrefclk_in]
      connect_bd_intf_net -intf_net gig_ethernet_pcs_pma_0_sfp [get_bd_intf_ports sfp] [get_bd_intf_pins gig_ethernet_pcs_pma_0/sfp]
      connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
      connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins axi_iic_1/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
      connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axi_iic_2/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI]
      connect_bd_intf_net -intf_net zynqmp_ps_GMII_ENET0 [get_bd_intf_pins gig_ethernet_pcs_pma_0/gmii_gem_pcs_pma] [get_bd_intf_pins zynqmp_ps/GMII_ENET0]
      connect_bd_intf_net -intf_net zynqmp_ps_MDIO_ENET0 [get_bd_intf_pins gig_ethernet_pcs_pma_0/mdio_pcs_pma] [get_bd_intf_pins zynqmp_ps/MDIO_ENET0]
      connect_bd_intf_net -intf_net zynqmp_ps_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynqmp_ps/M_AXI_HPM0_FPD]
      # Create port connections
      connect_bd_net -net Net [get_bd_ports emio_i2c_scl] [get_bd_pins util_ds_buf_0/IOBUF_IO_IO]
      connect_bd_net -net Net1 [get_bd_ports emio_i2c_sda] [get_bd_pins util_ds_buf_1/IOBUF_IO_IO]
      connect_bd_net -net Net2 [get_bd_ports M_SDA_0] [get_bd_pins util_ds_buf_2/IOBUF_IO_IO]
      connect_bd_net -net Net3 [get_bd_ports M_SCL_0] [get_bd_pins util_ds_buf_3/IOBUF_IO_IO]
      connect_bd_net -net Net4 [get_bd_ports wrflash_sda] [get_bd_pins util_ds_buf_4/IOBUF_IO_IO]
      connect_bd_net -net Net5 [get_bd_ports wrflash_scl] [get_bd_pins util_ds_buf_5/IOBUF_IO_IO]
      connect_bd_net -net Net6 [get_bd_ports bckpl_servmod_b] [get_bd_pins util_ds_buf_6/IOBUF_IO_IO]
      connect_bd_net -net Net7 [get_bd_ports bckpl_scl] [get_bd_pins util_ds_buf_7/IOBUF_IO_IO]
      connect_bd_net -net Net8 [get_bd_ports bckpl_sda] [get_bd_pins util_ds_buf_8/IOBUF_IO_IO]
      connect_bd_net -net Net9 [get_bd_ports f_rst] [get_bd_pins util_ds_buf_9/IOBUF_IO_IO]
      connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins constants_and_slices/wrflash_i2c_irq_i]
      connect_bd_net -net axi_iic_0_scl_o [get_bd_pins axi_iic_0/scl_o] [get_bd_pins util_ds_buf_5/IOBUF_IO_I]
      connect_bd_net -net axi_iic_0_scl_t [get_bd_pins axi_iic_0/scl_t] [get_bd_pins util_ds_buf_5/IOBUF_IO_T]
      connect_bd_net -net axi_iic_0_sda_o [get_bd_pins axi_iic_0/sda_o] [get_bd_pins util_ds_buf_4/IOBUF_IO_I]
      connect_bd_net -net axi_iic_0_sda_t [get_bd_pins axi_iic_0/sda_t] [get_bd_pins util_ds_buf_4/IOBUF_IO_T]
      connect_bd_net -net axi_iic_1_iic2intc_irpt [get_bd_pins axi_iic_1/iic2intc_irpt] [get_bd_pins constants_and_slices/m_i2c_irq_i]
      connect_bd_net -net axi_iic_1_scl_o [get_bd_pins axi_iic_1/scl_o] [get_bd_pins util_ds_buf_3/IOBUF_IO_I]
      connect_bd_net -net axi_iic_1_scl_t [get_bd_pins axi_iic_1/scl_t] [get_bd_pins util_ds_buf_3/IOBUF_IO_T]
      connect_bd_net -net axi_iic_1_sda_o [get_bd_pins axi_iic_1/sda_o] [get_bd_pins util_ds_buf_2/IOBUF_IO_I]
      connect_bd_net -net axi_iic_1_sda_t [get_bd_pins axi_iic_1/sda_t] [get_bd_pins util_ds_buf_2/IOBUF_IO_T]
      connect_bd_net -net axi_iic_2_iic2intc_irpt [get_bd_pins axi_iic_2/iic2intc_irpt] [get_bd_pins constants_and_slices/bckpl_i2c_irq_i]
      connect_bd_net -net axi_iic_2_scl_o [get_bd_pins axi_iic_2/scl_o] [get_bd_pins util_ds_buf_7/IOBUF_IO_I]
      connect_bd_net -net axi_iic_2_scl_t [get_bd_pins axi_iic_2/scl_t] [get_bd_pins util_ds_buf_7/IOBUF_IO_T]
      connect_bd_net -net axi_iic_2_sda_o [get_bd_pins axi_iic_2/sda_o] [get_bd_pins util_ds_buf_8/IOBUF_IO_I]
      connect_bd_net -net axi_iic_2_sda_t [get_bd_pins axi_iic_2/sda_t] [get_bd_pins util_ds_buf_8/IOBUF_IO_T]
      connect_bd_net -net constants_0_configuration_valid [get_bd_pins constants_and_slices/configuration_valid] [get_bd_pins gig_ethernet_pcs_pma_0/configuration_valid]
      connect_bd_net -net constants_0_configuration_vector [get_bd_pins constants_and_slices/configuration_vector] [get_bd_pins gig_ethernet_pcs_pma_0/configuration_vector]
      connect_bd_net -net constants_0_link_status_led [get_bd_ports link_status_led] [get_bd_pins constants_and_slices/link_status_led]
      connect_bd_net -net constants_0_link_sync_led [get_bd_ports link_sync_led] [get_bd_pins constants_and_slices/link_sync_led]
      connect_bd_net -net constants_0_mdc_clk_led [get_bd_ports mdc_clk_led] [get_bd_pins constants_and_slices/mdc_clk_led]
      connect_bd_net -net constants_0_phyaddr [get_bd_pins constants_and_slices/phyaddr] [get_bd_pins gig_ethernet_pcs_pma_0/phyaddr]
      connect_bd_net -net constants_0_signal_detect [get_bd_pins constants_and_slices/signal_detect] [get_bd_pins gig_ethernet_pcs_pma_0/signal_detect]
      connect_bd_net -net constants_and_slices_an_config_o [get_bd_pins constants_and_slices/an_config_o] [get_bd_pins gig_ethernet_pcs_pma_0/an_adv_config_val] [get_bd_pins gig_ethernet_pcs_pma_0/an_restart_config]
      connect_bd_net -net constants_and_slices_an_config_vec_o [get_bd_pins constants_and_slices/an_config_vec_o] [get_bd_pins gig_ethernet_pcs_pma_0/an_adv_config_vector]
      connect_bd_net -net constants_and_slices_bckpl_rst_n_o [get_bd_ports bckpl_rst_n_o] [get_bd_pins constants_and_slices/bckpl_rst_n_o]
      connect_bd_net -net constants_and_slices_bckpl_servmod_o [get_bd_pins constants_and_slices/bckpl_servmod_o] [get_bd_pins util_ds_buf_6/IOBUF_IO_I]
      connect_bd_net -net constants_and_slices_bckpl_servmod_t_o [get_bd_pins constants_and_slices/bckpl_servmod_t_o] [get_bd_pins util_ds_buf_6/IOBUF_IO_T]
      connect_bd_net -net constants_and_slices_clk_src_sel_o [get_bd_ports clk_src_sel_o] [get_bd_pins constants_and_slices/clk_src_sel_o]
      connect_bd_net -net constants_and_slices_f_rst_o [get_bd_pins constants_and_slices/f_rst_o] [get_bd_pins util_ds_buf_9/IOBUF_IO_I]
      connect_bd_net -net constants_and_slices_f_rst_t_o [get_bd_pins constants_and_slices/f_rst_t_o] [get_bd_pins util_ds_buf_9/IOBUF_IO_T]
      connect_bd_net -net constants_and_slices_ps_emio_o [get_bd_pins constants_and_slices/ps_emio_o] [get_bd_pins zynqmp_ps/emio_gpio_i]
      connect_bd_net -net constants_and_slices_ps_irq_o [get_bd_pins constants_and_slices/ps_irq_o] [get_bd_pins zynqmp_ps/pl_ps_irq0]
      connect_bd_net -net constants_and_slices_pwr_cycle_req_o [get_bd_ports pwr_cycle_req_o_0] [get_bd_pins constants_and_slices/pwr_cycle_req_o]
      connect_bd_net -net constants_and_slices_reset_o [get_bd_pins constants_and_slices/reset_o] [get_bd_pins gig_ethernet_pcs_pma_0/reset]
      connect_bd_net -net gig_ethernet_pcs_pma_0_status_vector [get_bd_pins constants_and_slices/status_vector] [get_bd_pins gig_ethernet_pcs_pma_0/status_vector]
      connect_bd_net -net p_pres_i_0_1 [get_bd_ports p_pres_i_0] [get_bd_pins constants_and_slices/p_pres_i]
      connect_bd_net -net psu_alert_i_0_1 [get_bd_ports psu_alert_i] [get_bd_pins constants_and_slices/psu_alert_i]
      connect_bd_net -net rst_ps8_0_50M_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_iic_1/s_axi_aresetn] [get_bd_pins axi_iic_2/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_50M/peripheral_aresetn]
      connect_bd_net -net util_ds_buf_0_IOBUF_IO_O [get_bd_pins util_ds_buf_0/IOBUF_IO_O] [get_bd_pins zynqmp_ps/emio_i2c1_scl_i]
      connect_bd_net -net util_ds_buf_1_IOBUF_IO_O [get_bd_pins util_ds_buf_1/IOBUF_IO_O] [get_bd_pins zynqmp_ps/emio_i2c1_sda_i]
      connect_bd_net -net util_ds_buf_2_IOBUF_IO_O [get_bd_pins axi_iic_1/sda_i] [get_bd_pins util_ds_buf_2/IOBUF_IO_O]
      connect_bd_net -net util_ds_buf_3_IOBUF_IO_O [get_bd_pins axi_iic_1/scl_i] [get_bd_pins util_ds_buf_3/IOBUF_IO_O]
      connect_bd_net -net util_ds_buf_4_IOBUF_IO_O [get_bd_pins axi_iic_0/sda_i] [get_bd_pins util_ds_buf_4/IOBUF_IO_O]
      connect_bd_net -net util_ds_buf_5_IOBUF_IO_O [get_bd_pins axi_iic_0/scl_i] [get_bd_pins util_ds_buf_5/IOBUF_IO_O]
      connect_bd_net -net util_ds_buf_6_IOBUF_IO_O [get_bd_pins constants_and_slices/bckpl_servmod_i] [get_bd_pins util_ds_buf_6/IOBUF_IO_O]
      connect_bd_net -net util_ds_buf_7_IOBUF_IO_O [get_bd_pins axi_iic_2/scl_i] [get_bd_pins util_ds_buf_7/IOBUF_IO_O]
      connect_bd_net -net util_ds_buf_8_IOBUF_IO_O [get_bd_pins axi_iic_2/sda_i] [get_bd_pins util_ds_buf_8/IOBUF_IO_O]
      connect_bd_net -net util_ds_buf_9_IOBUF_IO_O [get_bd_pins constants_and_slices/f_rst_i] [get_bd_pins util_ds_buf_9/IOBUF_IO_O]
      connect_bd_net -net zynqmp_ps_emio_enet0_mdio_mdc [get_bd_pins constants_and_slices/mdc_i] [get_bd_pins gig_ethernet_pcs_pma_0/mdc] [get_bd_pins zynqmp_ps/emio_enet0_mdio_mdc]
      connect_bd_net -net zynqmp_ps_emio_gpio_o [get_bd_pins constants_and_slices/ps_emio_i] [get_bd_pins zynqmp_ps/emio_gpio_o]
      connect_bd_net -net zynqmp_ps_emio_gpio_t [get_bd_pins constants_and_slices/ps_emio_t_i] [get_bd_pins zynqmp_ps/emio_gpio_t]
      connect_bd_net -net zynqmp_ps_emio_i2c1_scl_o [get_bd_pins util_ds_buf_0/IOBUF_IO_I] [get_bd_pins zynqmp_ps/emio_i2c1_scl_o]
      connect_bd_net -net zynqmp_ps_emio_i2c1_scl_t [get_bd_pins util_ds_buf_0/IOBUF_IO_T] [get_bd_pins zynqmp_ps/emio_i2c1_scl_t]
      connect_bd_net -net zynqmp_ps_emio_i2c1_sda_o [get_bd_pins util_ds_buf_1/IOBUF_IO_I] [get_bd_pins zynqmp_ps/emio_i2c1_sda_o]
      connect_bd_net -net zynqmp_ps_emio_i2c1_sda_t [get_bd_pins util_ds_buf_1/IOBUF_IO_T] [get_bd_pins zynqmp_ps/emio_i2c1_sda_t]
      connect_bd_net -net zynqmp_ps_pl_clk0 [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_iic_1/s_axi_aclk] [get_bd_pins axi_iic_2/s_axi_aclk] [get_bd_pins constants_and_slices/pl_clk_i] [get_bd_pins gig_ethernet_pcs_pma_0/independent_clock_bufg] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_50M/slowest_sync_clk] [get_bd_pins zynqmp_ps/maxihpm0_fpd_aclk] [get_bd_pins zynqmp_ps/pl_clk0]
      connect_bd_net -net zynqmp_ps_pl_resetn0 [get_bd_ports pl_reset_led] [get_bd_pins constants_and_slices/pl_resetn_i] [get_bd_pins rst_ps8_0_50M/ext_reset_in] [get_bd_pins zynqmp_ps/pl_resetn0]
      # Create address segments
      assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynqmp_ps/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] -force
      assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynqmp_ps/Data] [get_bd_addr_segs axi_iic_1/S_AXI/Reg] -force
      assign_bd_address -offset 0xA0020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynqmp_ps/Data] [get_bd_addr_segs axi_iic_2/S_AXI/Reg] -force
      # Restore current instance
      current_bd_instance $oldCurInst
      validate_bd_design
      save_bd_design
      close_bd_design $block_design_name
      }
      gw/projects/diot_v1/tcl/project_cfg.tcl 0 → 100644
      View file @ a292404f
      # Custom project settings
      set reference_part "xczu7cg-ffvf1517-1-e"
      set project_name "diot_v1"
      set entity_top "diot_v1_top"
      # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
      set max_threads 8
      set project_language "VHDL"
      set lib_default xil_defaultlib
      # Add properties
      set_user_property "default_lib" "xil_defaultlib"
      set_user_property "enable_vhdl_2008" "1"
      set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
      # Top Level
      add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
      # Vhdl Src
      add_vhdl_src ${lib_default} ../src/constants.vhd
      # Add Constraints
      add_constraint diot_v1.xdc
      gw/projects/diot_v1/tcl/ps_cfg.tcl 0 → 100644
      View file @ a292404f
      # Create instance: zynqmp_ps, and set properties
      write_msg "INFO: Adding ZynqMP PS Configuration" "1"
      set zynqmp_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynqmp_ps ]
      set_property -dict [ list \
      CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
      CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
      CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
      CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
      CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
      CONFIG.PSU_MIO_0_DIRECTION {out} \
      CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_0_POLARITY {Default} \
      CONFIG.PSU_MIO_10_DIRECTION {inout} \
      CONFIG.PSU_MIO_10_POLARITY {Default} \
      CONFIG.PSU_MIO_11_DIRECTION {inout} \
      CONFIG.PSU_MIO_11_POLARITY {Default} \
      CONFIG.PSU_MIO_12_DIRECTION {out} \
      CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_12_POLARITY {Default} \
      CONFIG.PSU_MIO_13_DIRECTION {inout} \
      CONFIG.PSU_MIO_13_POLARITY {Default} \
      CONFIG.PSU_MIO_14_DIRECTION {inout} \
      CONFIG.PSU_MIO_14_POLARITY {Default} \
      CONFIG.PSU_MIO_15_DIRECTION {inout} \
      CONFIG.PSU_MIO_15_POLARITY {Default} \
      CONFIG.PSU_MIO_16_DIRECTION {inout} \
      CONFIG.PSU_MIO_16_POLARITY {Default} \
      CONFIG.PSU_MIO_17_DIRECTION {inout} \
      CONFIG.PSU_MIO_17_POLARITY {Default} \
      CONFIG.PSU_MIO_18_DIRECTION {inout} \
      CONFIG.PSU_MIO_18_POLARITY {Default} \
      CONFIG.PSU_MIO_19_DIRECTION {inout} \
      CONFIG.PSU_MIO_19_POLARITY {Default} \
      CONFIG.PSU_MIO_1_DIRECTION {inout} \
      CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_1_POLARITY {Default} \
      CONFIG.PSU_MIO_1_SLEW {fast} \
      CONFIG.PSU_MIO_20_DIRECTION {inout} \
      CONFIG.PSU_MIO_20_POLARITY {Default} \
      CONFIG.PSU_MIO_21_DIRECTION {inout} \
      CONFIG.PSU_MIO_21_POLARITY {Default} \
      CONFIG.PSU_MIO_22_DIRECTION {out} \
      CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_22_POLARITY {Default} \
      CONFIG.PSU_MIO_26_DIRECTION {inout} \
      CONFIG.PSU_MIO_26_POLARITY {Default} \
      CONFIG.PSU_MIO_27_DIRECTION {inout} \
      CONFIG.PSU_MIO_27_POLARITY {Default} \
      CONFIG.PSU_MIO_28_DIRECTION {inout} \
      CONFIG.PSU_MIO_28_POLARITY {Default} \
      CONFIG.PSU_MIO_29_DIRECTION {inout} \
      CONFIG.PSU_MIO_29_POLARITY {Default} \
      CONFIG.PSU_MIO_2_DIRECTION {inout} \
      CONFIG.PSU_MIO_2_POLARITY {Default} \
      CONFIG.PSU_MIO_30_DIRECTION {inout} \
      CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_30_POLARITY {Default} \
      CONFIG.PSU_MIO_30_SLEW {fast} \
      CONFIG.PSU_MIO_31_DIRECTION {inout} \
      CONFIG.PSU_MIO_31_POLARITY {Default} \
      CONFIG.PSU_MIO_32_DIRECTION {inout} \
      CONFIG.PSU_MIO_32_POLARITY {Default} \
      CONFIG.PSU_MIO_33_DIRECTION {inout} \
      CONFIG.PSU_MIO_33_POLARITY {Default} \
      CONFIG.PSU_MIO_34_DIRECTION {inout} \
      CONFIG.PSU_MIO_34_POLARITY {Default} \
      CONFIG.PSU_MIO_35_DIRECTION {inout} \
      CONFIG.PSU_MIO_35_POLARITY {Default} \
      CONFIG.PSU_MIO_36_DIRECTION {inout} \
      CONFIG.PSU_MIO_36_POLARITY {Default} \
      CONFIG.PSU_MIO_37_DIRECTION {inout} \
      CONFIG.PSU_MIO_37_POLARITY {Default} \
      CONFIG.PSU_MIO_38_DIRECTION {inout} \
      CONFIG.PSU_MIO_38_POLARITY {Default} \
      CONFIG.PSU_MIO_39_DIRECTION {inout} \
      CONFIG.PSU_MIO_39_POLARITY {Default} \
      CONFIG.PSU_MIO_3_DIRECTION {inout} \
      CONFIG.PSU_MIO_3_POLARITY {Default} \
      CONFIG.PSU_MIO_40_DIRECTION {inout} \
      CONFIG.PSU_MIO_40_POLARITY {Default} \
      CONFIG.PSU_MIO_41_DIRECTION {inout} \
      CONFIG.PSU_MIO_41_POLARITY {Default} \
      CONFIG.PSU_MIO_42_DIRECTION {inout} \
      CONFIG.PSU_MIO_42_POLARITY {Default} \
      CONFIG.PSU_MIO_43_DIRECTION {inout} \
      CONFIG.PSU_MIO_43_POLARITY {Default} \
      CONFIG.PSU_MIO_44_DIRECTION {inout} \
      CONFIG.PSU_MIO_44_POLARITY {Default} \
      CONFIG.PSU_MIO_45_DIRECTION {inout} \
      CONFIG.PSU_MIO_45_POLARITY {Default} \
      CONFIG.PSU_MIO_46_DIRECTION {inout} \
      CONFIG.PSU_MIO_46_POLARITY {Default} \
      CONFIG.PSU_MIO_47_DIRECTION {inout} \
      CONFIG.PSU_MIO_47_POLARITY {Default} \
      CONFIG.PSU_MIO_48_DIRECTION {inout} \
      CONFIG.PSU_MIO_48_POLARITY {Default} \
      CONFIG.PSU_MIO_49_DIRECTION {inout} \
      CONFIG.PSU_MIO_49_POLARITY {Default} \
      CONFIG.PSU_MIO_4_DIRECTION {inout} \
      CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_4_POLARITY {Default} \
      CONFIG.PSU_MIO_50_DIRECTION {inout} \
      CONFIG.PSU_MIO_50_POLARITY {Default} \
      CONFIG.PSU_MIO_51_DIRECTION {out} \
      CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_51_POLARITY {Default} \
      CONFIG.PSU_MIO_52_DIRECTION {inout} \
      CONFIG.PSU_MIO_52_POLARITY {Default} \
      CONFIG.PSU_MIO_53_DIRECTION {inout} \
      CONFIG.PSU_MIO_53_POLARITY {Default} \
      CONFIG.PSU_MIO_54_DIRECTION {in} \
      CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_54_POLARITY {Default} \
      CONFIG.PSU_MIO_54_SLEW {fast} \
      CONFIG.PSU_MIO_55_DIRECTION {out} \
      CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_55_POLARITY {Default} \
      CONFIG.PSU_MIO_56_DIRECTION {inout} \
      CONFIG.PSU_MIO_56_POLARITY {Default} \
      CONFIG.PSU_MIO_57_DIRECTION {inout} \
      CONFIG.PSU_MIO_57_POLARITY {Default} \
      CONFIG.PSU_MIO_58_DIRECTION {inout} \
      CONFIG.PSU_MIO_58_POLARITY {Default} \
      CONFIG.PSU_MIO_59_DIRECTION {inout} \
      CONFIG.PSU_MIO_59_POLARITY {Default} \
      CONFIG.PSU_MIO_5_DIRECTION {out} \
      CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_5_POLARITY {Default} \
      CONFIG.PSU_MIO_60_DIRECTION {inout} \
      CONFIG.PSU_MIO_60_POLARITY {Default} \
      CONFIG.PSU_MIO_61_DIRECTION {inout} \
      CONFIG.PSU_MIO_61_POLARITY {Default} \
      CONFIG.PSU_MIO_62_DIRECTION {inout} \
      CONFIG.PSU_MIO_62_POLARITY {Default} \
      CONFIG.PSU_MIO_63_DIRECTION {inout} \
      CONFIG.PSU_MIO_63_POLARITY {Default} \
      CONFIG.PSU_MIO_64_DIRECTION {inout} \
      CONFIG.PSU_MIO_64_POLARITY {Default} \
      CONFIG.PSU_MIO_65_DIRECTION {inout} \
      CONFIG.PSU_MIO_65_POLARITY {Default} \
      CONFIG.PSU_MIO_66_DIRECTION {inout} \
      CONFIG.PSU_MIO_66_POLARITY {Default} \
      CONFIG.PSU_MIO_67_DIRECTION {inout} \
      CONFIG.PSU_MIO_67_POLARITY {Default} \
      CONFIG.PSU_MIO_68_DIRECTION {inout} \
      CONFIG.PSU_MIO_68_POLARITY {Default} \
      CONFIG.PSU_MIO_69_DIRECTION {inout} \
      CONFIG.PSU_MIO_69_POLARITY {Default} \
      CONFIG.PSU_MIO_70_DIRECTION {inout} \
      CONFIG.PSU_MIO_70_POLARITY {Default} \
      CONFIG.PSU_MIO_71_DIRECTION {inout} \
      CONFIG.PSU_MIO_71_POLARITY {Default} \
      CONFIG.PSU_MIO_72_DIRECTION {inout} \
      CONFIG.PSU_MIO_72_POLARITY {Default} \
      CONFIG.PSU_MIO_73_DIRECTION {inout} \
      CONFIG.PSU_MIO_73_POLARITY {Default} \
      CONFIG.PSU_MIO_74_DIRECTION {inout} \
      CONFIG.PSU_MIO_74_POLARITY {Default} \
      CONFIG.PSU_MIO_75_DIRECTION {inout} \
      CONFIG.PSU_MIO_75_POLARITY {Default} \
      CONFIG.PSU_MIO_76_DIRECTION {inout} \
      CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_76_POLARITY {Default} \
      CONFIG.PSU_MIO_77_DIRECTION {inout} \
      CONFIG.PSU_MIO_77_POLARITY {Default} \
      CONFIG.PSU_MIO_7_DIRECTION {out} \
      CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_7_POLARITY {Default} \
      CONFIG.PSU_MIO_8_DIRECTION {inout} \
      CONFIG.PSU_MIO_8_POLARITY {Default} \
      CONFIG.PSU_MIO_9_DIRECTION {inout} \
      CONFIG.PSU_MIO_9_POLARITY {Default} \
      CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash##Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0####I2C 0#I2C 0#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#GPIO2 MIO#GPIO2 MIO#UART 0#UART 0#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO} \
      CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out##n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out####scl_out#sda_out#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpio1[32]#gpio1[33]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#gpio1[43]#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#gpio2[52]#gpio2[53]#rxd#txd#gpio2[56]#gpio2[57]#gpio2[58]#gpio2[59]#gpio2[60]#gpio2[61]#gpio2[62]#gpio2[63]#gpio2[64]#gpio2[65]#gpio2[66]#gpio2[67]#gpio2[68]#gpio2[69]#gpio2[70]#gpio2[71]#gpio2[72]#gpio2[73]#gpio2[74]#gpio2[75]#gpio2[76]#gpio2[77]} \
      CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
      CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
      CONFIG.PSU__ACT_DDR_FREQ_MHZ {1200.000000} \
      CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
      CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
      CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {48} \
      CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {600.000000} \
      CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \
      CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
      CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {48} \
      CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25} \
      CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \
      CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
      CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.923077} \
      CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \
      CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
      CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {42} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
      CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
      CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125.000000} \
      CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {60} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {266.666656} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
      CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
      CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {16} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {50} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300.000000} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {32} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200.000000} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {16} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {50} \
      CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
      CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
      CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \
      CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
      CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
      CONFIG.PSU__DDRC__CL {17} \
      CONFIG.PSU__DDRC__CWL {12} \
      CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \
      CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
      CONFIG.PSU__DDRC__ECC {Enabled} \
      CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {ERR: 1 | 0} \
      CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
      CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
      CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400P} \
      CONFIG.PSU__DDRC__T_FAW {30.0} \
      CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \
      CONFIG.PSU__DDRC__T_RC {46.16} \
      CONFIG.PSU__DDRC__T_RCD {17} \
      CONFIG.PSU__DDRC__T_RP {17} \
      CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
      CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \
      CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {0} \
      CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \
      CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__DLL__ISUSED {1} \
      CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
      CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {1} \
      CONFIG.PSU__ENET0__GRP_MDIO__IO {EMIO} \
      CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__ENET0__PERIPHERAL__IO {EMIO} \
      CONFIG.PSU__ENET0__PTP__ENABLE {0} \
      CONFIG.PSU__ENET0__TSU__ENABLE {1} \
      CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
      CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
      CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__ENET1__PTP__ENABLE {0} \
      CONFIG.PSU__ENET1__TSU__ENABLE {0} \
      CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
      CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
      CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__ENET2__PTP__ENABLE {0} \
      CONFIG.PSU__ENET2__TSU__ENABLE {0} \
      CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
      CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
      CONFIG.PSU__ENET3__GRP_MDIO__IO {<Select>} \
      CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__ENET3__PERIPHERAL__IO {<Select>} \
      CONFIG.PSU__ENET3__PTP__ENABLE {0} \
      CONFIG.PSU__ENET3__TSU__ENABLE {0} \
      CONFIG.PSU__GEM0_COHERENCY {0} \
      CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__GEM1_COHERENCY {0} \
      CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__GEM2_COHERENCY {0} \
      CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__GEM3_COHERENCY {0} \
      CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__GEM__TSU__ENABLE {0} \
      CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
      CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
      CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__GPIO_EMIO_WIDTH {16} \
      CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {16} \
      CONFIG.PSU__GT__PRE_EMPH_LVL_4 {} \
      CONFIG.PSU__GT__VLT_SWNG_LVL_4 {} \
      CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \
      CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 26 .. 27} \
      CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__I2C1__PERIPHERAL__IO {EMIO} \
      CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
      CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \
      CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
      CONFIG.PSU__PCIE__BAR0_64BIT {0} \
      CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR0_VAL {} \
      CONFIG.PSU__PCIE__BAR1_64BIT {0} \
      CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR1_VAL {} \
      CONFIG.PSU__PCIE__BAR2_64BIT {0} \
      CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR2_VAL {} \
      CONFIG.PSU__PCIE__BAR3_64BIT {0} \
      CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR3_VAL {} \
      CONFIG.PSU__PCIE__BAR4_64BIT {0} \
      CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR4_VAL {} \
      CONFIG.PSU__PCIE__BAR5_64BIT {0} \
      CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR5_VAL {} \
      CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
      CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
      CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
      CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \
      CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
      CONFIG.PSU__PCIE__DEVICE_ID {} \
      CONFIG.PSU__PCIE__EROM_ENABLE {0} \
      CONFIG.PSU__PCIE__EROM_VAL {} \
      CONFIG.PSU__PCIE__INTX_GENERATION {0} \
      CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
      CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
      CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
      CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
      CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
      CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
      CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
      CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
      CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
      CONFIG.PSU__PCIE__REVISION_ID {} \
      CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
      CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
      CONFIG.PSU__PCIE__VENDOR_ID {} \
      CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;1|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
      CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
      CONFIG.PSU__PSS_REF_CLK__FREQMHZ {50} \
      CONFIG.PSU__QSPI_COHERENCY {0} \
      CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
      CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
      CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
      CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
      CONFIG.PSU__SATA__LANE0__ENABLE {0} \
      CONFIG.PSU__SATA__LANE1__ENABLE {0} \
      CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__SD0_COHERENCY {0} \
      CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__SD0__DATA_TRANSFER_MODE {8Bit} \
      CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
      CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
      CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
      CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 22} \
      CONFIG.PSU__SD0__RESET__ENABLE {0} \
      CONFIG.PSU__SD0__SLOT_TYPE {eMMC} \
      CONFIG.PSU__SD1_COHERENCY {0} \
      CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
      CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
      CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
      CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
      CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
      CONFIG.PSU__SD1__RESET__ENABLE {0} \
      CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
      CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
      CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
      CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
      CONFIG.PSU__UART0__BAUD_RATE {115200} \
      CONFIG.PSU__UART0__MODEM__ENABLE {0} \
      CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 54 .. 55} \
      CONFIG.PSU__USE__IRQ0 {1} \
      CONFIG.PSU__USE__M_AXI_GP0 {1} \
      CONFIG.PSU__USE__M_AXI_GP2 {0} \
      CONFIG.SUBPRESET1 {Custom} \
      ] $zynqmp_ps
      gw/projects/diot_v2/constraints/diot_v2.xdc 0 → 100644
      View file @ a292404f
      # ##############################################################################
      #
      # Constraints for DIOT System Board Version 2
      #
      # ##############################################################################
      # ------------------------------------------------------------------------------
      # GT REG CLK: 125 MHz
      set_property PACKAGE_PIN AH10 [get_ports {gtrefclk_in_clk_p}]
      create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports {gtrefclk_in_clk_p}]
      # ------------------------------------------------------------------------------
      # Clock Selector
      set_property -dict {PACKAGE_PIN AW5 IOSTANDARD LVCMOS18} [get_ports {clk_src_sel_o[1]}]
      set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVCMOS18} [get_ports {clk_src_sel_o[0]}]
      # ------------------------------------------------------------------------------
      # Power Cycle Request
      set_property -dict {PACKAGE_PIN A31 IOSTANDARD LVCMOS18} [get_ports {pwr_cycle_req_o_0}]
      # ------------------------------------------------------------------------------
      # BUS Monitor
      set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports {f_rst_b}]
      set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[0]}]
      set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[1]}]
      # ------------------------------------------------------------------------------
      # LEDs:
      # SFP_ACT_LED
      set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18} [get_ports {link_status_led}]
      # From USER_LED2 from schematic
      set_property -dict {PACKAGE_PIN AL26 IOSTANDARD LVCMOS18} [get_ports {pl_reset_led}]
      # From USER_LED1 from schematic
      set_property -dict {PACKAGE_PIN AT27 IOSTANDARD LVCMOS18} [get_ports {mdc_clk_led}]
      set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18} [get_ports {link_sync_led}]
      # ------------------------------------------------------------------------------
      # PSU Alert
      set_property -dict {PACKAGE_PIN AR8 IOSTANDARD LVCMOS18} [get_ports {psu_alert_i}]
      # ------------------------------------------------------------------------------
      # I2C EMIO
      set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports {emio_scl_b}]
      set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports {emio_sda_b}]
      # ------------------------------------------------------------------------------
      # I2C wr Flash
      set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18} [get_ports {wrflash_scl_b}]
      set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS18} [get_ports {wrflash_sda_b}]
      # ------------------------------------------------------------------------------
      # I2C Backplane
      set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN F15} [get_ports {bckpl_scl_b}]
      set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN G15} [get_ports {bckpl_sda_b}]
      # ------------------------------------------------------------------------------
      # SFP
      set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {tx_disable_o}]
      set_property PACKAGE_PIN AJ4 [get_ports sfp_rxp]
      set_property PACKAGE_PIN AJ3 [get_ports sfp_rxn]
      set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
      set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
      # ------------------------------------------------------------------------------
      # Backplain
      set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[0]}]
      set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[1]}]
      set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[2]}]
      set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[3]}]
      set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[4]}]
      set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[5]}]
      set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[6]}]
      set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[7]}]
      set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports {bckpl_rst_n_o}]
      gw/projects/diot_v2/src/constants.vhd 0 → 100644
      View file @ a292404f
      ----------------------------------------------------------------------------------
      -- Company:
      -- Engineer:
      --
      -- Create Date: 06/28/2021 04:30:23 PM
      -- Design Name:
      -- Module Name: constants - Behavioral
      -- Project Name:
      -- Target Devices:
      -- Tool Versions:
      -- Description:
      --
      -- Dependencies:
      --
      -- Revision:
      -- Revision 0.01 - File Created
      -- Additional Comments:
      --
      ----------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      --==============================================================================
      --! Entity declaration for constants
      --==============================================================================
      entity constants is
      generic (
      g_phyaddr : integer := 9;
      g_config_vector : integer := 0;
      g_config_valid : integer := 0;
      g_signal_detect : integer := 1
      );
      port (
      pl_clk_i : in std_logic;
      --! Vector indicating status. We need bits 0 and 1 of the vector
      status_vector : in std_logic_vector(15 downto 0);
      --! Management clock, (<= 2.5MHz)
      mdc_i : in std_logic;
      mdc_clk_led : out std_logic;
      --! Reset of the module, coming from PS
      pl_resetn_i : in std_logic;
      reset_o : out std_logic;
      --! Autoneg
      an_config_o : out std_logic;
      an_config_vec_o : out std_logic_vector(15 downto 0);
      tx_disable_o : out std_logic;
      --! EMIO GPIOs
      p_pres_i : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      psu_alert_i : in std_logic;
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t_o : out std_logic;
      ps_emio_o : out std_logic_vector(15 downto 0);
      ps_emio_i : in std_logic_vector(15 downto 0);
      ps_emio_t_i : in std_logic_vector(15 downto 0);
      --! I2C busses
      wrflash_i2c_irq_i : in std_logic;
      bckpl_i2c_irq_i : in std_logic;
      ps_irq_o : out std_logic_vector(1 downto 0);
      --! Constants module
      --! Addr of the PHY device(slave). A constant number
      phyaddr : out std_logic_vector(4 downto 0);
      configuration_vector : out std_logic_vector(4 downto 0);
      configuration_valid : out std_logic_vector(0 downto 0);
      --!'1' (if not connected to an optical module), otherwise, default is '0'
      signal_detect : out std_logic_vector(0 downto 0);
      --! Slices module
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end constants;
      --==============================================================================
      --! Architecture declaration
      --==============================================================================
      architecture Behavioral of constants is
      --! Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
      signal s_cnt : unsigned(11 downto 0);
      signal s_mdc_led_o : std_logic;
      type t_pwr_state is (IDLE, RST);
      signal pwr_state : t_pwr_state;
      signal ps_emio2_d0 : std_logic;
      signal ps_emio2_p : std_logic;
      --==============================================================================
      --! Architecture begin
      --==============================================================================
      begin
      an_config_o <= '0';
      an_config_vec_o <= x"D801";
      tx_disable_o <= '0';
      phyaddr <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr'length));
      configuration_vector <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector'length));
      configuration_valid <= std_logic_vector(to_unsigned(g_config_valid, configuration_valid'length));
      signal_detect <= std_logic_vector(to_unsigned(g_signal_detect, signal_detect'length));
      reset_o <= '1' when (pl_resetn_i = '0') else '0';
      link_status_led <= status_vector(0);
      link_sync_led <= status_vector(1);
      clk_src_sel_o <= "11";
      p_calc_mdc: process(mdc_i, pl_resetn_i)
      begin
      if (pl_resetn_i = '0') then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '0';
      elsif (rising_edge(mdc_i)) then
      if (s_cnt = 4096-2) then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '1';
      else
      s_mdc_led_o <= '0';
      s_cnt <= s_cnt + 1;
      end if;
      end if;
      end process p_calc_mdc;
      mdc_clk_led <= s_mdc_led_o;
      --! EMIO -> PL GPIO
      ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
      ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else '0';
      p_pwr: process(pl_clk_i)
      begin
      if rising_edge(pl_clk_i) then
      ps_emio2_d0 <= ps_emio_i(2);
      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
      pwr_state <= IDLE;
      pwr_cycle_req_o <= '0';
      else
      if pwr_state = IDLE then
      pwr_cycle_req_o <= '0';
      if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
      pwr_state <= RST;
      end if;
      elsif pwr_state = RST then
      pwr_cycle_req_o <= '1';
      end if;
      end if;
      end if;
      end process p_pwr;
      --! EMIO 83..90
      ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
      bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
      bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
      --! EMIO 91
      ps_emio_o(13) <= ps_emio_i(13);
      bckpl_rst_n_o <= ps_emio_i(13);
      --! EMIO 92
      ps_emio_o(14) <= psu_alert_i;
      --! EMIO 93
      ps_emio_o(15) <= f_rst_i;
      f_rst_o <= ps_emio_i(15);
      f_rst_t_o <= ps_emio_t_i(15);
      --! I2C irqs
      ps_irq_o(1 downto 0) <= bckpl_i2c_irq_i & wrflash_i2c_irq_i;
      end Behavioral;
      --==============================================================================
      -- architecture end
      --==============================================================================
      gw/projects/diot_v2/src/diot_v2_top.vhd 0 → 100644
      View file @ a292404f
      --==============================================================================
      --! @file diot_v2_top.vhd
      --==============================================================================
      --------------------------------------------------------------------------------
      -- --
      -- CERN - diot_v2 --
      -- --
      --------------------------------------------------------------------------------
      --
      -- unit name: dios_sb_top
      --
      --! @brief top level DIOT system board Version 2 based in ZynqMP+
      --
      --! @author alen.arias.vazquez@cern.ch
      --
      --! @date 01/04/2022
      --
      --------------------------------------------------------------------------------
      library ieee;
      library unisim;
      use ieee.std_logic_1164.all;
      use unisim.vcomponents.all;
      --==============================================================================
      --! Entity declaration for diot_v2_top
      --==============================================================================
      entity diot_v2_top is
      port (
      f_rst_b : inout std_logic;
      psu_alert_i : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0);
      gtrefclk_in_clk_p : in std_logic;
      gtrefclk_in_clk_n : in std_logic;
      pl_reset_led : out std_logic;
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      mdc_clk_led : out std_logic;
      tx_disable_o : out std_logic;
      sfp_rxp : in std_logic;
      sfp_rxn : in std_logic;
      sfp_txp : out std_logic;
      sfp_txn : out std_logic;
      bckpl_rst_n_o : out std_logic;
      bckpl_servmod_b : inout std_logic_vector(7 downto 0);
      bckpl_scl_b : inout std_logic;
      bckpl_sda_b : inout std_logic;
      emio_scl_b : inout std_logic;
      emio_sda_b : inout std_logic;
      wrflash_scl_b : inout std_logic;
      wrflash_sda_b : inout std_logic
      );
      end diot_v2_top;
      --==============================================================================
      --! Architecture declaration
      --==============================================================================
      architecture structure of diot_v2_top is
      component diot_v2 is
      port (
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t : out std_logic;
      psu_alert_i : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0);
      gtrefclk_in_clk_p : in std_logic;
      gtrefclk_in_clk_n : in std_logic;
      pl_reset_led : out std_logic;
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      mdc_clk_led : out std_logic;
      tx_disable_o : out std_logic;
      sfp_rxp : in std_logic;
      sfp_rxn : in std_logic;
      sfp_txp : out std_logic;
      sfp_txn : out std_logic;
      bckpl_rst_n_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t : out std_logic_vector(7 downto 0);
      i2c_bckpl_scl_i : in std_logic;
      i2c_bckpl_scl_o : out std_logic;
      i2c_bckpl_scl_t : out std_logic;
      i2c_bckpl_sda_i : in std_logic;
      i2c_bckpl_sda_o : out std_logic;
      i2c_bckpl_sda_t : out std_logic;
      i2c_emio_scl_i : in std_logic;
      i2c_emio_scl_o : out std_logic;
      i2c_emio_scl_t : out std_logic;
      i2c_emio_sda_i : in std_logic;
      i2c_emio_sda_o : out std_logic;
      i2c_emio_sda_t : out std_logic;
      i2c_wrflash_scl_i : in std_logic;
      i2c_wrflash_scl_o : out std_logic;
      i2c_wrflash_scl_t : out std_logic;
      i2c_wrflash_sda_i : in std_logic;
      i2c_wrflash_sda_o : out std_logic;
      i2c_wrflash_sda_t : out std_logic
      );
      end component diot_v2;
      --! Signals backplane servmod
      signal s_bckpl_servmod_o : std_logic_vector(7 downto 0);
      signal s_bckpl_servmod_i : std_logic_vector(7 downto 0);
      signal s_bckpl_servmod_t : std_logic_vector(7 downto 0);
      --! Signals F RST buffer
      signal s_f_rst_o : std_logic;
      signal s_f_rst_i : std_logic;
      signal s_f_rst_t : std_logic;
      --! Signals I2C WR FLASH
      signal s_wrflash_scl_i : std_logic;
      signal s_wrflash_scl_o : std_logic;
      signal s_wrflash_scl_t : std_logic;
      signal s_wrflash_sda_i : std_logic;
      signal s_wrflash_sda_o : std_logic;
      signal s_wrflash_sda_t : std_logic;
      --! Signals I2C Backplane
      signal s_bckpl_scl_i : std_logic;
      signal s_bckpl_scl_o : std_logic;
      signal s_bckpl_scl_t : std_logic;
      signal s_bckpl_sda_i : std_logic;
      signal s_bckpl_sda_o : std_logic;
      signal s_bckpl_sda_t : std_logic;
      --! Signals I2C EMIO
      signal s_emio_scl_i : std_logic;
      signal s_emio_scl_o : std_logic;
      signal s_emio_scl_t : std_logic;
      signal s_emio_sda_i : std_logic;
      signal s_emio_sda_o : std_logic;
      signal s_emio_sda_t : std_logic;
      --==============================================================================
      --! Architecture begin
      --==============================================================================
      begin
      ----------------------------------------------------------------------------
      --! I2C Write Flash
      i_buf_wr_flash_scl : IOBUF
      port map (
      I => s_wrflash_scl_o,
      O => s_wrflash_scl_i,
      T => s_wrflash_scl_t,
      IO => wrflash_scl_b
      );
      i_buf_wr_flash_sda : IOBUF
      port map (
      I => s_wrflash_sda_o,
      O => s_wrflash_sda_i,
      T => s_wrflash_sda_t,
      IO => wrflash_sda_b
      );
      ----------------------------------------------------------------------------
      --! I2C Backplane
      i_buf_bckpl_scl : IOBUF
      port map (
      I => s_bckpl_scl_o,
      O => s_bckpl_scl_i,
      T => s_bckpl_scl_t,
      IO => bckpl_scl_b
      );
      i_buf_bckpl_sda : IOBUF
      port map (
      I => s_bckpl_sda_o,
      O => s_bckpl_sda_i,
      T => s_bckpl_sda_t,
      IO => bckpl_sda_b
      );
      ----------------------------------------------------------------------------
      --! I2C EMIO -> PS I2C 1
      i_buf_emio_scl : IOBUF
      port map (
      I => s_emio_scl_o,
      O => s_emio_scl_i,
      T => s_emio_scl_t,
      IO => emio_scl_b
      );
      i_buf_emio_sda : IOBUF
      port map (
      I => s_emio_sda_o,
      O => s_emio_sda_i,
      T => s_emio_sda_t,
      IO => emio_sda_b
      );
      ----------------------------------------------------------------------------
      --! F RST
      i_buf_f_rst : IOBUF
      port map (
      I => s_f_rst_o,
      O => s_f_rst_i,
      T => s_f_rst_t,
      IO => f_rst_b
      );
      ----------------------------------------------------------------------------
      --! Backplane Servmod
      gen_buf_servmod: for x in 7 downto 0 generate
      i_buf_servmod : IOBUF
      port map (
      I => s_bckpl_servmod_o(x),
      O => s_bckpl_servmod_i(x),
      T => s_bckpl_servmod_t(x),
      IO => bckpl_servmod_b(x)
      );
      end generate gen_buf_servmod;
      ----------------------------------------------------------------------------
      --! Block Design instance
      diot_v2_i: component diot_v2
      port map (
      f_rst_i => s_f_rst_i,
      f_rst_o => s_f_rst_o,
      f_rst_t => s_f_rst_t,
      psu_alert_i => psu_alert_i,
      p_pres_i_0 => p_pres_i_0,
      pwr_cycle_req_o_0 => pwr_cycle_req_o_0,
      clk_src_sel_o => clk_src_sel_o,
      gtrefclk_in_clk_p => gtrefclk_in_clk_p,
      gtrefclk_in_clk_n => gtrefclk_in_clk_n,
      pl_reset_led => pl_reset_led,
      link_status_led => link_status_led,
      link_sync_led => link_sync_led,
      mdc_clk_led => mdc_clk_led,
      tx_disable_o => tx_disable_o,
      sfp_rxp => sfp_rxp,
      sfp_rxn => sfp_rxn,
      sfp_txp => sfp_txp,
      sfp_txn => sfp_txn,
      bckpl_rst_n_o => bckpl_rst_n_o,
      bckpl_servmod_i => s_bckpl_servmod_i,
      bckpl_servmod_o => s_bckpl_servmod_o,
      bckpl_servmod_t => s_bckpl_servmod_t,
      i2c_bckpl_scl_i => s_bckpl_scl_i,
      i2c_bckpl_scl_o => s_bckpl_scl_o,
      i2c_bckpl_scl_t => s_bckpl_scl_t,
      i2c_bckpl_sda_i => s_bckpl_sda_i,
      i2c_bckpl_sda_o => s_bckpl_sda_o,
      i2c_bckpl_sda_t => s_bckpl_sda_t,
      i2c_emio_scl_i => s_emio_scl_i,
      i2c_emio_scl_o => s_emio_scl_o,
      i2c_emio_scl_t => s_emio_scl_t,
      i2c_emio_sda_i => s_emio_sda_i,
      i2c_emio_sda_o => s_emio_sda_o,
      i2c_emio_sda_t => s_emio_sda_t,
      i2c_wrflash_scl_i => s_wrflash_scl_i,
      i2c_wrflash_scl_o => s_wrflash_scl_o,
      i2c_wrflash_scl_t => s_wrflash_scl_t,
      i2c_wrflash_sda_i => s_wrflash_sda_i,
      i2c_wrflash_sda_o => s_wrflash_sda_o,
      i2c_wrflash_sda_t => s_wrflash_sda_t
      );
      end architecture structure;
      --==============================================================================
      -- architecture end
      --==============================================================================
      gw/projects/diot_v2/tcl/create_bd.tcl 0 → 100644
      View file @ a292404f
      # Proc to create Block Design
      proc create_block_design { parentCell design_name target_path } {
      # Define design name
      set block_design_name $design_name
      write_msg "INFO: Creating block design $block_design_name" "1"
      create_bd_design $block_design_name
      # Get object for parentCell
      set parentObj [get_bd_cells $parentCell]
      # Save current instance; Restore later
      set oldCurInst [current_bd_instance .]
      # Set parent object as current
      current_bd_instance $parentObj
      # ################################
      # Interfaces
      # MGT Clock Interface
      set gtrefclk_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gtrefclk_in ]
      set_property -dict [ list \
      CONFIG.FREQ_HZ {100000000} \
      ] $gtrefclk_in
      # SFP Interface
      set sfp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 sfp ]
      # I2C Interfaces
      set i2c_wrflash [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_wrflash ]
      set i2c_bckpl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_bckpl ]
      set i2c_emio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_emio ]
      # ################################
      # Ports
      # MoniMOD
      set f_rst_i [ create_bd_port -dir I f_rst_i ]
      set f_rst_o [ create_bd_port -dir O f_rst_o ]
      set f_rst_t [ create_bd_port -dir O f_rst_t ]
      set p_pres_i_0 [ create_bd_port -dir I -from 1 -to 0 p_pres_i_0 ]
      # PSU alert
      set psu_alert_i [ create_bd_port -dir I psu_alert_i ]
      # Power cycle request
      set pwr_cycle_req_o_0 [ create_bd_port -dir O pwr_cycle_req_o_0 ]
      # Clock selector
      set clk_src_sel_o [ create_bd_port -dir O -from 1 -to 0 clk_src_sel_o ]
      # Leds
      set pl_reset_led [ create_bd_port -dir O -type rst pl_reset_led ]
      set link_status_led [ create_bd_port -dir O link_status_led ]
      set link_sync_led [ create_bd_port -dir O link_sync_led ]
      set mdc_clk_led [ create_bd_port -dir O mdc_clk_led ]
      # Create ports backplane
      set bckpl_rst_n_o [ create_bd_port -dir O bckpl_rst_n_o ]
      set bckpl_servmod_i [ create_bd_port -dir I -from 7 -to 0 bckpl_servmod_i ]
      set bckpl_servmod_o [ create_bd_port -dir O -from 7 -to 0 bckpl_servmod_o ]
      set bckpl_servmod_t [ create_bd_port -dir O -from 7 -to 0 bckpl_servmod_t ]
      # SFP tx disable
      set tx_disable_o [ create_bd_port -dir O tx_disable_o ]
      # Create instance: axi_iic_0, and set properties
      set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic axi_iic_0 ]
      set_property -dict [ list \
      CONFIG.C_SCL_INERTIAL_DELAY {5} \
      CONFIG.C_SDA_INERTIAL_DELAY {5} \
      ] $axi_iic_0
      # Create instance: axi_iic_1, and set properties
      set axi_iic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic axi_iic_1 ]
      set_property -dict [ list \
      CONFIG.C_SCL_INERTIAL_DELAY {5} \
      CONFIG.C_SDA_INERTIAL_DELAY {5} \
      CONFIG.IIC_FREQ_KHZ {100} \
      ] $axi_iic_1
      # Create instance: constants_and_slices, and set properties
      set constants_and_slices [ create_bd_cell -type module -reference constants constants_and_slices ]
      set_property -dict [ list \
      CONFIG.POLARITY {ACTIVE_HIGH} \
      ] [ get_bd_pins /constants_and_slices/reset_o ]
      # Create instance: gig_ethernet_pcs_pma_0, and set properties
      set gig_ethernet_pcs_pma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:gig_ethernet_pcs_pma gig_ethernet_pcs_pma_0 ]
      set_property -dict [ list \
      CONFIG.Auto_Negotiation {true} \
      CONFIG.EMAC_IF_TEMAC {GEM} \
      CONFIG.Ext_Management_Interface {false} \
      CONFIG.GT_Location {X0Y3} \
      CONFIG.GTinEx {false} \
      CONFIG.LvdsRefClk {125} \
      CONFIG.Physical_Interface {Transceiver} \
      CONFIG.RefClkRate {125} \
      CONFIG.Standard {1000BASEX} \
      CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
      CONFIG.TransceiverControl {false} \
      ] $gig_ethernet_pcs_pma_0
      # RST PS CLK0
      set RST_PS_CLK0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset RST_PS_CLK0 ]
      # Create instance: lpd_axi_interconnect, and set properties
      set lpd_axi_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect lpd_axi_interconnect ]
      set_property -dict [ list \
      CONFIG.NUM_MI {3} \
      ] $lpd_axi_interconnect
      source $target_path/tcl/ps_cfg.tcl
      # FPGA DEVICE
      set fpga_dev [ create_bd_cell -type module -reference fpga_device fpga_dev ]
      # Create interface connections
      connect_bd_intf_net [get_bd_intf_pins gig_ethernet_pcs_pma_0/gtrefclk_in] [get_bd_intf_ports gtrefclk_in]
      connect_bd_intf_net [get_bd_intf_pins gig_ethernet_pcs_pma_0/sfp] [get_bd_intf_ports sfp]
      connect_bd_intf_net [get_bd_intf_pins gig_ethernet_pcs_pma_0/gmii_gem_pcs_pma] [get_bd_intf_pins zynqmp_ps/GMII_ENET0]
      connect_bd_intf_net [get_bd_intf_pins gig_ethernet_pcs_pma_0/mdio_pcs_pma] [get_bd_intf_pins zynqmp_ps/MDIO_ENET0]
      # Connect LPD interconnect
      connect_bd_intf_net [get_bd_intf_pins lpd_axi_interconnect/S00_AXI] [get_bd_intf_pins zynqmp_ps/M_AXI_HPM0_LPD]
      connect_bd_intf_net [get_bd_intf_pins lpd_axi_interconnect/M00_AXI] [get_bd_intf_pins fpga_dev/S_AXI]
      connect_bd_intf_net [get_bd_intf_pins lpd_axi_interconnect/M01_AXI] [get_bd_intf_pins axi_iic_0/S_AXI]
      connect_bd_intf_net [get_bd_intf_pins lpd_axi_interconnect/M02_AXI] [get_bd_intf_pins axi_iic_1/S_AXI]
      # I2C Interfaces
      connect_bd_intf_net [get_bd_intf_pins axi_iic_0/IIC] [get_bd_intf_ports i2c_wrflash]
      connect_bd_intf_net [get_bd_intf_pins axi_iic_1/IIC] [get_bd_intf_ports i2c_bckpl]
      connect_bd_intf_net [get_bd_intf_pins zynqmp_ps/IIC_1] [get_bd_intf_ports i2c_emio]
      # PL RST CLK 0
      connect_bd_net -net pl_resetn0 [get_bd_ports pl_reset_led] [get_bd_pins constants_and_slices/pl_resetn_i] [get_bd_pins RST_PS_CLK0/ext_reset_in] \
      [get_bd_pins zynqmp_ps/pl_resetn0]
      connect_bd_net [get_bd_pins RST_PS_CLK0/interconnect_aresetn] [get_bd_pins lpd_axi_interconnect/ARESETN]
      connect_bd_net -net RST_PS_CLK0_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_iic_1/s_axi_aresetn] \
      [get_bd_pins lpd_axi_interconnect/M00_ARESETN] [get_bd_pins lpd_axi_interconnect/M01_ARESETN] [get_bd_pins lpd_axi_interconnect/M02_ARESETN] \
      [get_bd_pins lpd_axi_interconnect/S00_ARESETN] [get_bd_pins RST_PS_CLK0/peripheral_aresetn] [get_bd_pins fpga_dev/S_AXI_ARESETN]
      # PL CLK 0 DOMAIN
      connect_bd_net -net pl_clk0 [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_iic_1/s_axi_aclk] [get_bd_pins constants_and_slices/pl_clk_i] \
      [get_bd_pins gig_ethernet_pcs_pma_0/independent_clock_bufg] [get_bd_pins lpd_axi_interconnect/ACLK] [get_bd_pins lpd_axi_interconnect/M00_ACLK] \
      [get_bd_pins lpd_axi_interconnect/M01_ACLK] [get_bd_pins lpd_axi_interconnect/M02_ACLK] [get_bd_pins lpd_axi_interconnect/S00_ACLK] \
      [get_bd_pins RST_PS_CLK0/slowest_sync_clk] [get_bd_pins zynqmp_ps/maxihpm0_lpd_aclk] [get_bd_pins zynqmp_ps/pl_clk0] [get_bd_pins fpga_dev/S_AXI_ACLK]
      # Constants and Slices connections
      connect_bd_net [get_bd_pins constants_and_slices/wrflash_i2c_irq_i] [get_bd_pins axi_iic_0/iic2intc_irpt]
      connect_bd_net [get_bd_pins constants_and_slices/bckpl_i2c_irq_i] [get_bd_pins axi_iic_1/iic2intc_irpt]
      connect_bd_net [get_bd_pins constants_and_slices/configuration_valid] [get_bd_pins gig_ethernet_pcs_pma_0/configuration_valid]
      connect_bd_net [get_bd_pins constants_and_slices/configuration_vector] [get_bd_pins gig_ethernet_pcs_pma_0/configuration_vector]
      connect_bd_net [get_bd_pins constants_and_slices/link_status_led] [get_bd_ports link_status_led]
      connect_bd_net [get_bd_pins constants_and_slices/link_sync_led] [get_bd_ports link_sync_led]
      connect_bd_net [get_bd_pins constants_and_slices/mdc_clk_led] [get_bd_ports mdc_clk_led]
      connect_bd_net [get_bd_pins constants_and_slices/phyaddr] [get_bd_pins gig_ethernet_pcs_pma_0/phyaddr]
      connect_bd_net [get_bd_pins constants_and_slices/signal_detect] [get_bd_pins gig_ethernet_pcs_pma_0/signal_detect]
      connect_bd_net [get_bd_pins constants_and_slices/an_config_o] [get_bd_pins gig_ethernet_pcs_pma_0/an_adv_config_val] [get_bd_pins gig_ethernet_pcs_pma_0/an_restart_config]
      connect_bd_net [get_bd_pins constants_and_slices/an_config_vec_o] [get_bd_pins gig_ethernet_pcs_pma_0/an_adv_config_vector]
      connect_bd_net [get_bd_pins constants_and_slices/bckpl_rst_n_o] [get_bd_ports bckpl_rst_n_o]
      connect_bd_net [get_bd_pins constants_and_slices/clk_src_sel_o] [get_bd_ports clk_src_sel_o]
      connect_bd_net [get_bd_pins constants_and_slices/ps_emio_o] [get_bd_pins zynqmp_ps/emio_gpio_i]
      connect_bd_net [get_bd_pins constants_and_slices/ps_irq_o] [get_bd_pins zynqmp_ps/pl_ps_irq0]
      connect_bd_net [get_bd_pins constants_and_slices/pwr_cycle_req_o] [get_bd_ports pwr_cycle_req_o_0]
      connect_bd_net [get_bd_pins constants_and_slices/reset_o] [get_bd_pins gig_ethernet_pcs_pma_0/reset]
      connect_bd_net [get_bd_pins constants_and_slices/tx_disable_o] [get_bd_ports tx_disable_o]
      connect_bd_net [get_bd_pins constants_and_slices/status_vector] [get_bd_pins gig_ethernet_pcs_pma_0/status_vector]
      connect_bd_net [get_bd_pins constants_and_slices/p_pres_i] [get_bd_ports p_pres_i_0]
      connect_bd_net [get_bd_pins constants_and_slices/psu_alert_i] [get_bd_ports psu_alert_i]
      connect_bd_net [get_bd_pins constants_and_slices/mdc_i] [get_bd_pins gig_ethernet_pcs_pma_0/mdc] [get_bd_pins zynqmp_ps/emio_enet0_mdio_mdc]
      connect_bd_net [get_bd_pins constants_and_slices/ps_emio_i] [get_bd_pins zynqmp_ps/emio_gpio_o]
      connect_bd_net [get_bd_pins constants_and_slices/ps_emio_t_i] [get_bd_pins zynqmp_ps/emio_gpio_t]
      connect_bd_net [get_bd_pins constants_and_slices/f_rst_i] [get_bd_ports f_rst_i]
      connect_bd_net [get_bd_pins constants_and_slices/f_rst_o] [get_bd_ports f_rst_o]
      connect_bd_net [get_bd_pins constants_and_slices/f_rst_t_o] [get_bd_ports f_rst_t]
      connect_bd_net [get_bd_pins constants_and_slices/bckpl_servmod_i] [get_bd_ports bckpl_servmod_i]
      connect_bd_net [get_bd_pins constants_and_slices/bckpl_servmod_o] [get_bd_ports bckpl_servmod_o]
      connect_bd_net [get_bd_pins constants_and_slices/bckpl_servmod_t_o] [get_bd_ports bckpl_servmod_t]
      # Create address segments
      assign_bd_address -offset 0x80000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynqmp_ps/Data] [get_bd_addr_segs fpga_dev/S_AXI/reg0] -force
      assign_bd_address -offset 0x80001000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynqmp_ps/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] -force
      assign_bd_address -offset 0x80002000 -range 0x00001000 -target_address_space [get_bd_addr_spaces zynqmp_ps/Data] [get_bd_addr_segs axi_iic_1/S_AXI/Reg] -force
      # Restore current instance
      current_bd_instance $oldCurInst
      validate_bd_design
      save_bd_design
      close_bd_design $block_design_name
      }
      gw/projects/diot_v2/tcl/project_cfg.tcl 0 → 100644
      View file @ a292404f
      # Custom project settings
      set reference_part "xczu7cg-ffvf1517-1-e"
      set project_name "diot_v2"
      set entity_top "diot_v2_top"
      # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
      set max_threads 8
      set project_language "VHDL"
      set lib_default xil_defaultlib
      # Common IP directory
      set COMMON_IP ../../../common-ip
      # Add properties
      set_user_property "default_lib" "xil_defaultlib"
      set_user_property "enable_vhdl_2008" "1"
      set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
      # Top Level
      add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
      # Vhdl Src
      add_vhdl_src ${lib_default} ../src/constants.vhd
      # Add Constraints
      add_constraint diot_v2.xdc
      gw/projects/diot_v2/tcl/ps_cfg.tcl 0 → 100644
      View file @ a292404f
      # Create instance: zynqmp_ps, and set properties
      write_msg "INFO: Adding ZynqMP PS Configuration" "1"
      set zynqmp_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynqmp_ps ]
      set_property -dict [ list \
      CONFIG.CAN0_BOARD_INTERFACE {custom} \
      CONFIG.CAN1_BOARD_INTERFACE {custom} \
      CONFIG.CSU_BOARD_INTERFACE {custom} \
      CONFIG.DP_BOARD_INTERFACE {custom} \
      CONFIG.GEM0_BOARD_INTERFACE {custom} \
      CONFIG.GEM1_BOARD_INTERFACE {custom} \
      CONFIG.GEM2_BOARD_INTERFACE {custom} \
      CONFIG.GEM3_BOARD_INTERFACE {custom} \
      CONFIG.GPIO_BOARD_INTERFACE {custom} \
      CONFIG.IIC0_BOARD_INTERFACE {custom} \
      CONFIG.IIC1_BOARD_INTERFACE {custom} \
      CONFIG.NAND_BOARD_INTERFACE {custom} \
      CONFIG.PCIE_BOARD_INTERFACE {custom} \
      CONFIG.PJTAG_BOARD_INTERFACE {custom} \
      CONFIG.PMU_BOARD_INTERFACE {custom} \
      CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
      CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS33} \
      CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
      CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
      CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
      CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
      CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
      CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
      CONFIG.PSU_IMPORT_BOARD_PRESET {} \
      CONFIG.PSU_MIO_0_DIRECTION {out} \
      CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_0_POLARITY {Default} \
      CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_0_SLEW {fast} \
      CONFIG.PSU_MIO_10_DIRECTION {inout} \
      CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_10_POLARITY {Default} \
      CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_10_SLEW {fast} \
      CONFIG.PSU_MIO_11_DIRECTION {inout} \
      CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_11_POLARITY {Default} \
      CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_11_SLEW {fast} \
      CONFIG.PSU_MIO_12_DIRECTION {out} \
      CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_12_POLARITY {Default} \
      CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_12_SLEW {fast} \
      CONFIG.PSU_MIO_13_DIRECTION {inout} \
      CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_13_POLARITY {Default} \
      CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_13_SLEW {fast} \
      CONFIG.PSU_MIO_14_DIRECTION {inout} \
      CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_14_POLARITY {Default} \
      CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_14_SLEW {fast} \
      CONFIG.PSU_MIO_15_DIRECTION {inout} \
      CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_15_POLARITY {Default} \
      CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_15_SLEW {fast} \
      CONFIG.PSU_MIO_16_DIRECTION {inout} \
      CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_16_POLARITY {Default} \
      CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_16_SLEW {fast} \
      CONFIG.PSU_MIO_17_DIRECTION {inout} \
      CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_17_POLARITY {Default} \
      CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_17_SLEW {fast} \
      CONFIG.PSU_MIO_18_DIRECTION {inout} \
      CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_18_POLARITY {Default} \
      CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_18_SLEW {fast} \
      CONFIG.PSU_MIO_19_DIRECTION {inout} \
      CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_19_POLARITY {Default} \
      CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_19_SLEW {fast} \
      CONFIG.PSU_MIO_1_DIRECTION {inout} \
      CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_1_POLARITY {Default} \
      CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_1_SLEW {fast} \
      CONFIG.PSU_MIO_20_DIRECTION {inout} \
      CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_20_POLARITY {Default} \
      CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_20_SLEW {fast} \
      CONFIG.PSU_MIO_21_DIRECTION {inout} \
      CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_21_POLARITY {Default} \
      CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_21_SLEW {fast} \
      CONFIG.PSU_MIO_22_DIRECTION {out} \
      CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_22_POLARITY {Default} \
      CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_22_SLEW {fast} \
      CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_23_POLARITY {Default} \
      CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_23_SLEW {fast} \
      CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_24_POLARITY {Default} \
      CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_24_SLEW {fast} \
      CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_25_POLARITY {Default} \
      CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_25_SLEW {fast} \
      CONFIG.PSU_MIO_26_DIRECTION {inout} \
      CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_26_POLARITY {Default} \
      CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_26_SLEW {fast} \
      CONFIG.PSU_MIO_27_DIRECTION {inout} \
      CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_27_POLARITY {Default} \
      CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_27_SLEW {fast} \
      CONFIG.PSU_MIO_28_DIRECTION {inout} \
      CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_28_POLARITY {Default} \
      CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_28_SLEW {fast} \
      CONFIG.PSU_MIO_29_DIRECTION {inout} \
      CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_29_POLARITY {Default} \
      CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_29_SLEW {fast} \
      CONFIG.PSU_MIO_2_DIRECTION {inout} \
      CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_2_POLARITY {Default} \
      CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_2_SLEW {fast} \
      CONFIG.PSU_MIO_30_DIRECTION {inout} \
      CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_30_POLARITY {Default} \
      CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_30_SLEW {fast} \
      CONFIG.PSU_MIO_31_DIRECTION {inout} \
      CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_31_POLARITY {Default} \
      CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_31_SLEW {fast} \
      CONFIG.PSU_MIO_32_DIRECTION {inout} \
      CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_32_POLARITY {Default} \
      CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_32_SLEW {fast} \
      CONFIG.PSU_MIO_33_DIRECTION {inout} \
      CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_33_POLARITY {Default} \
      CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_33_SLEW {fast} \
      CONFIG.PSU_MIO_34_DIRECTION {inout} \
      CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_34_POLARITY {Default} \
      CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_34_SLEW {fast} \
      CONFIG.PSU_MIO_35_DIRECTION {inout} \
      CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_35_POLARITY {Default} \
      CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_35_SLEW {fast} \
      CONFIG.PSU_MIO_36_DIRECTION {inout} \
      CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_36_POLARITY {Default} \
      CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_36_SLEW {fast} \
      CONFIG.PSU_MIO_37_DIRECTION {inout} \
      CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_37_POLARITY {Default} \
      CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_37_SLEW {fast} \
      CONFIG.PSU_MIO_38_DIRECTION {inout} \
      CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_38_POLARITY {Default} \
      CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_38_SLEW {fast} \
      CONFIG.PSU_MIO_39_DIRECTION {inout} \
      CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_39_POLARITY {Default} \
      CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_39_SLEW {fast} \
      CONFIG.PSU_MIO_3_DIRECTION {inout} \
      CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_3_POLARITY {Default} \
      CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_3_SLEW {fast} \
      CONFIG.PSU_MIO_40_DIRECTION {inout} \
      CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_40_POLARITY {Default} \
      CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_40_SLEW {fast} \
      CONFIG.PSU_MIO_41_DIRECTION {inout} \
      CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_41_POLARITY {Default} \
      CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_41_SLEW {fast} \
      CONFIG.PSU_MIO_42_DIRECTION {inout} \
      CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_42_POLARITY {Default} \
      CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_42_SLEW {fast} \
      CONFIG.PSU_MIO_43_DIRECTION {inout} \
      CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_43_POLARITY {Default} \
      CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_43_SLEW {fast} \
      CONFIG.PSU_MIO_44_DIRECTION {inout} \
      CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_44_POLARITY {Default} \
      CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_44_SLEW {fast} \
      CONFIG.PSU_MIO_45_DIRECTION {inout} \
      CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_45_POLARITY {Default} \
      CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_45_SLEW {fast} \
      CONFIG.PSU_MIO_46_DIRECTION {inout} \
      CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_46_POLARITY {Default} \
      CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_46_SLEW {fast} \
      CONFIG.PSU_MIO_47_DIRECTION {inout} \
      CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_47_POLARITY {Default} \
      CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_47_SLEW {fast} \
      CONFIG.PSU_MIO_48_DIRECTION {inout} \
      CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_48_POLARITY {Default} \
      CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_48_SLEW {fast} \
      CONFIG.PSU_MIO_49_DIRECTION {inout} \
      CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_49_POLARITY {Default} \
      CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_49_SLEW {fast} \
      CONFIG.PSU_MIO_4_DIRECTION {inout} \
      CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_4_POLARITY {Default} \
      CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_4_SLEW {fast} \
      CONFIG.PSU_MIO_50_DIRECTION {inout} \
      CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_50_POLARITY {Default} \
      CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_50_SLEW {fast} \
      CONFIG.PSU_MIO_51_DIRECTION {out} \
      CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_51_POLARITY {Default} \
      CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_51_SLEW {fast} \
      CONFIG.PSU_MIO_52_DIRECTION {inout} \
      CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_52_POLARITY {Default} \
      CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_52_SLEW {fast} \
      CONFIG.PSU_MIO_53_DIRECTION {inout} \
      CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_53_POLARITY {Default} \
      CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_53_SLEW {fast} \
      CONFIG.PSU_MIO_54_DIRECTION {in} \
      CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_54_POLARITY {Default} \
      CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_54_SLEW {fast} \
      CONFIG.PSU_MIO_55_DIRECTION {out} \
      CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_55_POLARITY {Default} \
      CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_55_SLEW {fast} \
      CONFIG.PSU_MIO_56_DIRECTION {inout} \
      CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_56_POLARITY {Default} \
      CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_56_SLEW {fast} \
      CONFIG.PSU_MIO_57_DIRECTION {inout} \
      CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_57_POLARITY {Default} \
      CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_57_SLEW {fast} \
      CONFIG.PSU_MIO_58_DIRECTION {inout} \
      CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_58_POLARITY {Default} \
      CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_58_SLEW {fast} \
      CONFIG.PSU_MIO_59_DIRECTION {inout} \
      CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_59_POLARITY {Default} \
      CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_59_SLEW {fast} \
      CONFIG.PSU_MIO_5_DIRECTION {out} \
      CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_5_POLARITY {Default} \
      CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_5_SLEW {fast} \
      CONFIG.PSU_MIO_60_DIRECTION {inout} \
      CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_60_POLARITY {Default} \
      CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_60_SLEW {fast} \
      CONFIG.PSU_MIO_61_DIRECTION {inout} \
      CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_61_POLARITY {Default} \
      CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_61_SLEW {fast} \
      CONFIG.PSU_MIO_62_DIRECTION {inout} \
      CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_62_POLARITY {Default} \
      CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_62_SLEW {fast} \
      CONFIG.PSU_MIO_63_DIRECTION {inout} \
      CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_63_POLARITY {Default} \
      CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_63_SLEW {fast} \
      CONFIG.PSU_MIO_64_DIRECTION {inout} \
      CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_64_POLARITY {Default} \
      CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_64_SLEW {fast} \
      CONFIG.PSU_MIO_65_DIRECTION {inout} \
      CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_65_POLARITY {Default} \
      CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_65_SLEW {fast} \
      CONFIG.PSU_MIO_66_DIRECTION {inout} \
      CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_66_POLARITY {Default} \
      CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_66_SLEW {fast} \
      CONFIG.PSU_MIO_67_DIRECTION {inout} \
      CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_67_POLARITY {Default} \
      CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_67_SLEW {fast} \
      CONFIG.PSU_MIO_68_DIRECTION {inout} \
      CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_68_POLARITY {Default} \
      CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_68_SLEW {fast} \
      CONFIG.PSU_MIO_69_DIRECTION {inout} \
      CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_69_POLARITY {Default} \
      CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_69_SLEW {fast} \
      CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_6_POLARITY {Default} \
      CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_6_SLEW {fast} \
      CONFIG.PSU_MIO_70_DIRECTION {inout} \
      CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_70_POLARITY {Default} \
      CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_70_SLEW {fast} \
      CONFIG.PSU_MIO_71_DIRECTION {inout} \
      CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_71_POLARITY {Default} \
      CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_71_SLEW {fast} \
      CONFIG.PSU_MIO_72_DIRECTION {inout} \
      CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_72_POLARITY {Default} \
      CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_72_SLEW {fast} \
      CONFIG.PSU_MIO_73_DIRECTION {inout} \
      CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_73_POLARITY {Default} \
      CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_73_SLEW {fast} \
      CONFIG.PSU_MIO_74_DIRECTION {inout} \
      CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_74_POLARITY {Default} \
      CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_74_SLEW {fast} \
      CONFIG.PSU_MIO_75_DIRECTION {inout} \
      CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_75_POLARITY {Default} \
      CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_75_SLEW {fast} \
      CONFIG.PSU_MIO_76_DIRECTION {inout} \
      CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_76_POLARITY {Default} \
      CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_76_SLEW {fast} \
      CONFIG.PSU_MIO_77_DIRECTION {inout} \
      CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_77_POLARITY {Default} \
      CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_77_SLEW {fast} \
      CONFIG.PSU_MIO_7_DIRECTION {out} \
      CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_7_POLARITY {Default} \
      CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_7_SLEW {fast} \
      CONFIG.PSU_MIO_8_DIRECTION {inout} \
      CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_8_POLARITY {Default} \
      CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_8_SLEW {fast} \
      CONFIG.PSU_MIO_9_DIRECTION {inout} \
      CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
      CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
      CONFIG.PSU_MIO_9_POLARITY {Default} \
      CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
      CONFIG.PSU_MIO_9_SLEW {fast} \
      CONFIG.PSU_MIO_TREE_PERIPHERALS {\
      Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
      SPI Flash##Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI\
      Flash#Quad SPI Flash#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0####I2C\
      0#I2C 0#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1\
      MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1\
      MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#GPIO2 MIO#GPIO2\
      MIO#UART 0#UART 0#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2\
      MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2\
      MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2 MIO#GPIO2\
      MIO} \
      CONFIG.PSU_MIO_TREE_SIGNALS {\
      sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out##n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out####scl_out#sda_out#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpio1[32]#gpio1[33]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#gpio1[43]#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#gpio2[52]#gpio2[53]#rxd#txd#gpio2[56]#gpio2[57]#gpio2[58]#gpio2[59]#gpio2[60]#gpio2[61]#gpio2[62]#gpio2[63]#gpio2[64]#gpio2[65]#gpio2[66]#gpio2[67]#gpio2[68]#gpio2[69]#gpio2[70]#gpio2[71]#gpio2[72]#gpio2[73]#gpio2[74]#gpio2[75]#gpio2[76]#gpio2[77]} \
      CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
      CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
      CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
      CONFIG.PSU_SMC_CYCLE_T0 {NA} \
      CONFIG.PSU_SMC_CYCLE_T1 {NA} \
      CONFIG.PSU_SMC_CYCLE_T2 {NA} \
      CONFIG.PSU_SMC_CYCLE_T3 {NA} \
      CONFIG.PSU_SMC_CYCLE_T4 {NA} \
      CONFIG.PSU_SMC_CYCLE_T5 {NA} \
      CONFIG.PSU_SMC_CYCLE_T6 {NA} \
      CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {0} \
      CONFIG.PSU_VALUE_SILVERSION {3} \
      CONFIG.PSU__ACPU0__POWER__ON {1} \
      CONFIG.PSU__ACPU1__POWER__ON {1} \
      CONFIG.PSU__ACPU2__POWER__ON {0} \
      CONFIG.PSU__ACPU3__POWER__ON {0} \
      CONFIG.PSU__ACTUAL__IP {1} \
      CONFIG.PSU__ACT_DDR_FREQ_MHZ {1200.000000} \
      CONFIG.PSU__AFI0_COHERENCY {0} \
      CONFIG.PSU__AFI1_COHERENCY {0} \
      CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
      CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
      CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
      CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
      CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
      CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
      CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
      CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
      CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
      CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
      CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
      CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
      CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
      CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
      CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
      CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
      CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {48} \
      CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
      CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
      CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
      CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
      CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {600.000000} \
      CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \
      CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
      CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
      CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {48} \
      CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
      CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25} \
      CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \
      CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
      CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \
      CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
      CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.923077} \
      CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \
      CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
      CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {VPLL} \
      CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
      CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
      CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \
      CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \
      CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
      CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
      CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
      CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
      CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
      CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.333} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {42} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
      CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
      CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
      CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
      CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
      CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
      CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \
      CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
      CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
      CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
      CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
      CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
      CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125.000000} \
      CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
      CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {60} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {266.666656} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
      CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
      CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
      CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
      CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
      CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
      CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
      CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {16} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {50} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300.000000} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {32} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200.000000} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {16} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {50} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
      CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
      CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
      CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
      CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
      CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
      CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \
      CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
      CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250} \
      CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
      CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
      CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20} \
      CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
      CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
      CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__USB3__ENABLE {0} \
      CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
      CONFIG.PSU__CSU_COHERENCY {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
      CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
      CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
      CONFIG.PSU__DDRC__AL {0} \
      CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
      CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
      CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
      CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
      CONFIG.PSU__DDRC__CL {17} \
      CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
      CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
      CONFIG.PSU__DDRC__COMPONENTS {Components} \
      CONFIG.PSU__DDRC__CWL {12} \
      CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
      CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
      CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {1} \
      CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
      CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
      CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
      CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
      CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
      CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
      CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \
      CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
      CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
      CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
      CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
      CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
      CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
      CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
      CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
      CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
      CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
      CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
      CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
      CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
      CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
      CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
      CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
      CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
      CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
      CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
      CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
      CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
      CONFIG.PSU__DDRC__ECC {Enabled} \
      CONFIG.PSU__DDRC__ECC_SCRUB {0} \
      CONFIG.PSU__DDRC__ENABLE {1} \
      CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
      CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
      CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {ERR: 1 | 0} \
      CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
      CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
      CONFIG.PSU__DDRC__FGRM {1X} \
      CONFIG.PSU__DDRC__FREQ_MHZ {1} \
      CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
      CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
      CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
      CONFIG.PSU__DDRC__LP_ASR {manual normal} \
      CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
      CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
      CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
      CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
      CONFIG.PSU__DDRC__PLL_BYPASS {0} \
      CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
      CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
      CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
      CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
      CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
      CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
      CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400P} \
      CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
      CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
      CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
      CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
      CONFIG.PSU__DDRC__T_FAW {30.0} \
      CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \
      CONFIG.PSU__DDRC__T_RC {46.16} \
      CONFIG.PSU__DDRC__T_RCD {17} \
      CONFIG.PSU__DDRC__T_RP {17} \
      CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
      CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
      CONFIG.PSU__DDRC__VREF {1} \
      CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
      CONFIG.PSU__DDR_QOS_ENABLE {0} \
      CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \
      CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \
      CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \
      CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \
      CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \
      CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \
      CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \
      CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \
      CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
      CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
      CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
      CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
      CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
      CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
      CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
      CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
      CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
      CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
      CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
      CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
      CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \
      CONFIG.PSU__DEVICE_TYPE {CG} \
      CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {0} \
      CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \
      CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__DLL__ISUSED {1} \
      CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
      CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
      CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {1} \
      CONFIG.PSU__ENET0__GRP_MDIO__IO {EMIO} \
      CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__ENET0__PERIPHERAL__IO {EMIO} \
      CONFIG.PSU__ENET0__PTP__ENABLE {0} \
      CONFIG.PSU__ENET0__TSU__ENABLE {1} \
      CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
      CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
      CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__ENET1__PTP__ENABLE {0} \
      CONFIG.PSU__ENET1__TSU__ENABLE {0} \
      CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
      CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
      CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__ENET2__PTP__ENABLE {0} \
      CONFIG.PSU__ENET2__TSU__ENABLE {0} \
      CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
      CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
      CONFIG.PSU__ENET3__GRP_MDIO__IO {<Select>} \
      CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__ENET3__PERIPHERAL__IO {<Select>} \
      CONFIG.PSU__ENET3__PTP__ENABLE {0} \
      CONFIG.PSU__ENET3__TSU__ENABLE {0} \
      CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
      CONFIG.PSU__EN_EMIO_TRACE {0} \
      CONFIG.PSU__EP__IP {0} \
      CONFIG.PSU__EXPAND__CORESIGHT {0} \
      CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
      CONFIG.PSU__EXPAND__GIC {0} \
      CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
      CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
      CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
      CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100} \
      CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100} \
      CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
      CONFIG.PSU__FPGA_PL0_ENABLE {1} \
      CONFIG.PSU__FPGA_PL1_ENABLE {0} \
      CONFIG.PSU__FPGA_PL2_ENABLE {0} \
      CONFIG.PSU__FPGA_PL3_ENABLE {0} \
      CONFIG.PSU__FP__POWER__ON {1} \
      CONFIG.PSU__FTM__CTI_IN_0 {0} \
      CONFIG.PSU__FTM__CTI_IN_1 {0} \
      CONFIG.PSU__FTM__CTI_IN_2 {0} \
      CONFIG.PSU__FTM__CTI_IN_3 {0} \
      CONFIG.PSU__FTM__CTI_OUT_0 {0} \
      CONFIG.PSU__FTM__CTI_OUT_1 {0} \
      CONFIG.PSU__FTM__CTI_OUT_2 {0} \
      CONFIG.PSU__FTM__CTI_OUT_3 {0} \
      CONFIG.PSU__FTM__GPI {0} \
      CONFIG.PSU__FTM__GPO {0} \
      CONFIG.PSU__GEM0_COHERENCY {0} \
      CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__GEM1_COHERENCY {0} \
      CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__GEM2_COHERENCY {0} \
      CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__GEM3_COHERENCY {0} \
      CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__GEM__TSU__ENABLE {0} \
      CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
      CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
      CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
      CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
      CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
      CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
      CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
      CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
      CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
      CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
      CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
      CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
      CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
      CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__GPIO_EMIO_WIDTH {95} \
      CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {16} \
      CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
      CONFIG.PSU__GPU_PP0__POWER__ON {0} \
      CONFIG.PSU__GPU_PP1__POWER__ON {0} \
      CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
      CONFIG.PSU__GT__PRE_EMPH_LVL_4 {} \
      CONFIG.PSU__GT__VLT_SWNG_LVL_4 {} \
      CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \
      CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
      CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
      CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
      CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
      CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
      CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
      CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
      CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
      CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 26 .. 27} \
      CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
      CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__I2C1__PERIPHERAL__IO {EMIO} \
      CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
      CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
      CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
      CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
      CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
      CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100} \
      CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100} \
      CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100} \
      CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100} \
      CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100} \
      CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100} \
      CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100} \
      CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100} \
      CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
      CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
      CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
      CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
      CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
      CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
      CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
      CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
      CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
      CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
      CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
      CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
      CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
      CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
      CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \
      CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
      CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
      CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \
      CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \
      CONFIG.PSU__IRQ_P2F_CSU__INT {0} \
      CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
      CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
      CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
      CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
      CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \
      CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \
      CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \
      CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \
      CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \
      CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \
      CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
      CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
      CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
      CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
      CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
      CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
      CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
      CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
      CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \
      CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
      CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
      CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
      CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
      CONFIG.PSU__IRQ_P2F_NAND__INT {0} \
      CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
      CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
      CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
      CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
      CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
      CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
      CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
      CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
      CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
      CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
      CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
      CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
      CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
      CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
      CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \
      CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \
      CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
      CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
      CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \
      CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \
      CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
      CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
      CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
      CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
      CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
      CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
      CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
      CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
      CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
      CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
      CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
      CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
      CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
      CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
      CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
      CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
      CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
      CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
      CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
      CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
      CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
      CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
      CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
      CONFIG.PSU__L2_BANK0__POWER__ON {1} \
      CONFIG.PSU__LPDMA0_COHERENCY {0} \
      CONFIG.PSU__LPDMA1_COHERENCY {0} \
      CONFIG.PSU__LPDMA2_COHERENCY {0} \
      CONFIG.PSU__LPDMA3_COHERENCY {0} \
      CONFIG.PSU__LPDMA4_COHERENCY {0} \
      CONFIG.PSU__LPDMA5_COHERENCY {0} \
      CONFIG.PSU__LPDMA6_COHERENCY {0} \
      CONFIG.PSU__LPDMA7_COHERENCY {0} \
      CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
      CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
      CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
      CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \
      CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
      CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
      CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
      CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
      CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
      CONFIG.PSU__NAND_COHERENCY {0} \
      CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
      CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
      CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \
      CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \
      CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
      CONFIG.PSU__NUM_FABRIC_RESETS {1} \
      CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
      CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
      CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
      CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
      CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
      CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
      CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
      CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
      CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
      CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
      CONFIG.PSU__PCIE__BAR0_64BIT {0} \
      CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR0_VAL {} \
      CONFIG.PSU__PCIE__BAR1_64BIT {0} \
      CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR1_VAL {} \
      CONFIG.PSU__PCIE__BAR2_64BIT {0} \
      CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR2_VAL {} \
      CONFIG.PSU__PCIE__BAR3_64BIT {0} \
      CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR3_VAL {} \
      CONFIG.PSU__PCIE__BAR4_64BIT {0} \
      CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR4_VAL {} \
      CONFIG.PSU__PCIE__BAR5_64BIT {0} \
      CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
      CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
      CONFIG.PSU__PCIE__BAR5_VAL {} \
      CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
      CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
      CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
      CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \
      CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
      CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
      CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
      CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
      CONFIG.PSU__PCIE__DEVICE_ID {} \
      CONFIG.PSU__PCIE__ECRC_CHECK {0} \
      CONFIG.PSU__PCIE__ECRC_ERR {0} \
      CONFIG.PSU__PCIE__ECRC_GEN {0} \
      CONFIG.PSU__PCIE__EROM_ENABLE {0} \
      CONFIG.PSU__PCIE__EROM_VAL {} \
      CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
      CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
      CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
      CONFIG.PSU__PCIE__INTX_GENERATION {0} \
      CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
      CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
      CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
      CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
      CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
      CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
      CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
      CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
      CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
      CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
      CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
      CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
      CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
      CONFIG.PSU__PCIE__MULTIHEADER {0} \
      CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
      CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
      CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
      CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
      CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
      CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
      CONFIG.PSU__PCIE__REVISION_ID {} \
      CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
      CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
      CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
      CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
      CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
      CONFIG.PSU__PCIE__VENDOR_ID {} \
      CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__PL_CLK0_BUF {TRUE} \
      CONFIG.PSU__PL_CLK1_BUF {FALSE} \
      CONFIG.PSU__PL_CLK2_BUF {FALSE} \
      CONFIG.PSU__PL_CLK3_BUF {FALSE} \
      CONFIG.PSU__PL__POWER__ON {1} \
      CONFIG.PSU__PMU_COHERENCY {0} \
      CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
      CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
      CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
      CONFIG.PSU__PMU__GPI0__ENABLE {0} \
      CONFIG.PSU__PMU__GPI1__ENABLE {0} \
      CONFIG.PSU__PMU__GPI2__ENABLE {0} \
      CONFIG.PSU__PMU__GPI3__ENABLE {0} \
      CONFIG.PSU__PMU__GPI4__ENABLE {0} \
      CONFIG.PSU__PMU__GPI5__ENABLE {0} \
      CONFIG.PSU__PMU__GPO0__ENABLE {0} \
      CONFIG.PSU__PMU__GPO1__ENABLE {0} \
      CONFIG.PSU__PMU__GPO2__ENABLE {0} \
      CONFIG.PSU__PMU__GPO3__ENABLE {0} \
      CONFIG.PSU__PMU__GPO4__ENABLE {0} \
      CONFIG.PSU__PMU__GPO5__ENABLE {0} \
      CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
      CONFIG.PSU__PRESET_APPLIED {0} \
      CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
      CONFIG.PSU__PROTECTION__DEBUG {0} \
      CONFIG.PSU__PROTECTION__ENABLE {0} \
      CONFIG.PSU__PROTECTION__FPD_SEGMENTS {\
      SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |\
      SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
      subsystemId:Secure Subsystem} \
      CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
      CONFIG.PSU__PROTECTION__LPD_SEGMENTS {\
      SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
      SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
      SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ;\
      WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64;\
      UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure\
      Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ;\
      WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64;\
      UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
      CONFIG.PSU__PROTECTION__MASTERS {\
      USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;1|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
      CONFIG.PSU__PROTECTION__MASTERS_TZ {\
      GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \
      CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
      CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
      CONFIG.PSU__PROTECTION__SLAVES {\
      LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
      Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
      CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
      CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
      CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
      CONFIG.PSU__PSS_REF_CLK__FREQMHZ {50} \
      CONFIG.PSU__QSPI_COHERENCY {0} \
      CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
      CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
      CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
      CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
      CONFIG.PSU__REPORT__DBGLOG {0} \
      CONFIG.PSU__RPU_COHERENCY {0} \
      CONFIG.PSU__RPU__POWER__ON {1} \
      CONFIG.PSU__SATA__LANE0__ENABLE {0} \
      CONFIG.PSU__SATA__LANE1__ENABLE {0} \
      CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \
      CONFIG.PSU__SD0_COHERENCY {0} \
      CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__SD0__DATA_TRANSFER_MODE {8Bit} \
      CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
      CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
      CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
      CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 22} \
      CONFIG.PSU__SD0__RESET__ENABLE {0} \
      CONFIG.PSU__SD0__SLOT_TYPE {eMMC} \
      CONFIG.PSU__SD1_COHERENCY {0} \
      CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
      CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
      CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
      CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
      CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
      CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
      CONFIG.PSU__SD1__RESET__ENABLE {0} \
      CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
      CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
      CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
      CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
      CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
      CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
      CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
      CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
      CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
      CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
      CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
      CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
      CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
      CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
      CONFIG.PSU__TCM0A__POWER__ON {1} \
      CONFIG.PSU__TCM0B__POWER__ON {1} \
      CONFIG.PSU__TCM1A__POWER__ON {1} \
      CONFIG.PSU__TCM1B__POWER__ON {1} \
      CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \
      CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
      CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__TRISTATE__INVERTED {1} \
      CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
      CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
      CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
      CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
      CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
      CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
      CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
      CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
      CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
      CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
      CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
      CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
      CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
      CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
      CONFIG.PSU__UART0__BAUD_RATE {115200} \
      CONFIG.PSU__UART0__MODEM__ENABLE {0} \
      CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 54 .. 55} \
      CONFIG.PSU__UART1__MODEM__ENABLE {0} \
      CONFIG.PSU__UART1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__USB0_COHERENCY {0} \
      CONFIG.PSU__USB0__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__USB0__RESET__ENABLE {0} \
      CONFIG.PSU__USB1_COHERENCY {0} \
      CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__USB1__RESET__ENABLE {0} \
      CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
      CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
      CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
      CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
      CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \
      CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \
      CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
      CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
      CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
      CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \
      CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \
      CONFIG.PSU__USE__ADMA {0} \
      CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
      CONFIG.PSU__USE__AUDIO {0} \
      CONFIG.PSU__USE__CLK {0} \
      CONFIG.PSU__USE__CLK0 {0} \
      CONFIG.PSU__USE__CLK1 {0} \
      CONFIG.PSU__USE__CLK2 {0} \
      CONFIG.PSU__USE__CLK3 {0} \
      CONFIG.PSU__USE__CROSS_TRIGGER {0} \
      CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
      CONFIG.PSU__USE__DEBUG__TEST {0} \
      CONFIG.PSU__USE__EVENT_RPU {0} \
      CONFIG.PSU__USE__FABRIC__RST {1} \
      CONFIG.PSU__USE__FTM {0} \
      CONFIG.PSU__USE__GDMA {0} \
      CONFIG.PSU__USE__IRQ {0} \
      CONFIG.PSU__USE__IRQ0 {1} \
      CONFIG.PSU__USE__IRQ1 {0} \
      CONFIG.PSU__USE__M_AXI_GP0 {0} \
      CONFIG.PSU__USE__M_AXI_GP1 {0} \
      CONFIG.PSU__USE__M_AXI_GP2 {1} \
      CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
      CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
      CONFIG.PSU__USE__RST0 {0} \
      CONFIG.PSU__USE__RST1 {0} \
      CONFIG.PSU__USE__RST2 {0} \
      CONFIG.PSU__USE__RST3 {0} \
      CONFIG.PSU__USE__RTC {0} \
      CONFIG.PSU__USE__STM {0} \
      CONFIG.PSU__USE__S_AXI_ACE {0} \
      CONFIG.PSU__USE__S_AXI_ACP {0} \
      CONFIG.PSU__USE__S_AXI_GP0 {0} \
      CONFIG.PSU__USE__S_AXI_GP1 {0} \
      CONFIG.PSU__USE__S_AXI_GP2 {0} \
      CONFIG.PSU__USE__S_AXI_GP3 {0} \
      CONFIG.PSU__USE__S_AXI_GP4 {0} \
      CONFIG.PSU__USE__S_AXI_GP5 {0} \
      CONFIG.PSU__USE__S_AXI_GP6 {0} \
      CONFIG.PSU__USE__USB3_0_HUB {0} \
      CONFIG.PSU__USE__USB3_1_HUB {0} \
      CONFIG.PSU__USE__VIDEO {0} \
      CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
      CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
      CONFIG.QSPI_BOARD_INTERFACE {custom} \
      CONFIG.SATA_BOARD_INTERFACE {custom} \
      CONFIG.SD0_BOARD_INTERFACE {custom} \
      CONFIG.SD1_BOARD_INTERFACE {custom} \
      CONFIG.SPI0_BOARD_INTERFACE {custom} \
      CONFIG.SPI1_BOARD_INTERFACE {custom} \
      CONFIG.SUBPRESET1 {Custom} \
      CONFIG.SUBPRESET2 {Custom} \
      CONFIG.SWDT0_BOARD_INTERFACE {custom} \
      CONFIG.SWDT1_BOARD_INTERFACE {custom} \
      CONFIG.TRACE_BOARD_INTERFACE {custom} \
      CONFIG.TTC0_BOARD_INTERFACE {custom} \
      CONFIG.TTC1_BOARD_INTERFACE {custom} \
      CONFIG.TTC2_BOARD_INTERFACE {custom} \
      CONFIG.TTC3_BOARD_INTERFACE {custom} \
      CONFIG.UART0_BOARD_INTERFACE {custom} \
      CONFIG.UART1_BOARD_INTERFACE {custom} \
      CONFIG.USB0_BOARD_INTERFACE {custom} \
      CONFIG.USB1_BOARD_INTERFACE {custom} \
      ] $zynqmp_ps
      sw/Makefile
      View file @ a292404f
      ...@@ -43,7 +43,7 @@ endif ...@@ -43,7 +43,7 @@ endif
      DTC_BIN=artifacts/dtc DTC_BIN=artifacts/dtc
      GW_XSA=gw/hw_v$(SB_VER)/diot_sb_golden_hw_v$(SB_VER).xsa GW_XSA=../gw/output_files/diot_v$(SB_VER)/diot_v$(SB_VER).xsa
      export CROSS_COMPILE=aarch64-none-elf- export CROSS_COMPILE=aarch64-none-elf-
      export ARCH=aarch64 export ARCH=aarch64
      CROSS_COMPILE_MICROBLAZE=mb- CROSS_COMPILE_MICROBLAZE=mb-
      ...@@ -111,7 +111,6 @@ fetch: \ ...@@ -111,7 +111,6 @@ fetch: \
      # check the availability of commands # check the availability of commands
      $(XSCT_BIN) $(BOOTGEN_BIN) $(PETALINUX_BUILD_BIN) $(PETALINUX_CONFIG_BIN): $(XSCT_BIN) $(BOOTGEN_BIN) $(PETALINUX_BUILD_BIN) $(PETALINUX_CONFIG_BIN):
      $(if $(shell which $@),,$(error "$(@) not found")) $(if $(shell which $@),,$(error "$(@) not found"))
      ############################## u-boot ######################################### ############################## u-boot #########################################
      ...@@ -231,12 +230,12 @@ fsbl_config: bootfw_patch $(XSCT_BIN) $(GW_XSA) ...@@ -231,12 +230,12 @@ fsbl_config: bootfw_patch $(XSCT_BIN) $(GW_XSA)
      $(VT)echo -e "$(CO)Configuring fsbl...$(NC)" $(LOGT) $(VT)echo -e "$(CO)Configuring fsbl...$(NC)" $(LOGT)
      # gives erros like: # gives erros like:
      # WARNING: sysconfig command is DEPRECATED. # WARNING: sysconfig command is DEPRECATED.
      # #
      # Only one system configuration will be allowed in a platform. # Only one system configuration will be allowed in a platform.
      # If no system configuration is present, creating a domain will create the system configuration. # If no system configuration is present, creating a domain will create the system configuration.
      # #
      # ERROR:set_bsp_conf set periph_type_overrides {{BOARD template}}: Cannot set Property "periph_type_overrides" with {BOARD template} # ERROR:set_bsp_conf set periph_type_overrides {{BOARD template}}: Cannot set Property "periph_type_overrides" with {BOARD template}
      # #
      # ERROR: Could not find the bsp config parameter. # ERROR: Could not find the bsp config parameter.
      # to get the list of valida parameters on "os" run "bsp listparams -os" # to get the list of valida parameters on "os" run "bsp listparams -os"
      # to get the list of valida parameters on "processor" instance run "bsp listparams -proc" # to get the list of valida parameters on "processor" instance run "bsp listparams -proc"
      ...@@ -289,12 +288,12 @@ pmufw_config: bootfw_patch $(XSCT_BIN) $(GW_XSA) ...@@ -289,12 +288,12 @@ pmufw_config: bootfw_patch $(XSCT_BIN) $(GW_XSA)
      $(VT)echo -e "$(CO)Configuring pmufw...$(NC)" $(LOGT) $(VT)echo -e "$(CO)Configuring pmufw...$(NC)" $(LOGT)
      # gives erros like: # gives erros like:
      # WARNING: sysconfig command is DEPRECATED. # WARNING: sysconfig command is DEPRECATED.
      # #
      # Only one system configuration will be allowed in a platform. # Only one system configuration will be allowed in a platform.
      # If no system configuration is present, creating a domain will create the system configuration. # If no system configuration is present, creating a domain will create the system configuration.
      # #
      # ERROR:set_bsp_conf set periph_type_overrides {{BOARD template}}: Cannot set Property "periph_type_overrides" with {BOARD template} # ERROR:set_bsp_conf set periph_type_overrides {{BOARD template}}: Cannot set Property "periph_type_overrides" with {BOARD template}
      # #
      # ERROR: Could not find the bsp config parameter. # ERROR: Could not find the bsp config parameter.
      # to get the list of valida parameters on "os" run "bsp listparams -os" # to get the list of valida parameters on "os" run "bsp listparams -os"
      # to get the list of valida parameters on "processor" instance run "bsp listparams -proc" # to get the list of valida parameters on "processor" instance run "bsp listparams -proc"
      ...@@ -655,7 +654,6 @@ bootbin_distclean: ...@@ -655,7 +654,6 @@ bootbin_distclean:
      $(V) rm -f _done/bootbin_artifacts _done/bootbin_build _done/bootbin_config $(LOG) $(V) rm -f _done/bootbin_artifacts _done/bootbin_build _done/bootbin_config $(LOG)
      $(VT)echo -e "$(CO)Distclean boot.bin... done$(NC)" $(LOGT) $(VT)echo -e "$(CO)Distclean boot.bin... done$(NC)" $(LOGT)
      ############################## boot image (image.ub) ########################## ############################## boot image (image.ub) ##########################
      image_ub: image_ub_artifacts image_ub: image_ub_artifacts
      ......
      sw/configs/linux/linux_config
      View file @ a292404f
      ...@@ -1914,8 +1914,8 @@ CONFIG_VT_CONSOLE_SLEEP=y ...@@ -1914,8 +1914,8 @@ CONFIG_VT_CONSOLE_SLEEP=y
      CONFIG_HW_CONSOLE=y CONFIG_HW_CONSOLE=y
      CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_VT_HW_CONSOLE_BINDING=y
      CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTYS=y
      CONFIG_LEGACY_PTYS=y # CONFIG_LEGACY_PTYS is not set
      CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_LEGACY_PTY_COUNT is not set
      # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_SERIAL_NONSTANDARD is not set
      # CONFIG_NOZOMI is not set # CONFIG_NOZOMI is not set
      # CONFIG_N_GSM is not set # CONFIG_N_GSM is not set
      ......
      sw/gw/hw_v1/diot_sb_golden_hw_v1.xsa deleted 120000 → 0
      View file @ bd1726df
      ../../gw_all/diot_sb_v1_golden_211215.xsa
      \ No newline at end of file
      sw/gw/hw_v2/diot_sb_golden_hw_v2.xsa deleted 120000 → 0
      View file @ bd1726df
      ../../gw_all/diot_sb_v2_golden_211217.xsa
      \ No newline at end of file
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/diot-util.bb
      View file @ a292404f
      ...@@ -32,6 +32,8 @@ SRC_URI = " \ ...@@ -32,6 +32,8 @@ SRC_URI = " \
      file://term.h \ file://term.h \
      file://util.c \ file://util.c \
      file://util.h \ file://util.h \
      file://fpga_device.h \
      file://fpga_device.c \
      " "
      DEPENDS = "libgpiod readline lmsensors i2c-tools" DEPENDS = "libgpiod readline lmsensors i2c-tools"
      ...@@ -47,7 +49,6 @@ do_compile() { ...@@ -47,7 +49,6 @@ do_compile() {
      do_install() { do_install() {
      install -d ${D}${bindir} install -d ${D}${bindir}
      install -m 0755 ${S}/diot_util ${D}${bindir} install -m 0755 ${S}/diot_util ${D}${bindir}
      } }
      do_compile_prepend() { do_compile_prepend() {
      ......
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/Makefile
      View file @ a292404f
      ...@@ -13,6 +13,7 @@ APP_OBJS = \ ...@@ -13,6 +13,7 @@ APP_OBJS = \
      fru_utils.o \ fru_utils.o \
      term.o \ term.o \
      util.o \ util.o \
      fpga_device.o \
      LDLIBS+=-lgpiod -lreadline -lsensors -li2c LDLIBS+=-lgpiod -lreadline -lsensors -li2c
      CFLAGS+=-Wall -ggdb -g -O2 \ CFLAGS+=-Wall -ggdb -g -O2 \
      ......
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/diot_util.c
      View file @ a292404f
      ...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
      #include "util.h" #include "util.h"
      #include "fru_utils.h" #include "fru_utils.h"
      #include "fpga_device.h"
      #define DTB_HW_VER_FILE "/sys/firmware/devicetree/base/chosen/hw_ver" #define DTB_HW_VER_FILE "/sys/firmware/devicetree/base/chosen/hw_ver"
      #define DTB_MODEBOOT_FILE "/sys/firmware/devicetree/base/chosen/modeboot" #define DTB_MODEBOOT_FILE "/sys/firmware/devicetree/base/chosen/modeboot"
      ...@@ -38,6 +39,8 @@ ...@@ -38,6 +39,8 @@
      #define READLINE_PROMPT "diot_util> " #define READLINE_PROMPT "diot_util> "
      #define FPGA_DEVICE_ADDR 0x80000000
      #define RED_CHECK(x) x ? COLOR_RED: "" #define RED_CHECK(x) x ? COLOR_RED: ""
      #define RED_OFF(x) x ? COLOR_OFF: "" #define RED_OFF(x) x ? COLOR_OFF: ""
      ...@@ -70,7 +73,6 @@ struct string_map boot_mode_db[] = { ...@@ -70,7 +73,6 @@ struct string_map boot_mode_db[] = {
      { "nandboot", "nand" }, { "nandboot", "nand" },
      }; };
      struct command_entry commands_list[] = { struct command_entry commands_list[] = {
      { .cmd_name = "status", .cmd_func = cmd_print_status, .cmd_help_string = "Print status\n", .cmd_params = NULL}, { .cmd_name = "status", .cmd_func = cmd_print_status, .cmd_help_string = "Print status\n", .cmd_params = NULL},
      { .cmd_name = "exit", .cmd_func = cmd_exit, .cmd_help_string = "quit program\n", .cmd_params = NULL}, { .cmd_name = "exit", .cmd_func = cmd_exit, .cmd_help_string = "quit program\n", .cmd_params = NULL},
      ...@@ -88,25 +90,33 @@ struct command_entry commands_list[] = { ...@@ -88,25 +90,33 @@ struct command_entry commands_list[] = {
      { .cmd_name = "fantray", .cmd_func = cmd_fantray, .cmd_help_string = "Commands for fantray module. Type \"help " { .cmd_name = "fantray", .cmd_func = cmd_fantray, .cmd_help_string = "Commands for fantray module. Type \"help "
      "fantray\" for more information about " "fantray\" for more information about "
      "subcommands\n", .cmd_params = NULL}, "subcommands\n", .cmd_params = NULL},
      { .cmd_name = "gateware", .cmd_func = cmd_fpga, .cmd_help_string = "Print information related to the gateware. Type help for more information\n", .cmd_params = NULL},
      { .cmd_name = NULL } { .cmd_name = NULL }
      }; };
      int cmd_help(char *params) int cmd_help(char *params)
      { {
      struct command_entry *entry = commands_list; struct command_entry *entry;
      char buf[50]; char buf[50];
      /* Print fantray's help if requested */
      if (params && !strncmp(params, "fantray", strlen("fantray")))
      entry = commands_list_fantray;
      printf("diot_util for HW version %d\n", SB_VER); printf("diot_util for HW version %d\n", SB_VER);
      printf("Avaiable commands:\n"); printf("Available commands:\n");
      if (params && !strncmp(params, "fantray", strlen("fantray"))) {
      /* Print fantray's help if requested */
      entry = commands_list_fantray;
      } else if (params && !strncmp(params, "gateware", strlen("gateware"))) {
      /* Print gateware if requested */
      entry = commands_list_fpga_device;
      } else {
      entry = commands_list;
      }
      while (entry->cmd_name) { while (entry->cmd_name) {
      sprintf(buf, "%s %s", entry->cmd_name, sprintf(buf, "%s %s", entry->cmd_name,
      entry->cmd_params ? entry->cmd_params : ""); entry->cmd_params ? entry->cmd_params : "");
      printf("%-18s - %s", buf, entry->cmd_help_string); printf("%-18s - %s", buf, entry->cmd_help_string);
      entry++; entry++;
      } }
      return 0; return 0;
      ...@@ -379,6 +389,9 @@ int cmd_print_status(char *params) ...@@ -379,6 +389,9 @@ int cmd_print_status(char *params)
      printf("----------------------------+--------------+\n"); printf("----------------------------+--------------+\n");
      printf("\n"); printf("\n");
      get_fpga_status(false);
      printf("\n");
      print_slot_status(); print_slot_status();
      printf("\n"); printf("\n");
      print_fmc_status(); print_fmc_status();
      ...@@ -476,7 +489,7 @@ int main(int argc, char **argv) ...@@ -476,7 +489,7 @@ int main(int argc, char **argv)
      /* Copy command like readline would do */ /* Copy command like readline would do */
      line_read = strndup(curr_script_cmd, cmd_len); line_read = strndup(curr_script_cmd, cmd_len);
      } }
      } else { } else {
      /* Get a line from the user. */ /* Get a line from the user. */
      line_read = readline (READLINE_PROMPT); line_read = readline (READLINE_PROMPT);
      } }
      ...@@ -536,6 +549,9 @@ int main(int argc, char **argv) ...@@ -536,6 +549,9 @@ int main(int argc, char **argv)
      char * char *
      command_name_generator_fantray(const char *text, int state); command_name_generator_fantray(const char *text, int state);
      char *
      command_name_generator_gateware(const char *text, int state);
      char ** char **
      command_completion(const char *text, int start, int end) command_completion(const char *text, int start, int end)
      { {
      ...@@ -543,13 +559,17 @@ command_completion(const char *text, int start, int end) ...@@ -543,13 +559,17 @@ command_completion(const char *text, int start, int end)
      rl_attempted_completion_over = 1; rl_attempted_completion_over = 1;
      /* Call completion function if the first word */ /* Call completion function if the first word */
      if (start == 0) if (start == 0){
      return rl_completion_matches(text, command_name_generator); return rl_completion_matches(text, command_name_generator);
      }
      if (!strncmp(rl_line_buffer, "fantray load_fw", strlen("fantray load_fw"))) { if (!strncmp(rl_line_buffer, "fantray load_fw", strlen("fantray load_fw"))) {
      return rl_completion_matches(text, rl_filename_completion_function); return rl_completion_matches(text, rl_filename_completion_function);
      } }
      if (!strncmp(rl_line_buffer, "fantray", strlen("fantray"))) { if (!strncmp(rl_line_buffer, "fantray", strlen("fantray"))) {
      return rl_completion_matches(text, command_name_generator_fantray); return rl_completion_matches(text, command_name_generator_fantray);
      }
      if (!strncmp(rl_line_buffer, "gateware", strlen("gateware"))) {
      return rl_completion_matches(text, command_name_generator_gateware);
      } }
      return NULL; return NULL;
      } }
      ...@@ -593,3 +613,23 @@ char *command_name_generator_fantray(const char *text, int state) ...@@ -593,3 +613,23 @@ char *command_name_generator_fantray(const char *text, int state)
      return NULL; return NULL;
      } }
      /* command name generator for gateware */
      char *command_name_generator_gateware(const char *text, int state)
      {
      static int list_index, len;
      char *name;
      if (!state) {
      list_index = 0;
      len = strlen(text);
      }
      while ((commands_list_fpga_device[list_index].cmd_name) && (name = commands_list_fpga_device[list_index++].cmd_name)) {
      if (strncmp(name, text, len) == 0) {
      return strdup(name);
      }
      }
      return NULL;
      }
      \ No newline at end of file
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/fpga_device.c 0 → 100644
      View file @ a292404f
      /******************************************************************************/
      /*
      *
      * @file fpga_device.c
      *
      * Functions to plot the FPGA Device info
      *
      ******************************************************************************/
      /***************************** Include Files **********************************/
      #include "fpga_device.h"
      /************************** Functions Prototype *******************************/
      static int cmd_fpga_status (char *params);
      /******************************** Structs *************************************/
      struct command_entry commands_list_fpga_device[] = {
      { .cmd_name = "status", .cmd_func = cmd_fpga_status, .cmd_help_string = "Get all the information about FPGA convention\n", .cmd_params = "<all>"},
      { .cmd_name = NULL }
      };
      /******************************* Functions ************************************/
      /******************************************************************************/
      /**
      * This function print the information related with FPGA convention
      *
      ******************************************************************************/
      int get_fpga_status(bool full_info){
      struct tm build_date_s;
      char core_id_c[4] = { [0 ... 3] = 0 };
      char name_c[9] = { [0 ... 8] = 0 };
      char build_date_c[80] = { [0 ... 79] = 0 };
      char git_tag_c[9] = { [0 ... 8] = 0 };
      uintptr_t auxaddr = c_ADDR_IP_CORE;
      int fd = open("/dev/mem", O_RDWR | O_SYNC);
      if (fd < 0) {
      perror("Failed in Open device");
      return fd;
      }
      uint32_t * regs_32b = mmap(0, c_SIZE_BYTES, PROT_READ | PROT_WRITE, MAP_SHARED, fd, auxaddr);
      if (regs_32b == MAP_FAILED) {
      close(fd);
      perror("Failed in Mmap device");
      return -2;
      }
      printf("Gateware information\n");
      if (full_info) {
      //! Read Core ID
      uint32_t aux_core_id = bswap_32(regs_32b[c_ADDR_CORE_ID]);
      memcpy(&core_id_c,&aux_core_id,4);
      //! Read Project Name
      uint64_t name_u64 = bswap_64(((uint64_t) regs_32b[c_ADDR_NAME_MSB] << 32) + (uint64_t) regs_32b[c_ADDR_NAME_LSB]);
      memcpy(&name_c,&name_u64,8);
      }
      //! Read Build Date
      time_t date = (time_t) regs_32b[c_ADDR_BUILD_T];
      build_date_s = *localtime(&date);
      strftime(build_date_c, sizeof(build_date_c), "%a %Y-%m-%d %H:%M:%S", &build_date_s);
      //! Read String Tag
      uint64_t git_tag_u64 = bswap_64(((uint64_t) regs_32b[c_ADDR_TAG_MSB] << 32) + (uint64_t) regs_32b[c_ADDR_TAG_LSB]);
      memcpy(&git_tag_c,&git_tag_u64,8);
      if (full_info) {
      printf("VENDOR ID : %08x\n",regs_32b[c_ADDR_VENDOR_ID]);
      printf("DEVICE ID : %08x\n",regs_32b[c_ADDR_DEVICE_ID]);
      printf("VERSION : %08x\n",regs_32b[c_ADDR_VERSION]);
      printf("Byte Order Map : %08x\n",regs_32b[c_ADDR_BYTE_ORD_MARK]);
      printf("Source ID : %08x%08x%08x%08x\n",regs_32b[c_ADDR_SOURCE_ID_3],regs_32b[c_ADDR_SOURCE_ID_2],regs_32b[c_ADDR_SOURCE_ID_1],regs_32b[c_ADDR_SOURCE_ID_0]);
      printf("Capability Mask : %08x\n",regs_32b[c_ADDR_CAP_MASK]);
      printf("UUID : %08x%08x%08x%08x\n",regs_32b[c_ADDR_VENDOR_UUID_3],regs_32b[c_ADDR_VENDOR_UUID_2],regs_32b[c_ADDR_VENDOR_UUID_1],regs_32b[c_ADDR_VENDOR_UUID_0]);
      printf("IP CORE ID : %s\n",core_id_c);
      printf("NAME : %s\n",name_c);
      printf("BUILD DATE : %s\n",build_date_c);
      printf("GIT HASH : %08x%08x%08x%08x%08x\n",regs_32b[c_ADDR_HASH_4],regs_32b[c_ADDR_HASH_3],regs_32b[c_ADDR_HASH_2],regs_32b[c_ADDR_HASH_1],regs_32b[c_ADDR_HASH_0]);
      printf("GIT TAG : %s\n",git_tag_c);
      printf("DNA : %08x%08x%08x\n",regs_32b[c_ADDR_DNA_2],regs_32b[c_ADDR_DNA_1],regs_32b[c_ADDR_DNA_0]);
      } else {
      printf("BUILD DATE : %s\n",build_date_c);
      printf("GIT HASH : %08x%08x%08x%08x%08x\n",regs_32b[c_ADDR_HASH_4],regs_32b[c_ADDR_HASH_3],regs_32b[c_ADDR_HASH_2],regs_32b[c_ADDR_HASH_1],regs_32b[c_ADDR_HASH_0]);
      printf("GIT TAG : %s\n",git_tag_c);
      }
      munmap(regs_32b, c_SIZE_BYTES);
      close(fd);
      return 0;
      }
      /******************************************************************************/
      /**
      * This function implemets subcommand status related with FPGA information
      *
      ******************************************************************************/
      static int cmd_fpga_status(char *params) {
      int ret = 0;
      char *aux_params = NULL;
      if (!params || !(*params)) {
      printf("case no params \n");
      ret = get_fpga_status(false);
      } else {
      aux_params = strchr(params, ' ');
      if (!aux_params || !(*aux_params)) {
      if (!strncmp(params, "all", strlen("all"))) {
      ret = get_fpga_status(true);
      } else {
      cmd_help("gateware");
      }
      } else {
      cmd_help("gateware");
      }
      }
      if (ret != 0) {
      perror("Command gateware status failed");
      }
      return ret;
      }
      /******************************************************************************/
      /**
      * This function search for subcommands related with FPGA information
      *
      ******************************************************************************/
      int cmd_fpga (char *params) {
      struct command_entry *entry;
      char *cmd_start_p = params;
      int ret = 0;
      int cmd_len;
      if (!params || !(*params)) {
      printf("Please provide subcommand for the gateware command\n");
      cmd_help("gateware");
      ret = -ENOENT;
      } else {
      params = strchr(params, ' ');
      if (params) {
      cmd_len = params - cmd_start_p;
      /* skip spaces for params */
      while (*params && (*params == ' ')) {
      params++;
      }
      } else {
      cmd_len = strlen(cmd_start_p);
      }
      entry = commands_list_fpga_device;
      while (entry && entry->cmd_name) {
      if (cmd_len == strlen(entry->cmd_name) && !strncmp(entry->cmd_name, cmd_start_p, cmd_len)) {
      ret = entry->cmd_func(params);
      break;
      }
      entry++;
      }
      if (!(entry && entry->cmd_name)) {
      printf("Commad \"%s\" not found\n", cmd_start_p);
      ret = -ENOENT;
      }
      }
      return ret;
      }
      \ No newline at end of file
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/fpga_device.h 0 → 100644
      View file @ a292404f
      /** @file fpga_device.h
      *
      * @brief Library for FPGA device Convention
      *
      * @author alen.arias.vazquez@cern.ch
      * @date 12/05/2022
      * @url https://ohwr.org/project/fpga-dev-id/wikis/home
      *
      */
      #ifndef __FPGA_DEVICE_H
      #define __FPGA_DEVICE_H
      #ifdef __cplusplus
      extern "C" {
      #endif
      /***************************** Include Files **********************************/
      #include <limits.h>
      #include <stdlib.h>
      #include <stdio.h>
      #include <stdint.h>
      #include <string.h>
      #include <time.h>
      #include <unistd.h>
      #include <byteswap.h>
      #include <fcntl.h>
      #include <sys/stat.h>
      #include <sys/mman.h>
      #include <errno.h>
      #include <stdbool.h>
      #include "diot_util.h"
      /************************** Constant Definitions ******************************/
      /***************** Macros (Inline Functions) Definitions **********************/
      #define c_ADDR_VENDOR_ID 0x00
      #define c_ADDR_DEVICE_ID 0x01
      #define c_ADDR_VERSION 0x02
      #define c_ADDR_BYTE_ORD_MARK 0x03
      #define c_ADDR_SOURCE_ID_0 0x04
      #define c_ADDR_SOURCE_ID_1 0x05
      #define c_ADDR_SOURCE_ID_2 0x06
      #define c_ADDR_SOURCE_ID_3 0x07
      #define c_ADDR_CAP_MASK 0x08
      #define c_ADDR_VENDOR_UUID_0 0x0C
      #define c_ADDR_VENDOR_UUID_1 0x0D
      #define c_ADDR_VENDOR_UUID_2 0x0E
      #define c_ADDR_VENDOR_UUID_3 0x0F
      #define c_ADDR_CORE_ID 0x10
      #define c_ADDR_NAME_LSB 0x11
      #define c_ADDR_NAME_MSB 0x12
      #define c_ADDR_BUILD_T 0x13
      #define c_ADDR_HASH_0 0x14
      #define c_ADDR_HASH_1 0x15
      #define c_ADDR_HASH_2 0x16
      #define c_ADDR_HASH_3 0x17
      #define c_ADDR_HASH_4 0x18
      #define c_ADDR_DNA_0 0x19
      #define c_ADDR_DNA_1 0x1A
      #define c_ADDR_DNA_2 0x1B
      #define c_ADDR_TAG_LSB 0x1C
      #define c_ADDR_TAG_MSB 0x1D
      #define c_ADDR_IP_CORE 0x80000000
      #define c_SIZE_BYTES c_ADDR_TAG_MSB*4
      /**************************** Type Definitions ********************************/
      /******************************** Structs *************************************/
      extern struct command_entry commands_list_fpga_device[];
      /************************** Variable Definitions ******************************/
      /************************** Function Prototypes *******************************/
      int cmd_fpga (char *params);
      int get_fpga_status(bool full_info);
      #ifdef __cplusplus
      }
      #endif
      #endif /* __FPGA_DEVICE_H */
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