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DIOT Zynq Ultrascale-based System Board
Issues
#186
[L7] some clock lines near IC4 are missing GND return vias (like it's done for 7_PE_CLK_P/N)
1_PE_CLK_P/N
4_PE_CLK_P/N
5_PE_CLK_P/N
Edited
Aug 20, 2020
by
Filip Świtakowski
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