Skip to content
GitLab
Explore
Sign in
Projects
DIOT Zynq Ultrascale-based System Board
Issues
#22
[Cpcis_connectors_P1_P2_P3] Remove "<n>_PE_TX_P/N" labels, they are not used anywhere else
To upload designs, you'll need to enable LFS and have an admin enable hashed storage.
More information