Design reviews
Design reviews (schematics, PCB layout and VHDL firmware code) are very helpful to find errors early on. Most projects on the ohwr site have been extensively reviewed which has saved several design spins. The reviews are also a great way to learn about designing and can help you to explain why a design is done in a certain way. Therefore we suggest that you document the review comments on the ohwr site.
Documenting Schematics design reviews
Standardising the way of documenting design reviews will help the ease of interpreting the comments. At CERN we came up with the following suggestions.
1.- Sheet references
Group the comments by schematic page that they belong to. Some check the design in Altium and others the schematics pdf. For those that review from schematics, please reference the comments to both the sheet number and the name of the page (bad numbering is happening too often in designs).
2.- Subdivision of the review
Divide the review comments in the following sections:
+ Schematics
-- Schematics pages
-- BOM
+ Layout
-- Power planes
-- Clocks
-- High speed lines
-- FPGAs
-- IOs
-- rest of layout
3.- Reference to components
Use the IC**, R**, C**, L** identifier of components in addition to the usual references like AD5662, VMEH22501, Si570. It will reduce the chances of interpretation errors.
4.- Tagging by relevancy
Use a scale for the relevancy of the comments and order the comments accordingly:
! : fatal
+ : important
- : minor
? : question
* : note
A comment in your review file could look like this:
! VCC pin in IC14 is connected to GND
Examples of schematics design reviews
Following above suggestions
- Schematics review 03.02.2012 (from SVEC project)
- Review25042012 (from SVEC project)
Not following the above suggestions
- Review02032010 schematics review (from fmc-adc-100m14b4cha project)
- Review24032010 PCB review (from fmc-adc-100m14b4cha project)
Examples of firmware design reviews
- VHDL design review of nanoFIP
Schematics design review checklist
Create and study BOM, powerlist and netlist
-
Use as few different components as possible.
- A single BOM line is costing roughly 100-200 CHF (ordering, putting roll on machine etc.) and you will save time for yourself (checking BOM, ordering) and will also have less chances of mounting the wrong components.
- Print the BOM, check the resistor values used and see if you can remove some values by putting them in parallel or series (or actually taking existing values that are as good). The same for capacitors.
- Check if high precision or high power components are used (e.g. 0.1% or 0.5W) are needed.
- Avoid through-hole components as they should be manually mounted.
- Print out the power and ground list for all ICs and check if they’re correctly connected.
- Print out the netlist, sort alphabetically and check for any
inconsistencies (in naming, bus signals all used).
This takes some time, but really can show non-obvious mistakes.
Study schematics
- Buses: check if all bits are used.
- Differential signals: check if both _P and _N are used (and have really this polarity).
- Power signals naming: use P3V3, P5V, M12V etc.
- Check each connection of ICs. Notably hard-wired settings of ICs (division/amplification factors, operating modes etc. Add a note).
- Check polarity of capacitors, notably on those connected to negative power supplies.
- Check correct polarity of diodes and LEDs.
- Check if enough decoupling for each IC.
- Check global decoupling of power supplies (large cap at point of generation or entry).
- Check protection circuits on the signals. Verify in detail where current flows through.
- Check if signal levels are compatible between outputs and inputs (LVTTL etc.).
- Check for any crosses on wires (showing no connection) and check connectivity of crossing wires (a dot should show connected).
- Check if there is a note about hard-wired settings of ICs (division/amplification factors, operating modes etc.).
- Check if components are aligned to make the schematics look clear.
- Check consistency of naming and numbering of schematic pages.
FMC mezzanine cards
- EEPROM: GA1 should connect to A0, GA0 should connect to A1 (Observation 5.22 FMC spec).
- TDI and TDO are connected together if not used on the mezzanine
- Connect all mounting holes to ground (this is not in the specification, but is the best practice).
- Have a note on the schematic about allowed Vadj level (e.g. most carriers on ohwr can provide only 2V5).
- Foresee decoupling capacitors near the FMC connector (allowing power pins to work as signal return too).
Erik van der Bij, Carlos Gil Soriano, Matthieu Cattin - 6 November 2015