Transparent Bridge Wrapper for EBM
added by Mathias Kreider on 2013-07-19 14:32:54.257700
A transparent bridge approach over UDP should be feasible,
but there are restrictions for this usecase.
These would be:
- Only one packet in flight at any given time to avoid reordering
- EBM will stall until all operations are ack'ed or time out is hit
- Timeout must be in the range of 2 seconds (!) to rule out late
packet arrival
The wishbone bus assumes lossless and error free transmission
which UDP does not offer. We chose UDP for various reasons
in the timing system, first and foremost because of the low
overhead and the fact that we would not have the time for
retransmission anyway. The Timing master will use a hardware
EB master in the next release, but the situation is somewhat
simpler because it will broadcast and does not expect an answer.
A transparent bridge however means blocking the device until
read operations fetched their data and are acknowledged,
which can be slow, flawed because of packet reordering or a
packet might be lost entirely.
To my opinion, satisfying the Wishbone requirement would mean
either using TCP, recreate its functionality (which is redundant)
or introduce conditions under which this bridge can be called
transparent even when using UDP and WB standard is still satisfied.
Etherbone Hardware Master
added by Mathias Kreider on 2013-07-19 14:12:41.892049
Finished the first hand tested version of a hardware eb master
recently.
So far everything works nicely and it looks quite performant, the
interface
looks and feels a bit like a DMA controller kind of thing.
I had to use a couple of tricks in the interface in order to satisfy the
wishbone standard,
so this core is not transparent.
A wrapper that could achieve this is in planning
EtherBone goes BETA
added by Mathias Kreider on 2012-03-27 14:28:16.267228
As shown at the WhiteRabbit Workshop, we now have running Hard- and
Software
implementations. The EtherBone HDL core provides a slave module to go
with
the WR PTP core, while the API is flexible in its role and platform
independent.
Work in progress is systematic and randomized tests of both the API and
the HDL core
and finalization of documentation and code cleanup.
Project status will change to Beta in the coming days.
Initial EB master slave on hardware: the aftermath
added by Mathias Kreider on 2011-11-15 16:23:27.176859
I did a little dry run implementation sending back and forth messages
in inside one FPGA for the last WR Dev workshop, reading and writing
and reading data to and from a PWM controller hooked up to some LEDs.
Now the current task remains to update everything to EB spec v 0.2,
clean up, do monte carlo testing and adapt to the network interface
of WR core. Integration work from both sides has just begun, so stay
tuned
Etherbone Dissector for Wireshark
added by Mathias Kreider on 2011-08-18 12:25:58.041948
I've written this a while ago to inspect the EB packets generated from
my testbenches and test for
conformity. This is for the not yet exisiting version 0.2, so it will
need some work from Wesley
on the software lib before you can really play. If requested, I will
adapt the script fro V 0.1.
version from workshop demo uploaded
added by Mathias Kreider on 2011-04-19 14:42:43.186440
-Repo file clean up and renaming done
-Serialiser/Deserialiser to/from std_logic_vector implemented as
top_level EB_CORE_std_lgc_vec.vhd
TODO:
- cleanup code according to style guide
- rename signals with new nomenclature
- minor performance improvements
- test with 32/16b wishbone adapter when available
Etherbone/FEC demo layout
added by Mathias Kreider on 2011-03-09 16:29:11.886948
FEC is a complete standalone encoder/decoder block
which can be bypassed
Etherbone core will only support Wishbone slaves, not masters.
Remote EB Mastre will be in software on intel based PC with a GUI
for controlling remote memory mapped EB/Wishbone devices.
Controllable devices will be LED, PWM signal generator and
fake (free running) system time with get/set
NIOS soft CPU will configure altera 10/100/1000 ethernet mac.
The mac will be directly connected to the buffer stage as a streaming
sink/source.
First draft of functional spec
added by Julian Lewis on 2010-10-11 16:43:27.316537
The Document document is ready for comments.