10:00:41 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
10:00:42 INFO  : XSDB server has started successfully.
10:00:42 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
16:22:27 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
16:22:28 INFO  : XSDB server has started successfully.
16:22:34 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
16:22:35 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
16:25:36 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:25:36 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:25:54 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
16:26:43 INFO  : ps7_init is completed.
16:26:43 INFO  : ps7_post_config is completed.
16:26:43 INFO  : Processor reset is completed for ps7_cortexa9_0
16:33:26 INFO  : Processor reset is completed for ps7_cortexa9_0
16:37:31 INFO  : Processor reset is completed for ps7_cortexa9_0
16:48:27 INFO  : Processor reset is completed for ps7_cortexa9_0
18:05:23 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:05:23 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:05:40 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:06:12 INFO  : ps7_init is completed.
18:06:12 INFO  : ps7_post_config is completed.
18:06:13 INFO  : Processor reset is completed for ps7_cortexa9_0
18:07:47 INFO  : Processor reset is completed for ps7_cortexa9_0
18:08:37 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:08:37 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:08:54 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:09:51 ERROR : Unexpected error while parsing XMD response : com.google.gson.JsonSyntaxException: com.google.gson.stream.MalformedJsonException: invalid number or unquoted string near 
18:54:40 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
18:54:42 INFO  : XSDB server has started successfully.
18:54:42 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
18:54:44 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
18:55:21 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:55:38 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:55:38 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:55:56 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
19:00:12 ERROR : Checking FPGA configuration failed..Connection to Board Failed


    Unknown Error Occured
    Cable is not powered-on

19:00:12 ERROR : Unexpected error while launching program.
com.xilinx.sdk.targetmanager.TMException: Connection to Board Failed


    Unknown Error Occured
    Cable is not powered-on

	at com.xilinx.sdk.targetmanager.internal.TM.isFPGAConfigured(TM.java:374)
	at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.isFpgaConfigured(XilinxAppLaunchConfigurationDelegate.java:409)
	at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.launch(XilinxAppLaunchConfigurationDelegate.java:303)
	at com.xilinx.sdk.debug.ui.XilinxAppLaunchDelegateWrapper.launch(XilinxAppLaunchDelegateWrapper.java:31)
	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885)
	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739)
	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1039)
	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1256)
	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55)
19:00:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:00:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:01:08 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
19:01:16 ERROR : Checking FPGA configuration failed..Connection to Board Failed


    Unknown Error Occured
    Cable is not powered-on

19:01:16 ERROR : Unexpected error while launching program.
com.xilinx.sdk.targetmanager.TMException: Connection to Board Failed


    Unknown Error Occured
    Cable is not powered-on

	at com.xilinx.sdk.targetmanager.internal.TM.isFPGAConfigured(TM.java:374)
	at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.isFpgaConfigured(XilinxAppLaunchConfigurationDelegate.java:409)
	at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.launch(XilinxAppLaunchConfigurationDelegate.java:303)
	at com.xilinx.sdk.debug.ui.XilinxAppLaunchDelegateWrapper.launch(XilinxAppLaunchDelegateWrapper.java:31)
	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885)
	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739)
	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1039)
	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1256)
	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55)
19:02:07 ERROR : Checking FPGA configuration failed..Connection to Board Failed


    Unknown Error Occured
    Cable is not powered-on

19:02:07 ERROR : Unexpected error while launching program.
com.xilinx.sdk.targetmanager.TMException: Connection to Board Failed


    Unknown Error Occured
    Cable is not powered-on

	at com.xilinx.sdk.targetmanager.internal.TM.isFPGAConfigured(TM.java:374)
	at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.isFpgaConfigured(XilinxAppLaunchConfigurationDelegate.java:409)
	at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.launch(XilinxAppLaunchConfigurationDelegate.java:303)
	at com.xilinx.sdk.debug.ui.XilinxAppLaunchDelegateWrapper.launch(XilinxAppLaunchDelegateWrapper.java:31)
	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885)
	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739)
	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1039)
	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1256)
	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55)
19:02:13 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:02:13 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:02:30 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
19:02:54 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:02:54 INFO  : 'fpga -state' command is executed.
19:02:54 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:02:54 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:02:54 INFO  : 'jtag frequency' command is executed.
19:02:54 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:02:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:02:54 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:02:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:02:54 INFO  : 'stop' command is executed.
19:02:55 INFO  : 'ps7_init' command is executed.
19:02:55 INFO  : 'ps7_post_config' command is executed.
19:02:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:02:56 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:02:56 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:02:56 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Hello_FASEC/Debug/Hello_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:02:56 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Hello_FASEC/Debug/Hello_FASEC.elf
----------------End of Script----------------

19:02:56 INFO  : Memory regions updated for context APU
19:02:56 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:02:56 INFO  : 'con' command is executed.
19:02:56 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:02:56 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_hello_fasec.elf.tcl'
19:05:06 INFO  : Disconnected from the channel tcfchan#1.
19:05:06 ERROR : Checking FPGA configuration failed..Connection to Board Failed


    Unknown Error Occured
    Cable is not powered-on

19:05:06 ERROR : Unexpected error while launching program.
com.xilinx.sdk.targetmanager.TMException: Connection to Board Failed


    Unknown Error Occured
    Cable is not powered-on

	at com.xilinx.sdk.targetmanager.internal.TM.isFPGAConfigured(TM.java:374)
	at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.isFpgaConfigured(XilinxAppLaunchConfigurationDelegate.java:409)
	at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.launch(XilinxAppLaunchConfigurationDelegate.java:303)
	at com.xilinx.sdk.debug.ui.XilinxAppLaunchDelegateWrapper.launch(XilinxAppLaunchDelegateWrapper.java:31)
	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885)
	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739)
	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1039)
	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1256)
	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55)
19:05:25 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:05:25 INFO  : 'fpga -state' command is executed.
19:05:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:05:25 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:05:25 INFO  : 'jtag frequency' command is executed.
19:05:25 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:05:25 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:05:32 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:05:32 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:05:32 INFO  : 'stop' command is executed.
19:05:33 INFO  : 'ps7_init' command is executed.
19:05:33 INFO  : 'ps7_post_config' command is executed.
19:05:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:05:33 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:05:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:05:34 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Hello_FASEC/Debug/Hello_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:05:34 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Hello_FASEC/Debug/Hello_FASEC.elf
----------------End of Script----------------

19:05:34 INFO  : Memory regions updated for context APU
19:05:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:05:34 INFO  : 'con' command is executed.
19:05:34 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:05:34 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_hello_fasec.elf.tcl'
19:17:47 INFO  : Disconnected from the channel tcfchan#2.
19:17:48 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:17:48 INFO  : 'fpga -state' command is executed.
19:17:48 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:17:48 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:17:48 INFO  : 'jtag frequency' command is executed.
19:17:48 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:17:48 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:17:54 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:17:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:17:54 INFO  : 'stop' command is executed.
19:17:55 INFO  : 'ps7_init' command is executed.
19:17:55 INFO  : 'ps7_post_config' command is executed.
19:17:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:17:55 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:17:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:17:56 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Mem-Test_FASEC/Debug/Mem-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:17:56 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Mem-Test_FASEC/Debug/Mem-Test_FASEC.elf
----------------End of Script----------------

19:17:56 INFO  : Memory regions updated for context APU
19:17:56 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:17:56 INFO  : 'con' command is executed.
19:17:56 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:17:56 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_mem-test_fasec.elf.tcl'
19:26:27 INFO  : Disconnected from the channel tcfchan#3.
19:26:27 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:26:27 INFO  : 'fpga -state' command is executed.
19:26:27 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:26:27 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:26:27 INFO  : 'jtag frequency' command is executed.
19:26:27 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:26:27 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:26:32 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:26:32 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:26:32 INFO  : 'stop' command is executed.
19:26:34 INFO  : 'ps7_init' command is executed.
19:26:34 INFO  : 'ps7_post_config' command is executed.
19:26:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:26:34 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:26:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:26:34 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Mem-Test_FASEC/Debug/Mem-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:26:34 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Mem-Test_FASEC/Debug/Mem-Test_FASEC.elf
----------------End of Script----------------

19:26:34 INFO  : Memory regions updated for context APU
19:26:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:26:34 INFO  : 'con' command is executed.
19:26:34 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:26:34 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_mem-test_fasec.elf.tcl'
19:27:33 INFO  : Disconnected from the channel tcfchan#4.
19:27:34 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:27:34 INFO  : 'fpga -state' command is executed.
19:27:34 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:27:35 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:27:35 INFO  : 'jtag frequency' command is executed.
19:27:35 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:27:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:27:40 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:27:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:27:40 INFO  : 'stop' command is executed.
19:27:41 INFO  : 'ps7_init' command is executed.
19:27:41 INFO  : 'ps7_post_config' command is executed.
19:27:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:27:41 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:27:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:27:43 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:27:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

19:27:43 INFO  : Memory regions updated for context APU
19:27:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:27:43 INFO  : 'con' command is executed.
19:27:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:27:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
19:30:25 INFO  : Disconnected from the channel tcfchan#5.
19:30:25 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:30:25 INFO  : 'fpga -state' command is executed.
19:30:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:30:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:30:26 INFO  : 'jtag frequency' command is executed.
19:30:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:30:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:30:31 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:30:31 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:30:31 INFO  : 'stop' command is executed.
19:30:32 INFO  : 'ps7_init' command is executed.
19:30:33 INFO  : 'ps7_post_config' command is executed.
19:30:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:30:33 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:30:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:30:34 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:30:34 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

19:30:34 INFO  : Memory regions updated for context APU
19:30:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:30:34 INFO  : 'con' command is executed.
19:30:34 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:30:34 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
19:32:07 INFO  : Disconnected from the channel tcfchan#6.
19:32:08 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:32:08 INFO  : 'fpga -state' command is executed.
19:32:08 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:32:08 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:32:08 INFO  : 'jtag frequency' command is executed.
19:32:08 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:32:08 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:32:14 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:32:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:32:14 INFO  : 'stop' command is executed.
19:32:15 INFO  : 'ps7_init' command is executed.
19:32:15 INFO  : 'ps7_post_config' command is executed.
19:32:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:32:15 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:32:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:32:16 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Dhrystone_FASEC/Debug/Dhrystone_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:32:16 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Dhrystone_FASEC/Debug/Dhrystone_FASEC.elf
----------------End of Script----------------

19:32:16 INFO  : Memory regions updated for context APU
19:32:16 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:32:16 INFO  : 'con' command is executed.
19:32:16 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:32:16 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_dhrystone_fasec.elf.tcl'
19:48:27 INFO  : Disconnected from the channel tcfchan#7.
19:48:28 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:48:28 INFO  : 'fpga -state' command is executed.
19:48:28 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:48:28 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:48:28 INFO  : 'jtag frequency' command is executed.
19:48:28 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:48:28 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:48:34 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:48:34 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:48:34 INFO  : 'stop' command is executed.
19:48:35 INFO  : 'ps7_init' command is executed.
19:48:35 INFO  : 'ps7_post_config' command is executed.
19:48:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:48:35 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:48:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:48:37 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:48:37 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

19:48:37 INFO  : Memory regions updated for context APU
19:48:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:48:37 INFO  : 'con' command is executed.
19:48:37 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:48:37 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
19:52:51 INFO  : Disconnected from the channel tcfchan#8.
19:52:53 ERROR : Unexpected error while parsing XMD response : com.google.gson.JsonSyntaxException: com.google.gson.stream.MalformedJsonException: invalid number or unquoted string near 
08:35:50 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
08:35:51 INFO  : XSDB server has started successfully.
08:35:52 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
08:35:53 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
08:35:55 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1469601305000,  Project:1467272400000
08:35:55 INFO  : The hardware specification for project 'system_design_wrapper_hw_platform_0' is different from /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
08:35:55 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
08:36:02 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
08:36:03 INFO  : 
08:36:04 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
08:36:05 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
08:36:06 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
08:36:06 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
08:36:07 INFO  : Clearing existing target manager status.
09:27:38 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:27:48 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:27:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:28:06 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:39:32 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:39:32 INFO  : 'fpga -state' command is executed.
09:39:32 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:39:33 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:39:33 INFO  : 'jtag frequency' command is executed.
09:39:33 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:39:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:39:33 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:39:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:39:33 INFO  : 'stop' command is executed.
09:39:34 INFO  : 'ps7_init' command is executed.
09:39:34 INFO  : 'ps7_post_config' command is executed.
09:39:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:39:34 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:39:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:39:36 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:39:36 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:39:36 INFO  : Memory regions updated for context APU
09:39:36 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:39:36 INFO  : 'con' command is executed.
09:39:36 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:39:36 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:06:02 INFO  : Disconnected from the channel tcfchan#1.
10:06:02 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:06:02 INFO  : 'fpga -state' command is executed.
10:06:02 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:06:02 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:06:02 INFO  : 'jtag frequency' command is executed.
10:06:02 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:06:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:06:08 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:06:08 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:06:08 INFO  : 'stop' command is executed.
10:06:09 INFO  : 'ps7_init' command is executed.
10:06:09 INFO  : 'ps7_post_config' command is executed.
10:06:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:09 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:06:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:10 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:06:10 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:06:10 INFO  : Memory regions updated for context APU
10:06:10 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:11 INFO  : 'con' command is executed.
10:06:11 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:06:11 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
11:51:32 INFO  : Disconnected from the channel tcfchan#2.
11:51:33 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
11:51:33 INFO  : 'fpga -state' command is executed.
11:51:33 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
11:51:33 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
11:51:33 INFO  : 'jtag frequency' command is executed.
11:51:33 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
11:51:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:51:33 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
11:51:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:51:33 INFO  : 'stop' command is executed.
11:51:34 INFO  : 'ps7_init' command is executed.
11:51:34 INFO  : 'ps7_post_config' command is executed.
11:51:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:51:34 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
11:51:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:51:36 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
11:51:36 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

11:51:36 INFO  : Memory regions updated for context APU
11:51:36 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:51:36 INFO  : 'con' command is executed.
11:51:36 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

11:51:36 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
11:52:21 INFO  : Disconnected from the channel tcfchan#3.
11:52:21 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
11:52:21 INFO  : 'fpga -state' command is executed.
11:52:21 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
11:52:22 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
11:52:22 INFO  : 'jtag frequency' command is executed.
11:52:22 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
11:52:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:52:22 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
11:52:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:52:22 INFO  : 'stop' command is executed.
11:52:23 INFO  : 'ps7_init' command is executed.
11:52:23 INFO  : 'ps7_post_config' command is executed.
11:52:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:52:23 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
11:52:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:52:25 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
11:52:25 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

11:52:25 INFO  : Memory regions updated for context APU
11:52:25 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:52:25 INFO  : 'con' command is executed.
11:52:25 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

11:52:25 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
12:07:38 INFO  : Disconnected from the channel tcfchan#4.
12:07:38 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
12:07:38 INFO  : 'fpga -state' command is executed.
12:07:38 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
12:07:38 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
12:07:38 INFO  : 'jtag frequency' command is executed.
12:07:38 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
12:07:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:07:38 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
12:07:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:07:39 INFO  : 'stop' command is executed.
12:07:40 INFO  : 'ps7_init' command is executed.
12:07:40 INFO  : 'ps7_post_config' command is executed.
12:07:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:07:40 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
12:07:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:07:42 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
12:07:42 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

12:07:42 INFO  : Memory regions updated for context APU
12:07:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:07:42 INFO  : 'con' command is executed.
12:07:42 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

12:07:42 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
12:26:21 INFO  : Disconnected from the channel tcfchan#5.
12:26:21 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
12:26:21 INFO  : 'fpga -state' command is executed.
12:26:21 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
12:26:22 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
12:26:22 INFO  : 'jtag frequency' command is executed.
12:26:22 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
12:26:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:26:22 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
12:26:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:26:22 INFO  : 'stop' command is executed.
12:26:23 INFO  : 'ps7_init' command is executed.
12:26:23 INFO  : 'ps7_post_config' command is executed.
12:26:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:26:23 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
12:26:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:26:25 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
12:26:25 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

12:26:25 INFO  : Memory regions updated for context APU
12:26:25 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:26:25 INFO  : 'con' command is executed.
12:26:25 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

12:26:25 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
12:30:01 INFO  : Disconnected from the channel tcfchan#6.
12:30:01 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
12:30:01 INFO  : 'fpga -state' command is executed.
12:30:01 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
12:30:01 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
12:30:01 INFO  : 'jtag frequency' command is executed.
12:30:01 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
12:30:01 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:30:01 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
12:30:01 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:30:01 INFO  : 'stop' command is executed.
12:30:03 INFO  : 'ps7_init' command is executed.
12:30:03 INFO  : 'ps7_post_config' command is executed.
12:30:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:30:03 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
12:30:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:30:05 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
12:30:05 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

12:30:05 INFO  : Memory regions updated for context APU
12:30:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:30:05 INFO  : 'con' command is executed.
12:30:05 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

12:30:05 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
12:31:51 INFO  : Disconnected from the channel tcfchan#7.
12:31:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
12:31:51 INFO  : 'fpga -state' command is executed.
12:31:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
12:31:51 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
12:31:51 INFO  : 'jtag frequency' command is executed.
12:31:51 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
12:31:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:31:51 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
12:31:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:31:51 INFO  : 'stop' command is executed.
12:31:52 INFO  : 'ps7_init' command is executed.
12:31:52 INFO  : 'ps7_post_config' command is executed.
12:31:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:31:53 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
12:31:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:31:55 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
12:31:55 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

12:31:55 INFO  : Memory regions updated for context APU
12:31:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:31:55 INFO  : 'con' command is executed.
12:31:55 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

12:31:55 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:14:36 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:14:36 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:14:53 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:15:32 INFO  : Disconnected from the channel tcfchan#8.
08:15:32 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:15:32 INFO  : 'fpga -state' command is executed.
08:15:32 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:15:32 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:15:32 INFO  : 'jtag frequency' command is executed.
08:15:32 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:15:32 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:15:33 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:15:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:15:33 INFO  : 'stop' command is executed.
08:15:34 INFO  : 'ps7_init' command is executed.
08:15:34 INFO  : 'ps7_post_config' command is executed.
08:15:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:15:34 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:15:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:15:35 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:15:35 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:15:35 INFO  : Memory regions updated for context APU
08:15:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:15:35 INFO  : 'con' command is executed.
08:15:35 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:15:35 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:17:49 INFO  : Disconnected from the channel tcfchan#9.
08:17:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:17:49 INFO  : 'fpga -state' command is executed.
08:17:49 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:17:50 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:17:50 INFO  : 'jtag frequency' command is executed.
08:17:50 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:17:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:17:50 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:17:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:17:50 INFO  : 'stop' command is executed.
08:17:51 INFO  : 'ps7_init' command is executed.
08:17:51 INFO  : 'ps7_post_config' command is executed.
08:17:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:17:51 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:17:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:17:53 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:17:53 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:17:53 INFO  : Memory regions updated for context APU
08:17:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:17:53 INFO  : 'con' command is executed.
08:17:53 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:17:53 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:19:40 INFO  : Disconnected from the channel tcfchan#10.
08:19:47 INFO  : ps7_init is completed.
08:19:47 INFO  : ps7_post_config is completed.
08:19:47 INFO  : Processor reset is completed for ps7_cortexa9_0
08:22:30 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:22:30 INFO  : 'fpga -state' command is executed.
08:22:30 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:22:30 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:22:30 INFO  : 'jtag frequency' command is executed.
08:22:30 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:22:30 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:22:30 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:22:30 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:22:30 INFO  : 'stop' command is executed.
08:22:31 INFO  : 'ps7_init' command is executed.
08:22:31 INFO  : 'ps7_post_config' command is executed.
08:22:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:22:31 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:22:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:22:33 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:22:33 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:22:33 INFO  : Memory regions updated for context APU
08:22:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:22:33 INFO  : 'con' command is executed.
08:22:33 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:22:33 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:24:01 INFO  : Disconnected from the channel tcfchan#11.
08:24:01 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:24:02 INFO  : 'fpga -state' command is executed.
08:24:02 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:24:02 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:24:02 INFO  : 'jtag frequency' command is executed.
08:24:02 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:24:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:24:02 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:24:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:24:02 INFO  : 'stop' command is executed.
08:24:03 INFO  : 'ps7_init' command is executed.
08:24:03 INFO  : 'ps7_post_config' command is executed.
08:24:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:03 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:24:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:05 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:24:05 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:24:05 INFO  : Memory regions updated for context APU
08:24:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:05 INFO  : 'con' command is executed.
08:24:05 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:24:05 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:26:39 INFO  : Disconnected from the channel tcfchan#12.
08:26:39 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:26:39 INFO  : 'fpga -state' command is executed.
08:26:39 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:26:39 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:26:39 INFO  : 'jtag frequency' command is executed.
08:26:39 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:26:39 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:26:39 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:26:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:26:40 INFO  : 'stop' command is executed.
08:26:41 INFO  : 'ps7_init' command is executed.
08:26:41 INFO  : 'ps7_post_config' command is executed.
08:26:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:26:41 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:26:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:26:42 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:26:42 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:26:42 INFO  : Memory regions updated for context APU
08:26:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:26:42 INFO  : 'con' command is executed.
08:26:42 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:26:42 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:34:24 INFO  : Disconnected from the channel tcfchan#13.
08:34:24 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:34:24 INFO  : 'fpga -state' command is executed.
08:34:24 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:34:25 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:34:25 INFO  : 'jtag frequency' command is executed.
08:34:25 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:34:25 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:34:25 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:34:25 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:34:25 INFO  : 'stop' command is executed.
08:34:26 INFO  : 'ps7_init' command is executed.
08:34:26 INFO  : 'ps7_post_config' command is executed.
08:34:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:34:26 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:34:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:34:29 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:34:29 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:34:29 INFO  : Memory regions updated for context APU
08:34:29 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:34:29 INFO  : 'con' command is executed.
08:34:29 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:34:29 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:37:51 INFO  : Disconnected from the channel tcfchan#14.
08:37:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:37:51 INFO  : 'fpga -state' command is executed.
08:37:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:37:52 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:37:52 INFO  : 'jtag frequency' command is executed.
08:37:52 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:37:52 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:37:52 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:37:52 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:37:52 INFO  : 'stop' command is executed.
08:37:53 INFO  : 'ps7_init' command is executed.
08:37:53 INFO  : 'ps7_post_config' command is executed.
08:37:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:37:53 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:37:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:37:56 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:37:56 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:37:56 INFO  : Memory regions updated for context APU
08:37:56 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:37:56 INFO  : 'con' command is executed.
08:37:56 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:37:56 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:38:59 INFO  : Disconnected from the channel tcfchan#15.
08:39:00 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:39:00 INFO  : 'fpga -state' command is executed.
08:39:00 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:39:00 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:39:00 INFO  : 'jtag frequency' command is executed.
08:39:00 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:39:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:39:00 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:39:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:39:00 INFO  : 'stop' command is executed.
08:39:01 INFO  : 'ps7_init' command is executed.
08:39:01 INFO  : 'ps7_post_config' command is executed.
08:39:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:39:01 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:39:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:39:04 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:39:04 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:39:04 INFO  : Memory regions updated for context APU
08:39:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:39:04 INFO  : 'con' command is executed.
08:39:04 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:39:04 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:40:06 INFO  : Disconnected from the channel tcfchan#16.
08:40:07 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:40:07 INFO  : 'fpga -state' command is executed.
08:40:07 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:40:07 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:40:07 INFO  : 'jtag frequency' command is executed.
08:40:07 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:40:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:40:07 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:40:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:40:07 INFO  : 'stop' command is executed.
08:40:08 INFO  : 'ps7_init' command is executed.
08:40:08 INFO  : 'ps7_post_config' command is executed.
08:40:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:40:08 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:40:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:40:11 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:40:11 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:40:11 INFO  : Memory regions updated for context APU
08:40:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:40:11 INFO  : 'con' command is executed.
08:40:11 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:40:11 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:42:48 INFO  : Disconnected from the channel tcfchan#17.
08:42:48 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:42:48 INFO  : 'fpga -state' command is executed.
08:42:48 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:42:49 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:42:49 INFO  : 'jtag frequency' command is executed.
08:42:49 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:42:49 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:42:49 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:42:49 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:42:49 INFO  : 'stop' command is executed.
08:42:50 INFO  : 'ps7_init' command is executed.
08:42:50 INFO  : 'ps7_post_config' command is executed.
08:42:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:42:50 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:42:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:42:52 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:42:52 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:42:52 INFO  : Memory regions updated for context APU
08:42:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:42:52 INFO  : 'con' command is executed.
08:42:52 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:42:52 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:43:14 INFO  : Disconnected from the channel tcfchan#18.
08:43:14 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:43:14 INFO  : 'fpga -state' command is executed.
08:43:14 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:43:14 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:43:14 INFO  : 'jtag frequency' command is executed.
08:43:14 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:43:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:43:14 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:43:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:43:15 INFO  : 'stop' command is executed.
08:43:16 INFO  : 'ps7_init' command is executed.
08:43:16 INFO  : 'ps7_post_config' command is executed.
08:43:16 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:43:16 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:43:16 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:43:18 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:43:18 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:43:18 INFO  : Memory regions updated for context APU
08:43:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:43:18 INFO  : 'con' command is executed.
08:43:18 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:43:18 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:54:09 INFO  : Disconnected from the channel tcfchan#19.
08:54:10 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:54:10 INFO  : 'fpga -state' command is executed.
08:54:10 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:54:10 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:54:10 INFO  : 'jtag frequency' command is executed.
08:54:10 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:54:10 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:54:10 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:54:10 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:54:10 INFO  : 'stop' command is executed.
08:54:11 INFO  : 'ps7_init' command is executed.
08:54:11 INFO  : 'ps7_post_config' command is executed.
08:54:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:54:11 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:54:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:54:14 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:54:14 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:54:14 INFO  : Memory regions updated for context APU
08:54:14 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:54:14 INFO  : 'con' command is executed.
08:54:14 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:54:14 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:59:49 INFO  : Disconnected from the channel tcfchan#20.
08:59:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:59:49 INFO  : 'fpga -state' command is executed.
08:59:49 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:59:50 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:59:50 INFO  : 'jtag frequency' command is executed.
08:59:50 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:59:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:59:50 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:59:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:59:50 INFO  : 'stop' command is executed.
08:59:51 INFO  : 'ps7_init' command is executed.
08:59:51 INFO  : 'ps7_post_config' command is executed.
08:59:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:59:51 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:59:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:59:53 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:59:53 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:59:53 INFO  : Memory regions updated for context APU
08:59:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:59:53 INFO  : 'con' command is executed.
08:59:53 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:59:53 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:15:33 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:15:33 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:15:50 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:26:01 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1469689766000,  Project:1469601305000
09:26:01 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
09:26:07 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
09:26:13 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
09:26:15 INFO  : 
09:26:16 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
09:26:16 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
09:26:17 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
09:26:18 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
09:26:18 INFO  : Clearing existing target manager status.
09:26:18 INFO  : Closing and re-opening the MSS file of ther project standalone_bsp_0
09:26:18 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
09:26:19 WARN  : Linker script will not be updated automatically. Users need to update it manually.
09:27:06 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:27:06 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:27:23 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:27:32 INFO  : Disconnected from the channel tcfchan#21.
09:27:33 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:27:33 INFO  : 'fpga -state' command is executed.
09:27:33 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:27:33 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:27:33 INFO  : 'jtag frequency' command is executed.
09:27:33 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:27:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:27:33 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:27:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:27:33 INFO  : 'stop' command is executed.
09:27:34 INFO  : 'ps7_init' command is executed.
09:27:34 INFO  : 'ps7_post_config' command is executed.
09:27:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:27:34 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:27:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:27:36 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:27:36 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:27:36 INFO  : Memory regions updated for context APU
09:27:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:27:37 INFO  : 'con' command is executed.
09:27:37 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:27:37 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:34:37 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1469691224000,  Project:1469689766000
09:34:37 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
09:34:39 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
09:34:47 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
09:34:49 INFO  : 
09:34:49 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
09:34:50 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
09:34:51 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
09:34:52 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
09:34:52 INFO  : Clearing existing target manager status.
09:34:52 INFO  : Closing and re-opening the MSS file of ther project standalone_bsp_0
09:34:52 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
09:34:53 WARN  : Linker script will not be updated automatically. Users need to update it manually.
09:42:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:42:50 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:43:07 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:43:26 INFO  : Disconnected from the channel tcfchan#22.
09:43:27 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:43:27 INFO  : 'fpga -state' command is executed.
09:43:27 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:43:27 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:43:27 INFO  : 'jtag frequency' command is executed.
09:43:27 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:43:27 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:43:27 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:43:27 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:43:27 INFO  : 'stop' command is executed.
09:43:28 INFO  : 'ps7_init' command is executed.
09:43:28 INFO  : 'ps7_post_config' command is executed.
09:43:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:43:28 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:43:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:43:30 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:43:30 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:43:30 INFO  : Memory regions updated for context APU
09:43:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:43:30 INFO  : 'con' command is executed.
09:43:30 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:43:30 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:45:03 INFO  : Disconnected from the channel tcfchan#23.
09:45:04 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:45:04 INFO  : 'fpga -state' command is executed.
09:45:04 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:45:04 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:45:04 INFO  : 'jtag frequency' command is executed.
09:45:04 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:45:04 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:45:04 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:45:04 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:45:04 INFO  : 'stop' command is executed.
09:45:05 INFO  : 'ps7_init' command is executed.
09:45:05 INFO  : 'ps7_post_config' command is executed.
09:45:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:45:05 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:45:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:45:07 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:45:07 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:45:07 INFO  : Memory regions updated for context APU
09:45:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:45:08 INFO  : 'con' command is executed.
09:45:08 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:45:08 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:49:17 INFO  : Disconnected from the channel tcfchan#24.
09:49:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:49:17 INFO  : 'fpga -state' command is executed.
09:49:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:49:18 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:49:18 INFO  : 'jtag frequency' command is executed.
09:49:18 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:49:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:49:18 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:49:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:49:18 INFO  : 'stop' command is executed.
09:49:19 INFO  : 'ps7_init' command is executed.
09:49:19 INFO  : 'ps7_post_config' command is executed.
09:49:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:49:19 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:49:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:49:22 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:49:22 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:49:22 INFO  : Memory regions updated for context APU
09:49:22 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:49:22 INFO  : 'con' command is executed.
09:49:22 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:49:22 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:53:18 INFO  : Disconnected from the channel tcfchan#25.
09:53:19 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:53:19 INFO  : 'fpga -state' command is executed.
09:53:19 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:53:19 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:53:19 INFO  : 'jtag frequency' command is executed.
09:53:19 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:53:19 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:53:19 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:53:19 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:53:19 INFO  : 'stop' command is executed.
09:53:20 INFO  : 'ps7_init' command is executed.
09:53:20 INFO  : 'ps7_post_config' command is executed.
09:53:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:53:20 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:53:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:53:22 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:53:22 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:53:23 INFO  : Memory regions updated for context APU
09:53:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:53:23 INFO  : 'con' command is executed.
09:53:23 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:53:23 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:54:01 INFO  : Disconnected from the channel tcfchan#26.
09:54:01 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:54:01 INFO  : 'fpga -state' command is executed.
09:54:01 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:54:02 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:54:02 INFO  : 'jtag frequency' command is executed.
09:54:02 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:54:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:54:02 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:54:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:54:02 INFO  : 'stop' command is executed.
09:54:03 INFO  : 'ps7_init' command is executed.
09:54:03 INFO  : 'ps7_post_config' command is executed.
09:54:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:54:03 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:54:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:54:05 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:54:05 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:54:05 INFO  : Memory regions updated for context APU
09:54:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:54:05 INFO  : 'con' command is executed.
09:54:05 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:54:05 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:56:15 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:56:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:56:33 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:56:57 INFO  : Disconnected from the channel tcfchan#27.
09:56:57 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:56:57 INFO  : 'fpga -state' command is executed.
09:56:57 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:56:57 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:56:57 INFO  : 'jtag frequency' command is executed.
09:56:57 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:56:58 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:56:58 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:56:58 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:56:58 INFO  : 'stop' command is executed.
09:56:59 INFO  : 'ps7_init' command is executed.
09:56:59 INFO  : 'ps7_post_config' command is executed.
09:56:59 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:56:59 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:56:59 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:57:01 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:57:01 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:57:01 INFO  : Memory regions updated for context APU
09:57:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:57:01 INFO  : 'con' command is executed.
09:57:01 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:57:01 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:58:30 INFO  : Disconnected from the channel tcfchan#28.
09:58:30 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:58:30 INFO  : 'fpga -state' command is executed.
09:58:30 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:58:31 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:58:31 INFO  : 'jtag frequency' command is executed.
09:58:31 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:58:31 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:58:31 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:58:31 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:58:31 INFO  : 'stop' command is executed.
09:58:32 INFO  : 'ps7_init' command is executed.
09:58:32 INFO  : 'ps7_post_config' command is executed.
09:58:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:58:32 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:58:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:58:34 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:58:34 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:58:34 INFO  : Memory regions updated for context APU
09:58:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:58:34 INFO  : 'con' command is executed.
09:58:34 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:58:34 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:04:37 INFO  : Disconnected from the channel tcfchan#29.
10:04:37 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:04:37 INFO  : 'fpga -state' command is executed.
10:04:37 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:04:37 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:04:37 INFO  : 'jtag frequency' command is executed.
10:04:37 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:04:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:04:38 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:04:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:04:38 INFO  : 'stop' command is executed.
10:04:39 INFO  : 'ps7_init' command is executed.
10:04:39 INFO  : 'ps7_post_config' command is executed.
10:04:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:04:39 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:04:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:04:41 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:04:41 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:04:41 INFO  : Memory regions updated for context APU
10:04:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:04:41 INFO  : 'con' command is executed.
10:04:41 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:04:41 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:05:07 INFO  : Disconnected from the channel tcfchan#30.
10:05:07 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:05:07 INFO  : 'fpga -state' command is executed.
10:05:07 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:05:07 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:05:07 INFO  : 'jtag frequency' command is executed.
10:05:07 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:05:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:05:07 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:05:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:05:07 INFO  : 'stop' command is executed.
10:05:09 INFO  : 'ps7_init' command is executed.
10:05:09 INFO  : 'ps7_post_config' command is executed.
10:05:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:05:09 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:05:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:05:11 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:05:11 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:05:11 INFO  : Memory regions updated for context APU
10:05:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:05:11 INFO  : 'con' command is executed.
10:05:11 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:05:11 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:06:01 INFO  : Disconnected from the channel tcfchan#31.
10:06:02 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:06:02 INFO  : 'fpga -state' command is executed.
10:06:02 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:06:02 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:06:02 INFO  : 'jtag frequency' command is executed.
10:06:02 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:06:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:06:02 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:06:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:06:02 INFO  : 'stop' command is executed.
10:06:03 INFO  : 'ps7_init' command is executed.
10:06:03 INFO  : 'ps7_post_config' command is executed.
10:06:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:03 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:06:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:06 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:06:06 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:06:06 INFO  : Memory regions updated for context APU
10:06:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:06 INFO  : 'con' command is executed.
10:06:06 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:06:06 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:08:19 INFO  : Disconnected from the channel tcfchan#32.
10:08:19 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:08:19 INFO  : 'fpga -state' command is executed.
10:08:19 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:08:19 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:08:19 INFO  : 'jtag frequency' command is executed.
10:08:19 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:08:20 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:08:20 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:08:20 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:08:20 INFO  : 'stop' command is executed.
10:08:21 INFO  : 'ps7_init' command is executed.
10:08:21 INFO  : 'ps7_post_config' command is executed.
10:08:21 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:08:21 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:08:21 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:08:23 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:08:23 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:08:23 INFO  : Memory regions updated for context APU
10:08:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:08:23 INFO  : 'con' command is executed.
10:08:23 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:08:23 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:19:31 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:19:31 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:19:48 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:20:53 INFO  : Disconnected from the channel tcfchan#33.
18:20:54 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:20:54 INFO  : 'fpga -state' command is executed.
18:20:54 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:20:54 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:20:54 INFO  : 'jtag frequency' command is executed.
18:20:54 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:20:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:20:54 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:20:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:20:54 INFO  : 'stop' command is executed.
18:20:55 INFO  : 'ps7_init' command is executed.
18:20:55 INFO  : 'ps7_post_config' command is executed.
18:20:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:20:55 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:20:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:20:57 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:20:57 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:20:57 INFO  : Memory regions updated for context APU
18:20:57 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:20:57 INFO  : 'con' command is executed.
18:20:57 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:20:57 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:21:33 INFO  : Disconnected from the channel tcfchan#34.
18:21:33 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:21:33 INFO  : 'fpga -state' command is executed.
18:21:33 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:21:33 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:21:33 INFO  : 'jtag frequency' command is executed.
18:21:34 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:21:34 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:21:34 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:21:34 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:21:34 INFO  : 'stop' command is executed.
18:21:35 INFO  : 'ps7_init' command is executed.
18:21:35 INFO  : 'ps7_post_config' command is executed.
18:21:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:21:35 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:21:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:21:37 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:21:37 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:21:37 INFO  : Memory regions updated for context APU
18:21:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:21:37 INFO  : 'con' command is executed.
18:21:37 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:21:37 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:23:13 INFO  : Disconnected from the channel tcfchan#35.
18:23:13 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:23:13 INFO  : 'fpga -state' command is executed.
18:23:13 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:23:13 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:23:13 INFO  : 'jtag frequency' command is executed.
18:23:13 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:23:13 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:23:13 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:23:13 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:23:13 INFO  : 'stop' command is executed.
18:23:14 INFO  : 'ps7_init' command is executed.
18:23:14 INFO  : 'ps7_post_config' command is executed.
18:23:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:23:15 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:23:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:23:17 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:23:17 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:23:17 INFO  : Memory regions updated for context APU
18:23:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:23:17 INFO  : 'con' command is executed.
18:23:17 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:23:17 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:28:16 INFO  : Disconnected from the channel tcfchan#36.
18:28:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:28:16 INFO  : 'fpga -state' command is executed.
18:28:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:28:16 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:28:16 INFO  : 'jtag frequency' command is executed.
18:28:16 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:28:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:28:17 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:28:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:28:17 INFO  : 'stop' command is executed.
18:28:18 INFO  : 'ps7_init' command is executed.
18:28:18 INFO  : 'ps7_post_config' command is executed.
18:28:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:28:18 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:28:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:28:21 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:28:21 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:28:21 INFO  : Memory regions updated for context APU
18:28:21 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:28:21 INFO  : 'con' command is executed.
18:28:21 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:28:21 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:57:27 INFO  : Disconnected from the channel tcfchan#37.
18:57:27 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:57:27 INFO  : 'fpga -state' command is executed.
18:57:27 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:57:28 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:57:28 INFO  : 'jtag frequency' command is executed.
18:57:28 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:57:28 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:57:28 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:57:28 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:57:28 INFO  : 'stop' command is executed.
18:57:29 INFO  : 'ps7_init' command is executed.
18:57:29 INFO  : 'ps7_post_config' command is executed.
18:57:29 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:57:29 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:57:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:57:32 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:57:32 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:57:32 INFO  : Memory regions updated for context APU
18:57:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:57:32 INFO  : 'con' command is executed.
18:57:32 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:57:32 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
19:00:50 INFO  : Disconnected from the channel tcfchan#38.
19:00:50 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:00:50 INFO  : 'fpga -state' command is executed.
19:00:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:00:50 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:00:50 INFO  : 'jtag frequency' command is executed.
19:00:50 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:00:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:00:51 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:00:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:00:51 INFO  : 'stop' command is executed.
19:00:52 INFO  : 'ps7_init' command is executed.
19:00:52 INFO  : 'ps7_post_config' command is executed.
19:00:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:00:52 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:00:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:00:54 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:00:54 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

19:00:54 INFO  : Memory regions updated for context APU
19:00:54 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:00:54 INFO  : 'con' command is executed.
19:00:54 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:00:54 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
19:06:02 INFO  : Disconnected from the channel tcfchan#39.
19:06:02 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:06:02 INFO  : 'fpga -state' command is executed.
19:06:02 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:06:03 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:06:03 INFO  : 'jtag frequency' command is executed.
19:06:03 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:06:03 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:06:03 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:06:03 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:06:03 INFO  : 'stop' command is executed.
19:06:04 INFO  : 'ps7_init' command is executed.
19:06:04 INFO  : 'ps7_post_config' command is executed.
19:06:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:06:04 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:06:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:06:06 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:06:06 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

19:06:06 INFO  : Memory regions updated for context APU
19:06:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:06:06 INFO  : 'con' command is executed.
19:06:06 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:06:06 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:19:49 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:19:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:20:07 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:20:28 INFO  : Disconnected from the channel tcfchan#40.
08:20:28 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:20:28 INFO  : 'fpga -state' command is executed.
08:20:28 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:20:28 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:20:28 INFO  : 'jtag frequency' command is executed.
08:20:28 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:20:28 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:20:28 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:20:29 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:20:29 INFO  : 'stop' command is executed.
08:20:30 INFO  : 'ps7_init' command is executed.
08:20:30 INFO  : 'ps7_post_config' command is executed.
08:20:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:20:30 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:20:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:20:32 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:20:32 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:20:32 INFO  : Memory regions updated for context APU
08:20:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:20:32 INFO  : 'con' command is executed.
08:20:32 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:20:32 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:29:23 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:29:23 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:29:40 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:35:24 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:35:24 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:35:41 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:38:38 INFO  : Disconnected from the channel tcfchan#41.
08:38:38 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:38:38 INFO  : 'fpga -state' command is executed.
08:38:38 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:38:39 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:38:39 INFO  : 'jtag frequency' command is executed.
08:38:39 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:38:39 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:38:39 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:38:39 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:38:39 INFO  : 'stop' command is executed.
08:38:40 INFO  : 'ps7_init' command is executed.
08:38:40 INFO  : 'ps7_post_config' command is executed.
08:38:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:38:40 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:38:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:38:42 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:38:42 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:38:42 INFO  : Memory regions updated for context APU
08:38:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:38:42 INFO  : 'con' command is executed.
08:38:42 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:38:42 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:39:38 INFO  : Disconnected from the channel tcfchan#42.
08:39:39 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:39:39 INFO  : 'fpga -state' command is executed.
08:39:39 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:39:39 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:39:39 INFO  : 'jtag frequency' command is executed.
08:39:39 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:39:39 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:39:39 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:39:39 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:39:39 INFO  : 'stop' command is executed.
08:39:40 INFO  : 'ps7_init' command is executed.
08:39:40 INFO  : 'ps7_post_config' command is executed.
08:39:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:39:40 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:39:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:39:43 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:39:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:39:43 INFO  : Memory regions updated for context APU
08:39:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:39:43 INFO  : 'con' command is executed.
08:39:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:39:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:40:29 INFO  : Disconnected from the channel tcfchan#43.
08:40:29 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:40:29 INFO  : 'fpga -state' command is executed.
08:40:29 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:40:29 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:40:29 INFO  : 'jtag frequency' command is executed.
08:40:29 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:40:29 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:40:29 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:40:29 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:40:29 INFO  : 'stop' command is executed.
08:40:30 INFO  : 'ps7_init' command is executed.
08:40:30 INFO  : 'ps7_post_config' command is executed.
08:40:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:40:31 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:40:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:40:33 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:40:33 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:40:33 INFO  : Memory regions updated for context APU
08:40:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:40:33 INFO  : 'con' command is executed.
08:40:33 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:40:33 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:13:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:14:10 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:14:11 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:14:27 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:23:37 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:23:38 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:23:54 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:25:45 INFO  : Disconnected from the channel tcfchan#44.
09:25:45 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:25:45 INFO  : 'fpga -state' command is executed.
09:25:45 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:25:46 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:25:46 INFO  : 'jtag frequency' command is executed.
09:25:46 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:25:46 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:25:46 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:25:46 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:25:46 INFO  : 'stop' command is executed.
09:25:47 INFO  : 'ps7_init' command is executed.
09:25:47 INFO  : 'ps7_post_config' command is executed.
09:25:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:25:47 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:25:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:25:49 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:25:49 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:25:49 INFO  : Memory regions updated for context APU
09:25:49 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:25:49 INFO  : 'con' command is executed.
09:25:49 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:25:49 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:29:57 INFO  : Disconnected from the channel tcfchan#45.
09:29:57 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:29:57 INFO  : 'fpga -state' command is executed.
09:29:57 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:29:57 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:29:57 INFO  : 'jtag frequency' command is executed.
09:29:57 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:29:57 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:29:57 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:29:57 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:29:57 INFO  : 'stop' command is executed.
09:29:58 INFO  : 'ps7_init' command is executed.
09:29:59 INFO  : 'ps7_post_config' command is executed.
09:29:59 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:29:59 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:29:59 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:30:01 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:30:01 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:30:01 INFO  : Memory regions updated for context APU
09:30:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:30:01 INFO  : 'con' command is executed.
09:30:01 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:30:01 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:38:26 INFO  : Disconnected from the channel tcfchan#46.
09:38:26 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:38:26 INFO  : 'fpga -state' command is executed.
09:38:26 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:38:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:38:26 INFO  : 'jtag frequency' command is executed.
09:38:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:38:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:38:26 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:38:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:38:26 INFO  : 'stop' command is executed.
09:38:27 INFO  : 'ps7_init' command is executed.
09:38:27 INFO  : 'ps7_post_config' command is executed.
09:38:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:38:27 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:38:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:38:30 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:38:30 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:38:30 INFO  : Memory regions updated for context APU
09:38:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:38:30 INFO  : 'con' command is executed.
09:38:30 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:38:30 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:41:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:41:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:41:34 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:41:50 INFO  : Disconnected from the channel tcfchan#47.
09:41:50 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:41:50 INFO  : 'fpga -state' command is executed.
09:41:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:41:50 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:41:50 INFO  : 'jtag frequency' command is executed.
09:41:50 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:41:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:41:50 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:41:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:41:51 INFO  : 'stop' command is executed.
09:41:51 INFO  : 'ps7_init' command is executed.
09:41:51 INFO  : 'ps7_post_config' command is executed.
09:41:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:41:52 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:41:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:41:54 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:41:54 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:41:54 INFO  : Memory regions updated for context APU
09:41:54 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:41:54 INFO  : 'con' command is executed.
09:41:54 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:41:54 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:50:17 INFO  : Disconnected from the channel tcfchan#48.
09:50:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:50:17 INFO  : 'fpga -state' command is executed.
09:50:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:50:17 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:50:17 INFO  : 'jtag frequency' command is executed.
09:50:17 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:50:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:50:18 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:50:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:50:18 INFO  : 'stop' command is executed.
09:50:19 INFO  : 'ps7_init' command is executed.
09:50:19 INFO  : 'ps7_post_config' command is executed.
09:50:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:50:19 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:50:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:50:21 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:50:21 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:50:21 INFO  : Memory regions updated for context APU
09:50:21 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:50:21 INFO  : 'con' command is executed.
09:50:21 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:50:21 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:53:44 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:53:44 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:54:01 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:54:12 INFO  : Disconnected from the channel tcfchan#49.
09:54:12 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:54:12 INFO  : 'fpga -state' command is executed.
09:54:12 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:54:12 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:54:12 INFO  : 'jtag frequency' command is executed.
09:54:12 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:54:12 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:54:12 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:54:12 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:54:12 INFO  : 'stop' command is executed.
09:54:13 INFO  : 'ps7_init' command is executed.
09:54:13 INFO  : 'ps7_post_config' command is executed.
09:54:13 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:54:13 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:54:13 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:54:16 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:54:16 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:54:16 INFO  : Memory regions updated for context APU
09:54:16 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:54:16 INFO  : 'con' command is executed.
09:54:16 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:54:16 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:57:48 INFO  : Disconnected from the channel tcfchan#50.
09:57:48 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:57:48 INFO  : 'fpga -state' command is executed.
09:57:48 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:57:49 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:57:49 INFO  : 'jtag frequency' command is executed.
09:57:49 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:57:49 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:57:49 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:57:49 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:57:49 INFO  : 'stop' command is executed.
09:57:50 INFO  : 'ps7_init' command is executed.
09:57:50 INFO  : 'ps7_post_config' command is executed.
09:57:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:57:50 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:57:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:57:52 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:57:52 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:57:52 INFO  : Memory regions updated for context APU
09:57:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:57:53 INFO  : 'con' command is executed.
09:57:53 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:57:53 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:58:56 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:58:56 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:59:13 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:59:20 INFO  : Disconnected from the channel tcfchan#51.
09:59:20 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:59:20 INFO  : 'fpga -state' command is executed.
09:59:20 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:59:20 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:59:20 INFO  : 'jtag frequency' command is executed.
09:59:20 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:59:20 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:59:20 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:59:20 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:59:20 INFO  : 'stop' command is executed.
09:59:21 INFO  : 'ps7_init' command is executed.
09:59:21 INFO  : 'ps7_post_config' command is executed.
09:59:21 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:59:21 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:59:21 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:59:24 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:59:24 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:59:24 INFO  : Memory regions updated for context APU
09:59:24 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:59:24 INFO  : 'con' command is executed.
09:59:24 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:59:24 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:05:59 INFO  : Disconnected from the channel tcfchan#52.
10:06:00 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:06:00 INFO  : 'fpga -state' command is executed.
10:06:00 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:06:00 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:06:00 INFO  : 'jtag frequency' command is executed.
10:06:00 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:06:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:06:00 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:06:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:06:00 INFO  : 'stop' command is executed.
10:06:01 INFO  : 'ps7_init' command is executed.
10:06:01 INFO  : 'ps7_post_config' command is executed.
10:06:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:01 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:06:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:04 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:06:04 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:06:04 INFO  : Memory regions updated for context APU
10:06:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:06:04 INFO  : 'con' command is executed.
10:06:04 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:06:04 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:13:32 INFO  : Disconnected from the channel tcfchan#53.
10:13:32 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:13:33 INFO  : 'fpga -state' command is executed.
10:13:33 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:13:33 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:13:33 INFO  : 'jtag frequency' command is executed.
10:13:33 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:13:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:13:33 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:13:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:13:33 INFO  : 'stop' command is executed.
10:13:34 INFO  : 'ps7_init' command is executed.
10:13:34 INFO  : 'ps7_post_config' command is executed.
10:13:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:13:34 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:13:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:13:37 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:13:37 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:13:37 INFO  : Memory regions updated for context APU
10:13:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:13:37 INFO  : 'con' command is executed.
10:13:37 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:13:37 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:14:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:14:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:15:08 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
10:15:15 INFO  : Disconnected from the channel tcfchan#54.
10:15:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:15:16 INFO  : 'fpga -state' command is executed.
10:15:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:15:16 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:15:16 INFO  : 'jtag frequency' command is executed.
10:15:16 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:15:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:15:16 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:15:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:15:16 INFO  : 'stop' command is executed.
10:15:17 INFO  : 'ps7_init' command is executed.
10:15:17 INFO  : 'ps7_post_config' command is executed.
10:15:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:15:17 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:15:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:15:19 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:15:19 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:15:19 INFO  : Memory regions updated for context APU
10:15:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:15:20 INFO  : 'con' command is executed.
10:15:20 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:15:20 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:17:13 INFO  : Disconnected from the channel tcfchan#55.
10:17:13 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:17:13 INFO  : 'fpga -state' command is executed.
10:17:13 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:17:13 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:17:13 INFO  : 'jtag frequency' command is executed.
10:17:13 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:17:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:17:14 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:17:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:17:14 INFO  : 'stop' command is executed.
10:17:15 INFO  : 'ps7_init' command is executed.
10:17:15 INFO  : 'ps7_post_config' command is executed.
10:17:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:17:15 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:17:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:17:17 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:17:17 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:17:17 INFO  : Memory regions updated for context APU
10:17:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:17:17 INFO  : 'con' command is executed.
10:17:17 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:17:17 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:20:11 INFO  : Disconnected from the channel tcfchan#56.
10:20:11 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:20:11 INFO  : 'fpga -state' command is executed.
10:20:11 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:20:11 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:20:11 INFO  : 'jtag frequency' command is executed.
10:20:11 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:20:11 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:20:11 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:20:11 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:20:12 INFO  : 'stop' command is executed.
10:20:13 INFO  : 'ps7_init' command is executed.
10:20:13 INFO  : 'ps7_post_config' command is executed.
10:20:13 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:20:13 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:20:13 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:20:15 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:20:15 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:20:16 INFO  : Memory regions updated for context APU
10:20:16 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:20:16 INFO  : 'con' command is executed.
10:20:16 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:20:16 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:22:41 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:22:41 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:22:59 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
10:23:07 INFO  : Disconnected from the channel tcfchan#57.
10:23:07 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:23:07 INFO  : 'fpga -state' command is executed.
10:23:07 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:23:07 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:23:07 INFO  : 'jtag frequency' command is executed.
10:23:07 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:23:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:23:07 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:23:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:23:07 INFO  : 'stop' command is executed.
10:23:08 INFO  : 'ps7_init' command is executed.
10:23:08 INFO  : 'ps7_post_config' command is executed.
10:23:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:23:08 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:23:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:23:11 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:23:11 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:23:11 INFO  : Memory regions updated for context APU
10:23:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:23:11 INFO  : 'con' command is executed.
10:23:11 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:23:11 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:37:31 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:37:31 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:37:48 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
10:46:22 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:46:22 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:46:39 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
10:47:17 INFO  : Disconnected from the channel tcfchan#58.
10:47:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:47:17 INFO  : 'fpga -state' command is executed.
10:47:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:47:17 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:47:17 INFO  : 'jtag frequency' command is executed.
10:47:17 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:47:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:47:17 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:47:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:47:17 INFO  : 'stop' command is executed.
10:47:18 INFO  : 'ps7_init' command is executed.
10:47:18 INFO  : 'ps7_post_config' command is executed.
10:47:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:47:18 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:47:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:47:21 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:47:21 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:47:21 INFO  : Memory regions updated for context APU
10:47:21 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:47:21 INFO  : 'con' command is executed.
10:47:21 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:47:21 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:47:51 INFO  : Disconnected from the channel tcfchan#59.
10:47:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:47:51 INFO  : 'fpga -state' command is executed.
10:47:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:47:51 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:47:51 INFO  : 'jtag frequency' command is executed.
10:47:51 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:47:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:47:51 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:47:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:47:51 INFO  : 'stop' command is executed.
10:47:52 INFO  : 'ps7_init' command is executed.
10:47:52 INFO  : 'ps7_post_config' command is executed.
10:47:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:47:52 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:47:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:47:55 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:47:55 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:47:55 INFO  : Memory regions updated for context APU
10:47:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:47:55 INFO  : 'con' command is executed.
10:47:55 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:47:55 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:51:58 INFO  : Disconnected from the channel tcfchan#60.
10:51:58 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:51:58 INFO  : 'fpga -state' command is executed.
10:51:58 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:51:59 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:51:59 INFO  : 'jtag frequency' command is executed.
10:51:59 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:51:59 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:51:59 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:51:59 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:51:59 INFO  : 'stop' command is executed.
10:52:00 INFO  : 'ps7_init' command is executed.
10:52:00 INFO  : 'ps7_post_config' command is executed.
10:52:00 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:52:00 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:52:00 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:52:02 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:52:02 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:52:02 INFO  : Memory regions updated for context APU
10:52:02 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:52:02 INFO  : 'con' command is executed.
10:52:02 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:52:02 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:53:21 INFO  : Disconnected from the channel tcfchan#61.
10:53:21 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:53:21 INFO  : 'fpga -state' command is executed.
10:53:21 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:53:22 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:53:22 INFO  : 'jtag frequency' command is executed.
10:53:22 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:53:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:53:22 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:53:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:53:22 INFO  : 'stop' command is executed.
10:53:23 INFO  : 'ps7_init' command is executed.
10:53:23 INFO  : 'ps7_post_config' command is executed.
10:53:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:53:23 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:53:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:53:25 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:53:25 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:53:25 INFO  : Memory regions updated for context APU
10:53:25 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:53:26 INFO  : 'con' command is executed.
10:53:26 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:53:26 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:54:49 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:54:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:55:06 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
10:55:13 INFO  : Disconnected from the channel tcfchan#62.
10:55:13 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:55:13 INFO  : 'fpga -state' command is executed.
10:55:13 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:55:13 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:55:13 INFO  : 'jtag frequency' command is executed.
10:55:13 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:55:13 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:55:13 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:55:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:55:14 INFO  : 'stop' command is executed.
10:55:15 INFO  : 'ps7_init' command is executed.
10:55:15 INFO  : 'ps7_post_config' command is executed.
10:55:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:15 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:55:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:17 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:55:17 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:55:17 INFO  : Memory regions updated for context APU
10:55:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:17 INFO  : 'con' command is executed.
10:55:17 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:55:17 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:55:25 INFO  : Disconnected from the channel tcfchan#63.
10:55:26 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:55:26 INFO  : 'fpga -state' command is executed.
10:55:26 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:55:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:55:26 INFO  : 'jtag frequency' command is executed.
10:55:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:55:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:55:26 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:55:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:55:26 INFO  : 'stop' command is executed.
10:55:27 INFO  : 'ps7_init' command is executed.
10:55:27 INFO  : 'ps7_post_config' command is executed.
10:55:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:27 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:55:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:30 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:55:30 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

10:55:30 INFO  : Memory regions updated for context APU
10:55:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:30 INFO  : 'con' command is executed.
10:55:30 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:55:30 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:59:59 INFO  : Disconnected from the channel tcfchan#64.
10:59:59 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:59:59 INFO  : 'fpga -state' command is executed.
10:59:59 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
11:00:00 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
11:00:00 INFO  : 'jtag frequency' command is executed.
11:00:00 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
11:00:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:00:00 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
11:00:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:00:00 INFO  : 'stop' command is executed.
11:00:01 INFO  : 'ps7_init' command is executed.
11:00:01 INFO  : 'ps7_post_config' command is executed.
11:00:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:00:01 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
11:00:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:00:03 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
11:00:03 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

11:00:03 INFO  : Memory regions updated for context APU
11:00:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:00:03 INFO  : 'con' command is executed.
11:00:03 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

11:00:03 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
11:01:10 INFO  : Disconnected from the channel tcfchan#65.
11:01:10 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
11:01:10 INFO  : 'fpga -state' command is executed.
11:01:10 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
11:01:10 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
11:01:10 INFO  : 'jtag frequency' command is executed.
11:01:10 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
11:01:10 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:01:10 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
11:01:10 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:01:10 INFO  : 'stop' command is executed.
11:01:11 INFO  : 'ps7_init' command is executed.
11:01:11 INFO  : 'ps7_post_config' command is executed.
11:01:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:01:11 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
11:01:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:01:14 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
11:01:14 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

11:01:14 INFO  : Memory regions updated for context APU
11:01:14 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:01:14 INFO  : 'con' command is executed.
11:01:14 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

11:01:14 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
11:01:39 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
11:01:39 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
11:01:56 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
11:02:04 INFO  : Disconnected from the channel tcfchan#66.
11:02:04 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
11:02:04 INFO  : 'fpga -state' command is executed.
11:02:04 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
11:02:05 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
11:02:05 INFO  : 'jtag frequency' command is executed.
11:02:05 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
11:02:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:02:05 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
11:02:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:02:05 INFO  : 'stop' command is executed.
11:02:06 INFO  : 'ps7_init' command is executed.
11:02:06 INFO  : 'ps7_post_config' command is executed.
11:02:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:02:06 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
11:02:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:02:08 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
11:02:08 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

11:02:08 INFO  : Memory regions updated for context APU
11:02:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:02:08 INFO  : 'con' command is executed.
11:02:08 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

11:02:08 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
11:02:59 INFO  : Disconnected from the channel tcfchan#67.
11:02:59 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
11:02:59 INFO  : 'fpga -state' command is executed.
11:02:59 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
11:02:59 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
11:02:59 INFO  : 'jtag frequency' command is executed.
11:02:59 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
11:02:59 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:02:59 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
11:02:59 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
11:02:59 INFO  : 'stop' command is executed.
11:03:00 INFO  : 'ps7_init' command is executed.
11:03:00 INFO  : 'ps7_post_config' command is executed.
11:03:00 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:03:00 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
11:03:00 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:03:03 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
11:03:03 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

11:03:03 INFO  : Memory regions updated for context APU
11:03:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
11:03:03 INFO  : 'con' command is executed.
11:03:03 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

11:03:03 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:41:34 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:41:34 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:41:51 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
17:42:06 INFO  : Disconnected from the channel tcfchan#68.
17:42:06 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:42:06 INFO  : 'fpga -state' command is executed.
17:42:06 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:42:07 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:42:07 INFO  : 'jtag frequency' command is executed.
17:42:07 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:42:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:42:07 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:42:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:42:07 INFO  : 'stop' command is executed.
17:42:08 INFO  : 'ps7_init' command is executed.
17:42:08 INFO  : 'ps7_post_config' command is executed.
17:42:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:08 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:42:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:10 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:42:10 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:42:10 INFO  : Memory regions updated for context APU
17:42:10 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:10 INFO  : 'con' command is executed.
17:42:10 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:42:10 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:42:26 INFO  : Disconnected from the channel tcfchan#69.
17:42:26 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:42:26 INFO  : 'fpga -state' command is executed.
17:42:26 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:42:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:42:26 INFO  : 'jtag frequency' command is executed.
17:42:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:42:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:42:26 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:42:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:42:26 INFO  : 'stop' command is executed.
17:42:27 INFO  : 'ps7_init' command is executed.
17:42:27 INFO  : 'ps7_post_config' command is executed.
17:42:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:28 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:42:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:30 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:42:30 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:42:30 INFO  : Memory regions updated for context APU
17:42:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:30 INFO  : 'con' command is executed.
17:42:30 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:42:30 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:42:48 INFO  : Disconnected from the channel tcfchan#70.
17:42:48 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:42:48 INFO  : 'fpga -state' command is executed.
17:42:48 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:42:48 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:42:48 INFO  : 'jtag frequency' command is executed.
17:42:48 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:42:48 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:42:49 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:42:49 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:42:49 INFO  : 'stop' command is executed.
17:42:50 INFO  : 'ps7_init' command is executed.
17:42:50 INFO  : 'ps7_post_config' command is executed.
17:42:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:50 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:42:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:52 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:42:52 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:42:52 INFO  : Memory regions updated for context APU
17:42:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:42:52 INFO  : 'con' command is executed.
17:42:52 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:42:52 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:56:10 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:56:10 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:56:27 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
17:57:00 INFO  : Disconnected from the channel tcfchan#71.
17:57:00 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:57:00 INFO  : 'fpga -state' command is executed.
17:57:00 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:57:00 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:57:00 INFO  : 'jtag frequency' command is executed.
17:57:00 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:57:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:57:01 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:57:01 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:57:01 INFO  : 'stop' command is executed.
17:57:02 INFO  : 'ps7_init' command is executed.
17:57:02 INFO  : 'ps7_post_config' command is executed.
17:57:02 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:57:02 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:57:02 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:57:04 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:57:04 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:57:04 INFO  : Memory regions updated for context APU
17:57:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:57:04 INFO  : 'con' command is executed.
17:57:04 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:57:04 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:57:52 INFO  : Disconnected from the channel tcfchan#72.
17:57:52 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:57:52 INFO  : 'fpga -state' command is executed.
17:57:52 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:57:52 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:57:52 INFO  : 'jtag frequency' command is executed.
17:57:52 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:57:52 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:57:52 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:57:52 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:57:52 INFO  : 'stop' command is executed.
17:57:53 INFO  : 'ps7_init' command is executed.
17:57:53 INFO  : 'ps7_post_config' command is executed.
17:57:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:57:53 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:57:54 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:57:56 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:57:56 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:57:56 INFO  : Memory regions updated for context APU
17:57:56 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:57:56 INFO  : 'con' command is executed.
17:57:56 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:57:56 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:58:37 INFO  : Disconnected from the channel tcfchan#73.
17:58:37 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:58:37 INFO  : 'fpga -state' command is executed.
17:58:37 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:58:37 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:58:37 INFO  : 'jtag frequency' command is executed.
17:58:37 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:58:37 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:58:37 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:58:37 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:58:37 INFO  : 'stop' command is executed.
17:58:39 INFO  : 'ps7_init' command is executed.
17:58:39 INFO  : 'ps7_post_config' command is executed.
17:58:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:58:39 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:58:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:58:41 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:58:41 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:58:41 INFO  : Memory regions updated for context APU
17:58:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:58:41 INFO  : 'con' command is executed.
17:58:41 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:58:41 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:03:31 INFO  : Disconnected from the channel tcfchan#74.
18:03:31 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:03:31 INFO  : 'fpga -state' command is executed.
18:03:31 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:03:31 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:03:31 INFO  : 'jtag frequency' command is executed.
18:03:31 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:03:31 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:03:31 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:03:31 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:03:31 INFO  : 'stop' command is executed.
18:03:32 INFO  : 'ps7_init' command is executed.
18:03:32 INFO  : 'ps7_post_config' command is executed.
18:03:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:03:32 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:03:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:03:35 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:03:35 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:03:35 INFO  : Memory regions updated for context APU
18:03:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:03:35 INFO  : 'con' command is executed.
18:03:35 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:03:35 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:08:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:08:50 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:09:07 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:09:16 INFO  : Disconnected from the channel tcfchan#75.
18:09:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:09:16 INFO  : 'fpga -state' command is executed.
18:09:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:09:16 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:09:16 INFO  : 'jtag frequency' command is executed.
18:09:16 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:09:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:09:16 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:09:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:09:16 INFO  : 'stop' command is executed.
18:09:17 INFO  : 'ps7_init' command is executed.
18:09:17 INFO  : 'ps7_post_config' command is executed.
18:09:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:09:17 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:09:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:09:20 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:09:20 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:09:20 INFO  : Memory regions updated for context APU
18:09:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:09:20 INFO  : 'con' command is executed.
18:09:20 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:09:20 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:15:04 INFO  : Disconnected from the channel tcfchan#76.
18:15:05 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:15:05 INFO  : 'fpga -state' command is executed.
18:15:05 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:15:05 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:15:05 INFO  : 'jtag frequency' command is executed.
18:15:05 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:15:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:15:05 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:15:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:15:05 INFO  : 'stop' command is executed.
18:15:06 INFO  : 'ps7_init' command is executed.
18:15:06 INFO  : 'ps7_post_config' command is executed.
18:15:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:15:06 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:15:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:15:09 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:15:09 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:15:09 INFO  : Memory regions updated for context APU
18:15:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:15:09 INFO  : 'con' command is executed.
18:15:09 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:15:09 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:18:01 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:18:01 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:18:18 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:18:25 INFO  : Disconnected from the channel tcfchan#77.
18:18:25 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:18:25 INFO  : 'fpga -state' command is executed.
18:18:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:18:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:18:26 INFO  : 'jtag frequency' command is executed.
18:18:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:18:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:18:26 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:18:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:18:26 INFO  : 'stop' command is executed.
18:18:27 INFO  : 'ps7_init' command is executed.
18:18:27 INFO  : 'ps7_post_config' command is executed.
18:18:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:18:27 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:18:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:18:29 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:18:29 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:18:29 INFO  : Memory regions updated for context APU
18:18:29 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:18:29 INFO  : 'con' command is executed.
18:18:29 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:18:29 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:18:38 INFO  : Disconnected from the channel tcfchan#78.
18:18:38 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:18:38 INFO  : 'fpga -state' command is executed.
18:18:38 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:18:38 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:18:38 INFO  : 'jtag frequency' command is executed.
18:18:38 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:18:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:18:38 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:18:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:18:38 INFO  : 'stop' command is executed.
18:18:39 INFO  : 'ps7_init' command is executed.
18:18:40 INFO  : 'ps7_post_config' command is executed.
18:18:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:18:40 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:18:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:18:42 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:18:42 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:18:42 INFO  : Memory regions updated for context APU
18:18:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:18:42 INFO  : 'con' command is executed.
18:18:42 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:18:42 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
19:30:14 INFO  : Disconnected from the channel tcfchan#79.
19:30:15 ERROR : Unexpected error while parsing XMD response : com.google.gson.JsonSyntaxException: com.google.gson.stream.MalformedJsonException: invalid number or unquoted string near 
07:38:55 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
07:38:56 INFO  : XSDB server has started successfully.
07:38:57 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
07:38:59 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
07:39:01 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1470116206000,  Project:1469691224000
07:39:01 INFO  : The hardware specification for project 'system_design_wrapper_hw_platform_0' is different from /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
07:39:01 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
07:39:08 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
07:39:09 INFO  : 
07:39:10 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
07:39:11 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
07:39:12 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
07:39:13 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
07:39:13 INFO  : Clearing existing target manager status.
07:40:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:40:24 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:40:43 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:40:43 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
07:41:00 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
07:41:23 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
07:41:23 INFO  : 'fpga -state' command is executed.
07:41:23 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:41:23 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
07:41:23 INFO  : 'jtag frequency' command is executed.
07:41:23 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
07:41:23 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:41:24 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
07:41:24 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:41:24 INFO  : 'stop' command is executed.
07:41:25 INFO  : 'ps7_init' command is executed.
07:41:25 INFO  : 'ps7_post_config' command is executed.
07:41:25 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:41:25 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
07:41:25 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:41:27 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
07:41:27 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

07:41:27 INFO  : Memory regions updated for context APU
07:41:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:41:27 INFO  : 'con' command is executed.
07:41:27 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

07:41:27 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:42:55 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1470120015000,  Project:1470116206000
08:42:55 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
08:42:59 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
08:43:05 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
08:43:06 INFO  : 
08:43:07 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
08:43:08 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
08:43:09 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
08:43:09 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
08:43:09 INFO  : Clearing existing target manager status.
08:44:07 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:44:07 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:44:24 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:44:40 INFO  : Disconnected from the channel tcfchan#1.
08:44:41 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:44:41 INFO  : 'fpga -state' command is executed.
08:44:41 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:44:41 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:44:41 INFO  : 'jtag frequency' command is executed.
08:44:41 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:44:41 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:44:41 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:44:41 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:44:41 INFO  : 'stop' command is executed.
08:44:42 INFO  : 'ps7_init' command is executed.
08:44:42 INFO  : 'ps7_post_config' command is executed.
08:44:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:44:42 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:44:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:44:45 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:44:45 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:44:45 INFO  : Memory regions updated for context APU
08:44:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:44:45 INFO  : 'con' command is executed.
08:44:45 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:44:45 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:59:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:59:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:59:34 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:01:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:01:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:01:33 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:08:58 INFO  : Disconnected from the channel tcfchan#2.
09:08:58 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:08:58 INFO  : 'fpga -state' command is executed.
09:08:58 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:08:58 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:08:58 INFO  : 'jtag frequency' command is executed.
09:08:58 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:08:58 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:08:58 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:08:58 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:08:58 INFO  : 'stop' command is executed.
09:08:59 INFO  : 'ps7_init' command is executed.
09:08:59 INFO  : 'ps7_post_config' command is executed.
09:08:59 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:08:59 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:09:00 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:09:02 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:09:02 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:09:02 INFO  : Memory regions updated for context APU
09:09:02 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:09:02 INFO  : 'con' command is executed.
09:09:02 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:09:02 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
12:02:00 INFO  : Disconnected from the channel tcfchan#3.
12:02:01 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
12:02:01 INFO  : 'fpga -state' command is executed.
12:02:01 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
12:02:01 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
12:02:01 INFO  : 'jtag frequency' command is executed.
12:02:01 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
12:02:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:02:02 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
12:02:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
12:02:02 INFO  : 'stop' command is executed.
12:02:03 INFO  : 'ps7_init' command is executed.
12:02:03 INFO  : 'ps7_post_config' command is executed.
12:02:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:02:03 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
12:02:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:02:04 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Mem-Test_FASEC/Debug/Mem-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
12:02:04 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Mem-Test_FASEC/Debug/Mem-Test_FASEC.elf
----------------End of Script----------------

12:02:04 INFO  : Memory regions updated for context APU
12:02:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
12:02:04 INFO  : 'con' command is executed.
12:02:04 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

12:02:04 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_mem-test_fasec.elf.tcl'
08:52:13 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:52:13 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:52:30 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:53:32 INFO  : Disconnected from the channel tcfchan#4.
08:53:33 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:53:33 INFO  : 'fpga -state' command is executed.
08:53:33 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:53:33 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:53:33 INFO  : 'jtag frequency' command is executed.
08:53:33 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:53:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:53:33 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:53:33 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:53:33 INFO  : 'stop' command is executed.
08:53:34 INFO  : 'ps7_init' command is executed.
08:53:34 INFO  : 'ps7_post_config' command is executed.
08:53:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:53:34 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:53:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:53:37 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:53:37 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:53:37 INFO  : Memory regions updated for context APU
08:53:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:53:37 INFO  : 'con' command is executed.
08:53:37 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:53:37 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
10:16:45 INFO  : Disconnected from the channel tcfchan#5.
10:16:50 ERROR : Unexpected error while parsing XMD response : com.google.gson.JsonSyntaxException: com.google.gson.stream.MalformedJsonException: invalid number or unquoted string near 
09:09:13 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
09:09:15 INFO  : XSDB server has started successfully.
09:09:16 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
09:09:16 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
09:04:25 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
09:04:26 INFO  : XSDB server has started successfully.
09:04:32 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
09:04:34 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
09:04:34 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1472108558000,  Project:1470120015000
09:04:34 INFO  : The hardware specification for project 'system_design_wrapper_hw_platform_0' is different from /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
09:04:34 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
09:04:48 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
09:04:49 INFO  : 
09:04:50 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
09:04:51 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
09:04:52 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
09:04:52 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
09:04:52 INFO  : Clearing existing target manager status.
09:04:55 INFO  : Closing and re-opening the MSS file of ther project standalone_bsp_0
09:04:57 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
09:05:07 WARN  : Linker script will not be updated automatically. Users need to update it manually.
09:34:40 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:34:40 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:34:57 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:35:40 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:35:40 INFO  : 'fpga -state' command is executed.
09:35:40 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:35:40 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:35:40 INFO  : 'jtag frequency' command is executed.
09:35:40 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:35:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:35:41 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:35:41 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:35:41 INFO  : 'stop' command is executed.
09:35:42 INFO  : 'ps7_init' command is executed.
09:35:42 INFO  : 'ps7_post_config' command is executed.
09:35:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:35:42 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:35:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:35:43 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:35:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:35:43 INFO  : Memory regions updated for context APU
09:35:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:35:43 INFO  : 'con' command is executed.
09:35:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:35:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:36:34 INFO  : Disconnected from the channel tcfchan#1.
09:36:34 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:36:34 INFO  : 'fpga -state' command is executed.
09:36:34 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:36:35 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:36:35 INFO  : 'jtag frequency' command is executed.
09:36:35 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:36:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:36:39 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:36:39 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:36:39 INFO  : 'stop' command is executed.
09:36:40 INFO  : 'ps7_init' command is executed.
09:36:40 INFO  : 'ps7_post_config' command is executed.
09:36:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:36:40 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:36:40 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:36:42 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:36:42 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:36:42 INFO  : Memory regions updated for context APU
09:36:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:36:42 INFO  : 'con' command is executed.
09:36:42 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:36:42 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:38:57 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:38:57 INFO  : 'fpga -state' command is executed.
09:38:57 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:38:57 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:38:57 INFO  : 'jtag frequency' command is executed.
09:38:57 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:38:57 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:38:57 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:38:57 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:38:57 INFO  : 'stop' command is executed.
09:38:59 INFO  : 'ps7_init' command is executed.
09:38:59 INFO  : 'ps7_post_config' command is executed.
09:38:59 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:38:59 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:38:59 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:39:01 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:39:01 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

09:39:01 INFO  : Memory regions updated for context APU
09:39:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:39:01 INFO  : 'con' command is executed.
09:39:01 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:39:01 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
09:39:13 INFO  : Disconnected from the channel tcfchan#2.
09:39:13 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:39:13 INFO  : 'fpga -state' command is executed.
09:39:13 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:39:14 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:39:14 INFO  : 'jtag frequency' command is executed.
09:39:14 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:39:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:39:14 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:39:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:39:14 INFO  : 'stop' command is executed.
09:39:15 INFO  : 'ps7_init' command is executed.
09:39:15 INFO  : 'ps7_post_config' command is executed.
09:39:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:39:15 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:39:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:39:17 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:39:17 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:39:17 INFO  : Memory regions updated for context APU
09:39:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:39:17 INFO  : 'con' command is executed.
09:39:17 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:39:17 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:40:20 INFO  : Disconnected from the channel tcfchan#3.
09:40:20 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:40:20 INFO  : 'fpga -state' command is executed.
09:40:20 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:40:20 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:40:20 INFO  : 'jtag frequency' command is executed.
09:40:20 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:40:21 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:40:21 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:40:21 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:40:21 INFO  : 'stop' command is executed.
09:40:22 INFO  : 'ps7_init' command is executed.
09:40:22 INFO  : 'ps7_post_config' command is executed.
09:40:22 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:40:22 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:40:22 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:40:23 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:40:23 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:40:23 INFO  : Memory regions updated for context APU
09:40:24 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:40:24 INFO  : 'con' command is executed.
09:40:24 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:40:24 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:41:53 INFO  : Disconnected from the channel tcfchan#4.
09:41:53 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:41:53 INFO  : 'fpga -state' command is executed.
09:41:53 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:41:53 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:41:53 INFO  : 'jtag frequency' command is executed.
09:41:53 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:41:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:41:54 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:41:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:41:54 INFO  : 'stop' command is executed.
09:41:55 INFO  : 'ps7_init' command is executed.
09:41:55 INFO  : 'ps7_post_config' command is executed.
09:41:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:41:55 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:41:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:41:56 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:41:56 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:41:56 INFO  : Memory regions updated for context APU
09:41:56 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:41:56 INFO  : 'con' command is executed.
09:41:56 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:41:56 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:44:50 INFO  : Disconnected from the channel tcfchan#5.
09:44:50 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:44:50 INFO  : 'fpga -state' command is executed.
09:44:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:44:50 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:44:50 INFO  : 'jtag frequency' command is executed.
09:44:50 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:44:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:44:50 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:44:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:44:50 INFO  : 'stop' command is executed.
09:44:51 INFO  : 'ps7_init' command is executed.
09:44:51 INFO  : 'ps7_post_config' command is executed.
09:44:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:44:51 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:44:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:44:53 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:44:53 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:44:53 INFO  : Memory regions updated for context APU
09:44:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:44:53 INFO  : 'con' command is executed.
09:44:53 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:44:53 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:46:16 INFO  : Disconnected from the channel tcfchan#6.
09:46:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:46:16 INFO  : 'fpga -state' command is executed.
09:46:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:46:16 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:46:16 INFO  : 'jtag frequency' command is executed.
09:46:16 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:46:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:46:16 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:46:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:46:16 INFO  : 'stop' command is executed.
09:46:18 INFO  : 'ps7_init' command is executed.
09:46:18 INFO  : 'ps7_post_config' command is executed.
09:46:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:46:18 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:46:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:46:19 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:46:19 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:46:19 INFO  : Memory regions updated for context APU
09:46:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:46:19 INFO  : 'con' command is executed.
09:46:19 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:46:19 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:47:22 INFO  : Disconnected from the channel tcfchan#7.
09:47:22 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:47:22 INFO  : 'fpga -state' command is executed.
09:47:22 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:47:22 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:47:22 INFO  : 'jtag frequency' command is executed.
09:47:22 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:47:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:47:22 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:47:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:47:22 INFO  : 'stop' command is executed.
09:47:24 INFO  : 'ps7_init' command is executed.
09:47:24 INFO  : 'ps7_post_config' command is executed.
09:47:24 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:47:24 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:47:24 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:47:25 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:47:25 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:47:25 INFO  : Memory regions updated for context APU
09:47:25 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:47:25 INFO  : 'con' command is executed.
09:47:25 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:47:25 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:50:01 INFO  : Disconnected from the channel tcfchan#8.
09:50:01 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:50:01 INFO  : 'fpga -state' command is executed.
09:50:01 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:50:02 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:50:02 INFO  : 'jtag frequency' command is executed.
09:50:02 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:50:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:50:02 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:50:02 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:50:02 INFO  : 'stop' command is executed.
09:50:03 INFO  : 'ps7_init' command is executed.
09:50:03 INFO  : 'ps7_post_config' command is executed.
09:50:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:50:03 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:50:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:50:05 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:50:05 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:50:05 INFO  : Memory regions updated for context APU
09:50:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:50:05 INFO  : 'con' command is executed.
09:50:05 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:50:05 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:51:42 INFO  : Disconnected from the channel tcfchan#9.
09:51:42 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:51:42 INFO  : 'fpga -state' command is executed.
09:51:42 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:51:42 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:51:42 INFO  : 'jtag frequency' command is executed.
09:51:42 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:51:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:51:42 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:51:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:51:42 INFO  : 'stop' command is executed.
09:51:43 INFO  : 'ps7_init' command is executed.
09:51:43 INFO  : 'ps7_post_config' command is executed.
09:51:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:51:44 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:51:44 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:51:45 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:51:45 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:51:45 INFO  : Memory regions updated for context APU
09:51:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:51:45 INFO  : 'con' command is executed.
09:51:45 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:51:45 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:56:14 INFO  : Disconnected from the channel tcfchan#10.
09:56:14 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:56:14 INFO  : 'fpga -state' command is executed.
09:56:14 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:56:14 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:56:14 INFO  : 'jtag frequency' command is executed.
09:56:14 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:56:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:56:14 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:56:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:56:15 INFO  : 'stop' command is executed.
09:56:20 INFO  : 'ps7_init' command is executed.
09:56:20 INFO  : 'ps7_post_config' command is executed.
09:56:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:56:20 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:56:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:56:22 ERROR : DEVICEEN is 0
09:56:22 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:58:08 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:58:08 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:58:25 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:58:43 WARN  : channel "tcfchan#2" closed
09:58:43 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:58:43 INFO  : 'fpga -state' command is executed.
09:58:43 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:58:43 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:58:43 INFO  : 'jtag frequency' command is executed.
09:58:43 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:58:43 ERROR : no targets found with "name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"". available targets:
  1  APU (JTAG port open error. AP transaction error, DAP status f0000021)
     2  ARM Cortex-A9 MPCore #0 (Running)
     3  ARM Cortex-A9 MPCore #1 (DEVICEEN is '0')
  4* xc7z030
09:58:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
----------------End of Script----------------

09:59:30 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:59:30 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:59:47 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:59:55 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:59:55 INFO  : 'fpga -state' command is executed.
09:59:55 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:59:56 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:59:56 INFO  : 'jtag frequency' command is executed.
09:59:56 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:59:56 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:59:56 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:59:56 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:59:56 INFO  : 'stop' command is executed.
09:59:57 INFO  : 'ps7_init' command is executed.
09:59:57 INFO  : 'ps7_post_config' command is executed.
09:59:57 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:59:57 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:59:57 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:59:58 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:59:58 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:59:58 INFO  : Memory regions updated for context APU
09:59:58 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:59:58 INFO  : 'con' command is executed.
09:59:58 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:59:58 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
10:00:25 INFO  : Disconnected from the channel tcfchan#11.
10:00:25 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:00:25 INFO  : 'fpga -state' command is executed.
10:00:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:00:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:00:26 INFO  : 'jtag frequency' command is executed.
10:00:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:00:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:00:26 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:00:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:00:26 INFO  : 'stop' command is executed.
10:00:27 INFO  : 'ps7_init' command is executed.
10:00:27 INFO  : 'ps7_post_config' command is executed.
10:00:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:00:27 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:00:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:00:28 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:00:28 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

10:00:28 INFO  : Memory regions updated for context APU
10:00:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:00:28 INFO  : 'con' command is executed.
10:00:28 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:00:28 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
10:03:15 INFO  : Disconnected from the channel tcfchan#12.
10:03:15 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:03:15 INFO  : 'fpga -state' command is executed.
10:03:15 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:03:15 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:03:15 INFO  : 'jtag frequency' command is executed.
10:03:15 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:03:15 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:03:15 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:03:15 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:03:15 INFO  : 'stop' command is executed.
10:03:16 INFO  : 'ps7_init' command is executed.
10:03:16 INFO  : 'ps7_post_config' command is executed.
10:03:16 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:03:17 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:03:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:03:18 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:03:18 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

10:03:18 INFO  : Memory regions updated for context APU
10:03:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:03:18 INFO  : 'con' command is executed.
10:03:18 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:03:18 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
16:26:28 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1472135118000,  Project:1472108558000
16:26:28 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
16:26:34 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
16:26:40 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
16:26:41 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

16:26:41 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

16:26:41 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

16:26:41 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

16:26:41 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

16:26:41 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-colord.service-9q0sAn"

16:26:41 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-rtkit-daemon.service-epARcy"

16:26:41 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

16:26:41 ERROR : Error updating BSP project MSS files.
16:26:42 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
16:26:43 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
16:26:44 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
16:26:44 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
16:26:45 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
16:26:45 INFO  : Clearing existing target manager status.
16:26:45 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
16:26:46 WARN  : Linker script will not be updated automatically. Users need to update it manually.
16:26:46 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

16:26:46 ERROR :  [Common 17-39] 'hsi::current_sw_design' failed due to earlier errors.
16:26:46 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

16:26:46 INFO  : Unable to read in MSS file /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/standalone_bsp_0/system.mss : null
16:26:46 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

16:26:46 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

16:26:46 ERROR : Failed to get_connected_periphs
Reason: ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

16:26:46 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

16:26:46 ERROR :  [Common 17-39] 'hsi::current_sw_design' failed due to earlier errors.
16:26:46 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

16:26:46 INFO  : Unable to read in MSS file /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/standalone_bsp_0/system.mss : null
16:26:46 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

16:26:46 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

16:26:46 ERROR : Failed to get_connected_periphs
Reason: ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

17:22:49 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:22:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:23:06 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
17:23:20 INFO  : Disconnected from the channel tcfchan#13.
17:23:20 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:23:20 INFO  : 'fpga -state' command is executed.
17:23:20 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:23:21 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:23:21 INFO  : 'jtag frequency' command is executed.
17:23:21 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:23:21 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:23:21 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:23:21 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:23:21 INFO  : 'stop' command is executed.
17:23:22 INFO  : 'ps7_init' command is executed.
17:23:22 INFO  : 'ps7_post_config' command is executed.
17:23:22 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:23:22 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:23:22 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:23:23 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:23:23 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:23:23 INFO  : Memory regions updated for context APU
17:23:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:23:24 INFO  : 'con' command is executed.
17:23:24 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:23:24 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:24:40 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:24:40 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:24:57 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
17:25:14 INFO  : Disconnected from the channel tcfchan#14.
17:25:14 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:25:14 INFO  : 'fpga -state' command is executed.
17:25:14 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:25:14 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:25:14 INFO  : 'jtag frequency' command is executed.
17:25:14 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:25:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:25:14 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:25:14 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:25:14 INFO  : 'stop' command is executed.
17:25:15 INFO  : 'ps7_init' command is executed.
17:25:15 INFO  : 'ps7_post_config' command is executed.
17:25:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:25:15 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:25:16 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:25:17 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:25:17 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:25:17 INFO  : Memory regions updated for context APU
17:25:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:25:17 INFO  : 'con' command is executed.
17:25:17 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:25:17 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:25:31 INFO  : Disconnected from the channel tcfchan#15.
17:25:31 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:25:31 INFO  : 'fpga -state' command is executed.
17:25:31 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:25:32 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:25:32 INFO  : 'jtag frequency' command is executed.
17:25:32 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:25:32 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:25:32 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:25:32 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:25:32 INFO  : 'stop' command is executed.
17:25:33 INFO  : 'ps7_init' command is executed.
17:25:33 INFO  : 'ps7_post_config' command is executed.
17:25:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:25:33 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:25:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:25:34 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:25:34 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:25:34 INFO  : Memory regions updated for context APU
17:25:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:25:34 INFO  : 'con' command is executed.
17:25:34 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:25:34 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:27:46 INFO  : Disconnected from the channel tcfchan#16.
17:27:46 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:27:46 INFO  : 'fpga -state' command is executed.
17:27:46 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:27:47 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:27:47 INFO  : 'jtag frequency' command is executed.
17:27:47 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:27:47 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:27:47 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:27:47 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:27:47 INFO  : 'stop' command is executed.
17:27:48 INFO  : 'ps7_init' command is executed.
17:27:48 INFO  : 'ps7_post_config' command is executed.
17:27:48 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:27:48 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:27:48 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:27:49 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:27:49 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:27:49 INFO  : Memory regions updated for context APU
17:27:49 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:27:49 INFO  : 'con' command is executed.
17:27:49 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:27:49 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:30:16 INFO  : Disconnected from the channel tcfchan#17.
17:30:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:30:16 INFO  : 'fpga -state' command is executed.
17:30:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:30:17 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:30:17 INFO  : 'jtag frequency' command is executed.
17:30:17 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:30:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:30:17 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:30:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:30:17 INFO  : 'stop' command is executed.
17:30:18 INFO  : 'ps7_init' command is executed.
17:30:18 INFO  : 'ps7_post_config' command is executed.
17:30:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:18 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:30:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:19 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:30:19 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:30:19 INFO  : Memory regions updated for context APU
17:30:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:19 INFO  : 'con' command is executed.
17:30:19 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:30:19 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:30:29 INFO  : Disconnected from the channel tcfchan#18.
17:30:30 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:30:30 INFO  : 'fpga -state' command is executed.
17:30:30 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:30:30 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:30:30 INFO  : 'jtag frequency' command is executed.
17:30:30 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:30:30 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:30:30 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:30:30 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:30:30 INFO  : 'stop' command is executed.
17:30:31 INFO  : 'ps7_init' command is executed.
17:30:31 INFO  : 'ps7_post_config' command is executed.
17:30:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:31 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:30:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:32 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:30:32 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:30:32 INFO  : Memory regions updated for context APU
17:30:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:32 INFO  : 'con' command is executed.
17:30:32 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:30:32 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:30:51 INFO  : Disconnected from the channel tcfchan#19.
17:30:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:30:51 INFO  : 'fpga -state' command is executed.
17:30:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:30:51 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:30:51 INFO  : 'jtag frequency' command is executed.
17:30:51 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:30:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:30:51 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:30:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:30:51 INFO  : 'stop' command is executed.
17:30:52 INFO  : 'ps7_init' command is executed.
17:30:52 INFO  : 'ps7_post_config' command is executed.
17:30:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:52 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:30:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:54 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:30:54 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:30:54 INFO  : Memory regions updated for context APU
17:30:54 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:30:54 INFO  : 'con' command is executed.
17:30:54 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:30:54 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:31:03 INFO  : Disconnected from the channel tcfchan#20.
17:31:04 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:31:04 INFO  : 'fpga -state' command is executed.
17:31:04 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:31:04 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:31:04 INFO  : 'jtag frequency' command is executed.
17:31:04 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:31:04 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:31:04 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:31:04 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:31:04 INFO  : 'stop' command is executed.
17:31:05 INFO  : 'ps7_init' command is executed.
17:31:05 INFO  : 'ps7_post_config' command is executed.
17:31:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:31:05 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:31:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:31:07 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:31:07 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:31:07 INFO  : Memory regions updated for context APU
17:31:07 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:31:07 INFO  : 'con' command is executed.
17:31:07 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:31:07 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:34:42 INFO  : Disconnected from the channel tcfchan#21.
17:34:42 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:34:42 INFO  : 'fpga -state' command is executed.
17:34:42 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:34:42 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:34:42 INFO  : 'jtag frequency' command is executed.
17:34:42 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:34:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:34:42 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:34:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:34:42 INFO  : 'stop' command is executed.
17:34:43 INFO  : 'ps7_init' command is executed.
17:34:43 INFO  : 'ps7_post_config' command is executed.
17:34:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:34:44 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:34:44 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:34:45 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:34:45 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:34:45 INFO  : Memory regions updated for context APU
17:34:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:34:45 INFO  : 'con' command is executed.
17:34:45 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:34:45 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:35:33 INFO  : Disconnected from the channel tcfchan#22.
17:35:34 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:35:34 INFO  : 'fpga -state' command is executed.
17:35:34 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:35:34 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:35:34 INFO  : 'jtag frequency' command is executed.
17:35:34 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:35:34 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:35:34 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:35:34 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:35:34 INFO  : 'stop' command is executed.
17:35:35 INFO  : 'ps7_init' command is executed.
17:35:35 INFO  : 'ps7_post_config' command is executed.
17:35:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:35:35 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:35:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:35:36 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:35:36 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:35:36 INFO  : Memory regions updated for context APU
17:35:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:35:37 INFO  : 'con' command is executed.
17:35:37 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:35:37 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:38:29 INFO  : Disconnected from the channel tcfchan#23.
17:38:29 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:38:29 INFO  : 'fpga -state' command is executed.
17:38:29 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:38:29 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:38:29 INFO  : 'jtag frequency' command is executed.
17:38:29 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:38:29 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:38:29 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:38:29 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:38:29 INFO  : 'stop' command is executed.
17:38:30 INFO  : 'ps7_init' command is executed.
17:38:30 INFO  : 'ps7_post_config' command is executed.
17:38:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:38:30 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:38:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:38:32 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:38:32 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:38:32 INFO  : Memory regions updated for context APU
17:38:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:38:32 INFO  : 'con' command is executed.
17:38:32 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:38:32 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
18:01:13 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1472140701000,  Project:1472135118000
18:01:13 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
18:01:15 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
18:01:23 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
18:01:23 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-colord.service-9q0sAn"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-rtkit-daemon.service-epARcy"

18:01:23 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

18:01:23 ERROR : Error updating BSP project MSS files.
18:01:24 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
18:01:25 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
18:01:26 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
18:01:27 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
18:01:27 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
18:01:27 INFO  : Clearing existing target manager status.
18:01:27 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
18:01:28 WARN  : Linker script will not be updated automatically. Users need to update it manually.
18:03:46 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:03:46 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:04:03 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:05:04 INFO  : Disconnected from the channel tcfchan#24.
18:05:04 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:05:04 INFO  : 'fpga -state' command is executed.
18:05:04 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:05:05 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:05:05 INFO  : 'jtag frequency' command is executed.
18:05:05 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:05:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:05:05 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:05:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:05:05 INFO  : 'stop' command is executed.
18:05:06 INFO  : 'ps7_init' command is executed.
18:05:06 INFO  : 'ps7_post_config' command is executed.
18:05:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:05:06 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:05:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:05:08 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:05:08 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

18:05:08 INFO  : Memory regions updated for context APU
18:05:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:05:08 INFO  : 'con' command is executed.
18:05:08 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:05:08 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:25:29 INFO  : Disconnected from the channel tcfchan#25.
19:25:29 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:25:29 INFO  : 'fpga -state' command is executed.
19:25:29 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:25:29 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:25:29 INFO  : 'jtag frequency' command is executed.
19:25:29 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:25:29 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:25:29 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:25:29 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:25:29 INFO  : 'stop' command is executed.
19:25:30 INFO  : 'ps7_init' command is executed.
19:25:30 INFO  : 'ps7_post_config' command is executed.
19:25:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:25:31 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:25:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:25:32 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:25:32 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:25:32 INFO  : Memory regions updated for context APU
19:25:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:25:32 INFO  : 'con' command is executed.
19:25:32 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:25:32 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:28:39 INFO  : Disconnected from the channel tcfchan#26.
19:28:39 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:28:39 INFO  : 'fpga -state' command is executed.
19:28:39 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:28:40 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:28:40 INFO  : 'jtag frequency' command is executed.
19:28:40 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:28:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:28:40 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:28:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:28:40 INFO  : 'stop' command is executed.
19:28:41 INFO  : 'ps7_init' command is executed.
19:28:41 INFO  : 'ps7_post_config' command is executed.
19:28:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:28:41 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:28:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:28:42 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:28:42 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:28:42 INFO  : Memory regions updated for context APU
19:28:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:28:43 INFO  : 'con' command is executed.
19:28:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:28:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:29:40 INFO  : Disconnected from the channel tcfchan#27.
19:29:40 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:29:40 INFO  : 'fpga -state' command is executed.
19:29:40 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:29:40 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:29:40 INFO  : 'jtag frequency' command is executed.
19:29:40 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:29:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:29:40 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:29:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:29:40 INFO  : 'stop' command is executed.
19:29:41 INFO  : 'ps7_init' command is executed.
19:29:41 INFO  : 'ps7_post_config' command is executed.
19:29:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:29:41 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:29:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:29:43 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:29:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:29:43 INFO  : Memory regions updated for context APU
19:29:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:29:43 INFO  : 'con' command is executed.
19:29:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:29:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:30:55 INFO  : Disconnected from the channel tcfchan#28.
19:30:55 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:30:55 INFO  : 'fpga -state' command is executed.
19:30:55 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:30:55 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:30:55 INFO  : 'jtag frequency' command is executed.
19:30:55 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:30:55 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:30:55 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:30:55 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:30:55 INFO  : 'stop' command is executed.
19:30:56 INFO  : 'ps7_init' command is executed.
19:30:56 INFO  : 'ps7_post_config' command is executed.
19:30:56 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:30:56 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:30:56 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:30:58 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:30:58 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:30:58 INFO  : Memory regions updated for context APU
19:30:58 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:30:58 INFO  : 'con' command is executed.
19:30:58 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:30:58 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:35:41 INFO  : Disconnected from the channel tcfchan#29.
19:35:41 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:35:41 INFO  : 'fpga -state' command is executed.
19:35:41 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:35:42 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:35:42 INFO  : 'jtag frequency' command is executed.
19:35:42 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:35:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:35:42 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:35:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:35:42 INFO  : 'stop' command is executed.
19:35:43 INFO  : 'ps7_init' command is executed.
19:35:43 INFO  : 'ps7_post_config' command is executed.
19:35:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:35:43 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:35:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:35:44 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:35:44 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:35:44 INFO  : Memory regions updated for context APU
19:35:44 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:35:44 INFO  : 'con' command is executed.
19:35:44 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:35:44 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:39:04 INFO  : Disconnected from the channel tcfchan#30.
19:39:04 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:39:04 INFO  : 'fpga -state' command is executed.
19:39:04 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:39:04 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:39:04 INFO  : 'jtag frequency' command is executed.
19:39:04 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:39:04 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:39:04 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:39:04 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:39:04 INFO  : 'stop' command is executed.
19:39:05 INFO  : 'ps7_init' command is executed.
19:39:05 INFO  : 'ps7_post_config' command is executed.
19:39:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:39:06 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:39:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:39:07 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:39:07 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:39:07 INFO  : Memory regions updated for context APU
19:39:07 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:39:07 INFO  : 'con' command is executed.
19:39:07 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:39:07 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:39:44 INFO  : Disconnected from the channel tcfchan#31.
19:39:44 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:39:44 INFO  : 'fpga -state' command is executed.
19:39:44 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:39:45 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:39:45 INFO  : 'jtag frequency' command is executed.
19:39:45 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:39:45 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:39:45 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:39:45 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:39:45 INFO  : 'stop' command is executed.
19:39:46 INFO  : 'ps7_init' command is executed.
19:39:46 INFO  : 'ps7_post_config' command is executed.
19:39:46 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:39:46 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:39:46 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:39:47 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:39:47 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:39:47 INFO  : Memory regions updated for context APU
19:39:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:39:47 INFO  : 'con' command is executed.
19:39:47 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:39:47 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:40:34 INFO  : Disconnected from the channel tcfchan#32.
19:40:34 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:40:34 INFO  : 'fpga -state' command is executed.
19:40:34 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:40:34 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:40:35 INFO  : 'jtag frequency' command is executed.
19:40:35 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:40:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:40:35 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:40:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:40:35 INFO  : 'stop' command is executed.
19:40:36 INFO  : 'ps7_init' command is executed.
19:40:36 INFO  : 'ps7_post_config' command is executed.
19:40:36 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:40:36 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:40:36 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:40:37 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:40:37 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:40:37 INFO  : Memory regions updated for context APU
19:40:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:40:37 INFO  : 'con' command is executed.
19:40:37 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:40:37 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:42:17 INFO  : Disconnected from the channel tcfchan#33.
19:42:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:42:17 INFO  : 'fpga -state' command is executed.
19:42:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:42:18 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:42:18 INFO  : 'jtag frequency' command is executed.
19:42:18 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:42:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:42:18 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:42:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:42:18 INFO  : 'stop' command is executed.
19:42:19 INFO  : 'ps7_init' command is executed.
19:42:19 INFO  : 'ps7_post_config' command is executed.
19:42:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:42:19 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:42:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:42:20 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:42:20 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:42:20 INFO  : Memory regions updated for context APU
19:42:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:42:20 INFO  : 'con' command is executed.
19:42:20 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:42:20 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:43:44 INFO  : Disconnected from the channel tcfchan#34.
19:43:44 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:43:44 INFO  : 'fpga -state' command is executed.
19:43:44 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:43:45 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:43:45 INFO  : 'jtag frequency' command is executed.
19:43:45 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:43:45 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:43:45 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:43:45 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:43:45 INFO  : 'stop' command is executed.
19:43:46 INFO  : 'ps7_init' command is executed.
19:43:46 INFO  : 'ps7_post_config' command is executed.
19:43:46 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:43:46 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:43:46 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:43:47 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:43:47 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:43:47 INFO  : Memory regions updated for context APU
19:43:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:43:47 INFO  : 'con' command is executed.
19:43:47 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:43:47 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:51:32 INFO  : Disconnected from the channel tcfchan#35.
19:51:32 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:51:32 INFO  : 'fpga -state' command is executed.
19:51:32 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:51:32 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:51:32 INFO  : 'jtag frequency' command is executed.
19:51:32 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:51:32 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:51:32 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:51:32 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:51:32 INFO  : 'stop' command is executed.
19:51:33 INFO  : 'ps7_init' command is executed.
19:51:33 INFO  : 'ps7_post_config' command is executed.
19:51:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:51:34 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:51:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:51:35 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:51:35 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:51:35 INFO  : Memory regions updated for context APU
19:51:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:51:35 INFO  : 'con' command is executed.
19:51:35 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:51:35 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:52:17 INFO  : Disconnected from the channel tcfchan#36.
19:52:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:52:17 INFO  : 'fpga -state' command is executed.
19:52:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:52:18 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:52:18 INFO  : 'jtag frequency' command is executed.
19:52:18 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:52:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:52:18 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:52:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:52:18 INFO  : 'stop' command is executed.
19:52:19 INFO  : 'ps7_init' command is executed.
19:52:19 INFO  : 'ps7_post_config' command is executed.
19:52:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:52:19 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:52:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:52:20 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:52:20 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:52:20 INFO  : Memory regions updated for context APU
19:52:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:52:20 INFO  : 'con' command is executed.
19:52:20 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:52:20 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:52:43 INFO  : Disconnected from the channel tcfchan#37.
19:52:44 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:52:44 INFO  : 'fpga -state' command is executed.
19:52:44 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:52:44 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:52:44 INFO  : 'jtag frequency' command is executed.
19:52:44 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:52:44 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:52:44 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:52:44 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:52:44 INFO  : 'stop' command is executed.
19:52:45 INFO  : 'ps7_init' command is executed.
19:52:45 INFO  : 'ps7_post_config' command is executed.
19:52:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:52:45 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:52:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:52:47 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:52:47 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:52:47 INFO  : Memory regions updated for context APU
19:52:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:52:47 INFO  : 'con' command is executed.
19:52:47 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:52:47 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:59:36 INFO  : Disconnected from the channel tcfchan#38.
19:59:36 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:59:36 INFO  : 'fpga -state' command is executed.
19:59:36 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:59:36 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
19:59:36 INFO  : 'jtag frequency' command is executed.
19:59:36 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
19:59:37 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:59:37 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
19:59:37 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
19:59:37 INFO  : 'stop' command is executed.
19:59:38 INFO  : 'ps7_init' command is executed.
19:59:38 INFO  : 'ps7_post_config' command is executed.
19:59:38 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:59:38 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
19:59:38 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:59:39 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
19:59:39 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

19:59:39 INFO  : Memory regions updated for context APU
19:59:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
19:59:39 INFO  : 'con' command is executed.
19:59:39 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

19:59:39 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
20:00:40 INFO  : Disconnected from the channel tcfchan#39.
20:00:41 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:00:41 INFO  : 'fpga -state' command is executed.
20:00:41 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:00:41 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
20:00:41 INFO  : 'jtag frequency' command is executed.
20:00:41 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
20:00:41 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:00:41 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
20:00:41 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:00:41 INFO  : 'stop' command is executed.
20:00:42 INFO  : 'ps7_init' command is executed.
20:00:42 INFO  : 'ps7_post_config' command is executed.
20:00:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:00:42 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
20:00:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:00:44 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
20:00:44 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

20:00:44 INFO  : Memory regions updated for context APU
20:00:44 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:00:44 INFO  : 'con' command is executed.
20:00:44 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

20:00:44 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
20:03:12 INFO  : Disconnected from the channel tcfchan#40.
20:03:12 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:03:12 INFO  : 'fpga -state' command is executed.
20:03:12 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:03:12 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
20:03:12 INFO  : 'jtag frequency' command is executed.
20:03:12 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
20:03:12 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:03:12 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
20:03:12 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:03:12 INFO  : 'stop' command is executed.
20:03:13 INFO  : 'ps7_init' command is executed.
20:03:13 INFO  : 'ps7_post_config' command is executed.
20:03:13 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:03:13 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
20:03:13 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:03:15 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
20:03:15 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

20:03:15 INFO  : Memory regions updated for context APU
20:03:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:03:15 INFO  : 'con' command is executed.
20:03:15 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

20:03:15 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:19:05 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:19:05 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:19:22 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:19:39 INFO  : Disconnected from the channel tcfchan#41.
09:19:40 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:19:40 INFO  : 'fpga -state' command is executed.
09:19:40 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:19:40 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:19:40 INFO  : 'jtag frequency' command is executed.
09:19:40 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:19:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:19:40 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:19:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:19:40 INFO  : 'stop' command is executed.
09:19:41 INFO  : 'ps7_init' command is executed.
09:19:41 INFO  : 'ps7_post_config' command is executed.
09:19:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:19:41 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:19:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:19:43 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:19:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:19:43 INFO  : Memory regions updated for context APU
09:19:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:19:43 INFO  : 'con' command is executed.
09:19:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:19:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
15:36:06 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1472199598000,  Project:1472140701000
15:36:06 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
15:36:09 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
15:36:16 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
15:36:17 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

15:36:17 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

15:36:17 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

15:36:17 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

15:36:17 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

15:36:17 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-colord.service-9q0sAn"

15:36:17 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-rtkit-daemon.service-epARcy"

15:36:17 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

15:36:17 ERROR : Error updating BSP project MSS files.
15:36:18 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
15:36:19 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
15:36:19 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
15:36:20 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
15:36:21 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
15:36:21 INFO  : Clearing existing target manager status.
15:36:21 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
15:36:21 WARN  : Linker script will not be updated automatically. Users need to update it manually.
15:47:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
15:47:50 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
15:48:08 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
15:51:04 INFO  : Disconnected from the channel tcfchan#42.
15:51:04 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
15:51:04 INFO  : 'fpga -state' command is executed.
15:51:04 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
15:51:05 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
15:51:05 INFO  : 'jtag frequency' command is executed.
15:51:05 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
15:51:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
15:51:05 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
15:51:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
15:51:05 INFO  : 'stop' command is executed.
15:51:06 INFO  : 'ps7_init' command is executed.
15:51:06 INFO  : 'ps7_post_config' command is executed.
15:51:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
15:51:06 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
15:51:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
15:51:07 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
15:51:07 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

15:51:07 INFO  : Memory regions updated for context APU
15:51:07 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
15:51:07 INFO  : 'con' command is executed.
15:51:07 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

15:51:07 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
16:13:50 INFO  : Disconnected from the channel tcfchan#43.
16:13:50 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:13:50 INFO  : 'fpga -state' command is executed.
16:13:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:13:50 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:13:50 INFO  : 'jtag frequency' command is executed.
16:13:50 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:13:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:13:50 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:13:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:13:51 INFO  : 'stop' command is executed.
16:13:52 INFO  : 'ps7_init' command is executed.
16:13:52 INFO  : 'ps7_post_config' command is executed.
16:13:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:13:52 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:13:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:13:54 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:13:54 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

16:13:54 INFO  : Memory regions updated for context APU
16:13:54 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:13:54 INFO  : 'con' command is executed.
16:13:54 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:13:54 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
16:15:25 INFO  : Disconnected from the channel tcfchan#44.
16:15:26 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:15:26 INFO  : 'fpga -state' command is executed.
16:15:26 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:15:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:15:26 INFO  : 'jtag frequency' command is executed.
16:15:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:15:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:15:26 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:15:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:15:26 INFO  : 'stop' command is executed.
16:15:27 INFO  : 'ps7_init' command is executed.
16:15:27 INFO  : 'ps7_post_config' command is executed.
16:15:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:15:27 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:15:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:15:29 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:15:29 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

16:15:29 INFO  : Memory regions updated for context APU
16:15:29 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:15:29 INFO  : 'con' command is executed.
16:15:29 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:15:29 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
16:25:56 INFO  : Disconnected from the channel tcfchan#45.
16:25:56 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:25:56 INFO  : 'fpga -state' command is executed.
16:25:56 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:25:57 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:25:57 INFO  : 'jtag frequency' command is executed.
16:25:57 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:25:57 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:25:57 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:25:57 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:25:57 INFO  : 'stop' command is executed.
16:25:58 INFO  : 'ps7_init' command is executed.
16:25:58 INFO  : 'ps7_post_config' command is executed.
16:25:58 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:25:58 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:25:58 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:26:00 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:26:00 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

16:26:00 INFO  : Memory regions updated for context APU
16:26:00 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:26:00 INFO  : 'con' command is executed.
16:26:00 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:26:00 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
16:27:09 INFO  : Disconnected from the channel tcfchan#46.
16:27:09 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:27:09 INFO  : 'fpga -state' command is executed.
16:27:09 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:27:09 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:27:09 INFO  : 'jtag frequency' command is executed.
16:27:09 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:27:10 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:27:10 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:27:10 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:27:10 INFO  : 'stop' command is executed.
16:27:11 INFO  : 'ps7_init' command is executed.
16:27:11 INFO  : 'ps7_post_config' command is executed.
16:27:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:27:11 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:27:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:27:12 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:27:12 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

16:27:12 INFO  : Memory regions updated for context APU
16:27:12 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:27:12 INFO  : 'con' command is executed.
16:27:12 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:27:12 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
16:34:24 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:34:24 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:34:41 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
16:34:47 INFO  : Disconnected from the channel tcfchan#47.
16:34:47 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:34:47 INFO  : 'fpga -state' command is executed.
16:34:47 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:34:48 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:34:48 INFO  : 'jtag frequency' command is executed.
16:34:48 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:34:48 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:34:48 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:34:48 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:34:48 INFO  : 'stop' command is executed.
16:34:49 INFO  : 'ps7_init' command is executed.
16:34:49 INFO  : 'ps7_post_config' command is executed.
16:34:49 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:34:49 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:34:49 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:34:51 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:34:51 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

16:34:51 INFO  : Memory regions updated for context APU
16:34:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:34:51 INFO  : 'con' command is executed.
16:34:51 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:34:51 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
16:51:50 INFO  : Disconnected from the channel tcfchan#48.
16:51:50 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:51:50 INFO  : 'fpga -state' command is executed.
16:51:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:51:50 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:51:50 INFO  : 'jtag frequency' command is executed.
16:51:50 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:51:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:51:50 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:51:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:51:50 INFO  : 'stop' command is executed.
16:51:51 INFO  : 'ps7_init' command is executed.
16:51:51 INFO  : 'ps7_post_config' command is executed.
16:51:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:51:51 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:51:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:51:53 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:51:53 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

16:51:53 INFO  : Memory regions updated for context APU
16:51:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:51:53 INFO  : 'con' command is executed.
16:51:53 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:51:53 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:18:34 INFO  : Disconnected from the channel tcfchan#49.
17:18:34 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:18:34 INFO  : 'fpga -state' command is executed.
17:18:34 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:18:35 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:18:35 INFO  : 'jtag frequency' command is executed.
17:18:35 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:18:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:18:35 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:18:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:18:35 INFO  : 'stop' command is executed.
17:18:36 INFO  : 'ps7_init' command is executed.
17:18:36 INFO  : 'ps7_post_config' command is executed.
17:18:36 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:18:36 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:18:36 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:18:38 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:18:38 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:18:38 INFO  : Memory regions updated for context APU
17:18:38 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:18:38 INFO  : 'con' command is executed.
17:18:38 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:18:38 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
17:20:15 INFO  : Disconnected from the channel tcfchan#50.
17:20:15 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:20:15 INFO  : 'fpga -state' command is executed.
17:20:15 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:20:16 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:20:16 INFO  : 'jtag frequency' command is executed.
17:20:16 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:20:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:20:16 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:20:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:20:16 INFO  : 'stop' command is executed.
17:20:17 INFO  : 'ps7_init' command is executed.
17:20:17 INFO  : 'ps7_post_config' command is executed.
17:20:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:20:17 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:20:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:20:19 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:20:19 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:20:19 INFO  : Memory regions updated for context APU
17:20:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:20:19 INFO  : 'con' command is executed.
17:20:19 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:20:19 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
18:14:08 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1472227151000,  Project:1472199598000
18:14:08 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
18:14:10 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
18:14:17 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
18:14:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

18:14:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

18:14:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

18:14:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

18:14:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

18:14:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-colord.service-9q0sAn"

18:14:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-rtkit-daemon.service-epARcy"

18:14:18 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

18:14:18 ERROR : Error updating BSP project MSS files.
18:14:19 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
18:14:19 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
18:14:20 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
18:14:21 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
18:14:22 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
18:14:22 INFO  : Clearing existing target manager status.
18:14:22 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
18:14:22 WARN  : Linker script will not be updated automatically. Users need to update it manually.
18:16:07 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:16:07 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:16:25 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:16:30 INFO  : Disconnected from the channel tcfchan#51.
18:16:31 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:16:31 INFO  : 'fpga -state' command is executed.
18:16:31 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:16:31 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:16:31 INFO  : 'jtag frequency' command is executed.
18:16:31 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:16:31 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:16:31 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:16:31 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:16:31 INFO  : 'stop' command is executed.
18:16:32 INFO  : 'ps7_init' command is executed.
18:16:32 INFO  : 'ps7_post_config' command is executed.
18:16:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:16:32 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:16:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:16:34 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:16:34 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

18:16:34 INFO  : Memory regions updated for context APU
18:16:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:16:34 INFO  : 'con' command is executed.
18:16:34 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:16:34 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
18:17:07 INFO  : Disconnected from the channel tcfchan#52.
18:17:08 ERROR : Unexpected error while parsing XMD response : com.google.gson.JsonSyntaxException: com.google.gson.stream.MalformedJsonException: invalid number or unquoted string near 
11:35:01 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
11:35:03 INFO  : XSDB server has started successfully.
11:35:03 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
11:35:05 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
12:29:41 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1472550700000,  Project:1472227151000
12:29:41 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
12:29:42 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
12:29:50 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
12:29:51 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

12:29:51 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

12:29:51 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

12:29:51 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

12:29:51 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

12:29:51 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-colord.service-9q0sAn"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-rtkit-daemon.service-epARcy"

12:29:51 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

12:29:51 ERROR : Error updating BSP project MSS files.
12:29:52 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
12:29:53 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
12:29:53 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
12:29:54 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
12:29:55 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
12:29:55 INFO  : Clearing existing target manager status.
12:29:58 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
12:30:09 WARN  : Linker script will not be updated automatically. Users need to update it manually.
17:36:55 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
17:36:56 INFO  : XSDB server has started successfully.
17:36:56 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
17:36:58 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
17:37:01 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1472657763000,  Project:1472630774000
17:37:01 INFO  : The hardware specification for project 'system_design_wrapper_hw_platform_0' is different from /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
17:37:01 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
17:37:10 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
17:37:11 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

17:37:11 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

17:37:11 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

17:37:11 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

17:37:11 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

17:37:11 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-colord.service-9q0sAn"

17:37:11 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-rtkit-daemon.service-epARcy"

17:37:11 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

17:37:11 ERROR : Error updating BSP project MSS files.
17:37:12 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
17:37:13 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
17:37:14 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
17:37:15 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
17:37:16 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
17:37:16 INFO  : Clearing existing target manager status.
17:37:19 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
17:37:32 WARN  : Linker script will not be updated automatically. Users need to update it manually.
17:38:41 ERROR : Unexpected error while parsing XMD response : com.google.gson.JsonSyntaxException: com.google.gson.stream.MalformedJsonException: invalid number or unquoted string near 
16:28:41 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
16:28:42 INFO  : XSDB server has started successfully.
16:28:42 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
16:28:44 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
09:36:21 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
09:36:23 INFO  : XSDB server has started successfully.
09:36:23 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
09:36:25 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
09:46:28 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:46:28 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:46:45 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:47:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:47:49 INFO  : 'fpga -state' command is executed.
09:47:49 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:47:49 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:47:49 INFO  : 'jtag frequency' command is executed.
09:47:49 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:47:49 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:47:50 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:47:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:47:50 INFO  : 'stop' command is executed.
09:47:51 INFO  : 'ps7_init' command is executed.
09:47:51 INFO  : 'ps7_post_config' command is executed.
09:47:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:47:51 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:47:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:47:53 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:47:53 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:47:53 INFO  : Memory regions updated for context APU
09:47:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:47:53 INFO  : 'con' command is executed.
09:47:53 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:47:53 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
10:14:37 INFO  : Disconnected from the channel tcfchan#1.
10:14:37 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:14:37 INFO  : 'fpga -state' command is executed.
10:14:37 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:14:38 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:14:38 INFO  : 'jtag frequency' command is executed.
10:14:38 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:14:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:14:42 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:14:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:14:42 INFO  : 'stop' command is executed.
10:14:44 INFO  : 'ps7_init' command is executed.
10:14:44 INFO  : 'ps7_post_config' command is executed.
10:14:44 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:14:44 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:14:44 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:14:45 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:14:45 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

10:14:45 INFO  : Memory regions updated for context APU
10:14:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:14:45 INFO  : 'con' command is executed.
10:14:45 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:14:45 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
10:15:44 INFO  : Disconnected from the channel tcfchan#2.
10:15:44 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:15:44 INFO  : 'fpga -state' command is executed.
10:15:44 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:15:45 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:15:45 INFO  : 'jtag frequency' command is executed.
10:15:45 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:15:45 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:15:50 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:15:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:15:50 INFO  : 'stop' command is executed.
10:15:51 INFO  : 'ps7_init' command is executed.
10:15:51 INFO  : 'ps7_post_config' command is executed.
10:15:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:15:51 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:15:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:15:53 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:15:53 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

10:15:53 INFO  : Memory regions updated for context APU
10:15:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:15:53 INFO  : 'con' command is executed.
10:15:53 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:15:53 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
10:53:20 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:53:20 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:53:37 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
10:55:38 INFO  : Disconnected from the channel tcfchan#3.
10:55:38 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:55:38 INFO  : 'fpga -state' command is executed.
10:55:38 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:55:38 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:55:38 INFO  : 'jtag frequency' command is executed.
10:55:39 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:55:39 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:55:44 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:55:44 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:55:44 INFO  : 'stop' command is executed.
10:55:45 INFO  : 'ps7_init' command is executed.
10:55:45 INFO  : 'ps7_post_config' command is executed.
10:55:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:45 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:55:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:47 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:55:47 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

10:55:47 INFO  : Memory regions updated for context APU
10:55:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:55:47 INFO  : 'con' command is executed.
10:55:47 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:55:47 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
19:45:16 INFO  : Disconnected from the channel tcfchan#4.
18:17:43 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
18:17:44 INFO  : XSDB server has started successfully.
18:17:45 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
18:17:46 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
19:24:30 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
19:24:30 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
19:24:48 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
20:04:21 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:04:21 INFO  : 'fpga -state' command is executed.
20:04:21 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:04:22 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
20:04:22 INFO  : 'jtag frequency' command is executed.
20:04:22 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
20:04:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:04:22 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
20:04:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:04:22 INFO  : 'stop' command is executed.
20:04:23 INFO  : 'ps7_init' command is executed.
20:04:23 INFO  : 'ps7_post_config' command is executed.
20:04:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:04:23 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
20:04:23 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:04:25 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
20:04:25 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

20:04:26 INFO  : Memory regions updated for context APU
20:04:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:04:26 INFO  : 'con' command is executed.
20:04:26 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

20:04:26 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
20:07:43 INFO  : Disconnected from the channel tcfchan#1.
20:07:44 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:07:44 INFO  : 'fpga -state' command is executed.
20:07:44 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:07:44 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
20:07:44 INFO  : 'jtag frequency' command is executed.
20:07:44 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
20:07:44 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:07:49 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
20:07:49 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:07:49 INFO  : 'stop' command is executed.
20:07:50 INFO  : 'ps7_init' command is executed.
20:07:50 INFO  : 'ps7_post_config' command is executed.
20:07:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:07:50 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
20:07:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:07:53 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
20:07:53 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

20:07:53 INFO  : Memory regions updated for context APU
20:07:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:07:53 INFO  : 'con' command is executed.
20:07:53 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

20:07:53 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
20:13:33 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:13:33 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:13:50 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
20:23:36 INFO  : Disconnected from the channel tcfchan#2.
20:23:37 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:23:37 INFO  : 'fpga -state' command is executed.
20:23:37 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:23:37 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
20:23:37 INFO  : 'jtag frequency' command is executed.
20:23:37 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
20:23:37 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:23:42 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
20:23:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:23:42 INFO  : 'stop' command is executed.
20:23:43 INFO  : 'ps7_init' command is executed.
20:23:43 INFO  : 'ps7_post_config' command is executed.
20:23:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:23:43 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
20:23:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:23:46 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
20:23:46 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

20:23:46 INFO  : Memory regions updated for context APU
20:23:46 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:23:46 INFO  : 'con' command is executed.
20:23:46 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

20:23:46 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
20:31:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:31:25 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:31:42 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
20:31:52 INFO  : Disconnected from the channel tcfchan#3.
20:31:52 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:31:52 INFO  : 'fpga -state' command is executed.
20:31:52 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:31:52 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
20:31:52 INFO  : 'jtag frequency' command is executed.
20:31:52 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
20:31:52 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:31:57 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
20:31:57 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:31:57 INFO  : 'stop' command is executed.
20:31:58 INFO  : 'ps7_init' command is executed.
20:31:58 INFO  : 'ps7_post_config' command is executed.
20:31:58 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:31:58 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
20:31:58 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:32:00 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
20:32:00 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

20:32:00 INFO  : Memory regions updated for context APU
20:32:00 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:32:00 INFO  : 'con' command is executed.
20:32:00 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

20:32:00 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
20:44:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:44:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:44:34 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
20:45:02 INFO  : Disconnected from the channel tcfchan#4.
20:45:03 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:45:03 INFO  : 'fpga -state' command is executed.
20:45:03 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:45:03 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
20:45:03 INFO  : 'jtag frequency' command is executed.
20:45:03 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
20:45:03 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:45:08 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
20:45:08 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
20:45:08 INFO  : 'stop' command is executed.
20:45:09 INFO  : 'ps7_init' command is executed.
20:45:09 INFO  : 'ps7_post_config' command is executed.
20:45:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:45:09 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
20:45:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:45:12 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
20:45:12 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

20:45:12 INFO  : Memory regions updated for context APU
20:45:12 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
20:45:12 INFO  : 'con' command is executed.
20:45:12 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

20:45:12 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
20:49:21 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
20:49:21 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
20:49:38 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
21:00:51 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
21:00:52 INFO  : XSDB server has started successfully.
21:00:52 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
21:00:57 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
21:01:20 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
21:01:20 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
21:01:38 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
21:01:47 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
21:01:47 INFO  : 'fpga -state' command is executed.
21:01:47 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
21:01:48 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
21:01:48 INFO  : 'jtag frequency' command is executed.
21:01:48 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
21:01:48 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
21:01:48 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
21:01:48 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
21:01:48 INFO  : 'stop' command is executed.
21:01:49 INFO  : 'ps7_init' command is executed.
21:01:49 INFO  : 'ps7_post_config' command is executed.
21:01:49 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
21:01:49 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
21:01:49 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
21:01:51 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
21:01:51 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

21:01:51 INFO  : Memory regions updated for context APU
21:01:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
21:01:51 INFO  : 'con' command is executed.
21:01:51 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

21:01:51 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
21:04:27 INFO  : Disconnected from the channel tcfchan#1.
09:35:51 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
09:35:53 INFO  : XSDB server has started successfully.
09:35:53 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
09:35:54 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
15:34:00 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
15:34:08 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
15:34:12 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
15:34:29 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
16:20:31 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:20:31 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:20:48 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
16:55:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:55:16 INFO  : 'fpga -state' command is executed.
16:55:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:55:16 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:55:16 INFO  : 'jtag frequency' command is executed.
16:55:16 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:55:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:55:16 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:55:16 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:55:16 INFO  : 'stop' command is executed.
16:55:17 INFO  : 'ps7_init' command is executed.
16:55:17 INFO  : 'ps7_post_config' command is executed.
16:55:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:55:17 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:55:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:55:20 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:55:20 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:55:20 INFO  : Memory regions updated for context APU
16:55:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:55:20 INFO  : 'con' command is executed.
16:55:20 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:55:20 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
16:57:35 INFO  : Disconnected from the channel tcfchan#1.
16:57:35 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:57:35 INFO  : 'fpga -state' command is executed.
16:57:35 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:57:35 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:57:35 INFO  : 'jtag frequency' command is executed.
16:57:35 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:57:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:57:39 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:57:39 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:57:39 INFO  : 'stop' command is executed.
16:57:40 INFO  : 'ps7_init' command is executed.
16:57:41 INFO  : 'ps7_post_config' command is executed.
16:57:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:57:41 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:57:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:57:43 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:57:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:57:43 INFO  : Memory regions updated for context APU
16:57:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:57:43 INFO  : 'con' command is executed.
16:57:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:57:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:13:58 INFO  : Disconnected from the channel tcfchan#2.
17:13:58 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:13:58 INFO  : 'fpga -state' command is executed.
17:13:58 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:13:58 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:13:58 INFO  : 'jtag frequency' command is executed.
17:13:58 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:13:58 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:14:02 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:14:03 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:14:03 INFO  : 'stop' command is executed.
17:14:04 INFO  : 'ps7_init' command is executed.
17:14:04 INFO  : 'ps7_post_config' command is executed.
17:14:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:14:04 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:14:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:14:06 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:14:06 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:14:06 INFO  : Memory regions updated for context APU
17:14:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:14:06 INFO  : 'con' command is executed.
17:14:06 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:14:06 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:16:10 INFO  : Disconnected from the channel tcfchan#3.
17:16:10 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:16:10 INFO  : 'fpga -state' command is executed.
17:16:10 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:16:11 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:16:11 INFO  : 'jtag frequency' command is executed.
17:16:11 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:16:11 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:16:15 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:16:15 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:16:15 INFO  : 'stop' command is executed.
17:16:17 INFO  : 'ps7_init' command is executed.
17:16:17 INFO  : 'ps7_post_config' command is executed.
17:16:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:16:17 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:16:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:16:19 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:16:19 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:16:19 INFO  : Memory regions updated for context APU
17:16:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:16:19 INFO  : 'con' command is executed.
17:16:19 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:16:19 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:17:13 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:17:14 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:17:31 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:19:34 INFO  : Disconnected from the channel tcfchan#4.
18:19:34 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:19:34 INFO  : 'fpga -state' command is executed.
18:19:34 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:19:35 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:19:35 INFO  : 'jtag frequency' command is executed.
18:19:35 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:19:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:19:40 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:19:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:19:40 INFO  : 'stop' command is executed.
18:19:41 INFO  : 'ps7_init' command is executed.
18:19:41 INFO  : 'ps7_post_config' command is executed.
18:19:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:19:41 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:19:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:19:43 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:19:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:19:43 INFO  : Memory regions updated for context APU
18:19:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:19:43 INFO  : 'con' command is executed.
18:19:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:19:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:20:26 INFO  : Disconnected from the channel tcfchan#5.
18:20:26 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:20:26 INFO  : 'fpga -state' command is executed.
18:20:26 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:20:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:20:26 INFO  : 'jtag frequency' command is executed.
18:20:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:20:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:20:31 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:20:31 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:20:31 INFO  : 'stop' command is executed.
18:20:33 INFO  : 'ps7_init' command is executed.
18:20:33 INFO  : 'ps7_post_config' command is executed.
18:20:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:20:33 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:20:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:20:35 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:20:35 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:20:35 INFO  : Memory regions updated for context APU
18:20:35 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:20:35 INFO  : 'con' command is executed.
18:20:35 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:20:35 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:35:12 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:35:12 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:35:29 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
18:35:58 INFO  : Disconnected from the channel tcfchan#6.
18:35:59 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:35:59 INFO  : 'fpga -state' command is executed.
18:35:59 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:35:59 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:35:59 INFO  : 'jtag frequency' command is executed.
18:35:59 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:35:59 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:36:04 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:36:04 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:36:04 INFO  : 'stop' command is executed.
18:36:05 INFO  : 'ps7_init' command is executed.
18:36:05 INFO  : 'ps7_post_config' command is executed.
18:36:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:36:05 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:36:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:36:07 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:36:07 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:36:07 INFO  : Memory regions updated for context APU
18:36:07 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:36:07 INFO  : 'con' command is executed.
18:36:07 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:36:07 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
18:36:18 INFO  : Disconnected from the channel tcfchan#7.
18:36:19 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
18:36:19 INFO  : 'fpga -state' command is executed.
18:36:19 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
18:36:19 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
18:36:19 INFO  : 'jtag frequency' command is executed.
18:36:19 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
18:36:19 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:36:24 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
18:36:24 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
18:36:24 INFO  : 'stop' command is executed.
18:36:25 INFO  : 'ps7_init' command is executed.
18:36:25 INFO  : 'ps7_post_config' command is executed.
18:36:25 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:36:25 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
18:36:25 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:36:27 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
18:36:27 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

18:36:28 INFO  : Memory regions updated for context APU
18:36:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
18:36:28 INFO  : 'con' command is executed.
18:36:28 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

18:36:28 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
07:46:43 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:46:43 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
07:47:00 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
07:51:03 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:51:04 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
07:51:20 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
07:52:11 INFO  : Disconnected from the channel tcfchan#8.
07:52:12 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
07:52:12 INFO  : 'fpga -state' command is executed.
07:52:12 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:52:12 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
07:52:12 INFO  : 'jtag frequency' command is executed.
07:52:12 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
07:52:12 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:52:17 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
07:52:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:52:17 INFO  : 'stop' command is executed.
07:52:18 INFO  : 'ps7_init' command is executed.
07:52:18 INFO  : 'ps7_post_config' command is executed.
07:52:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:52:18 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
07:52:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:52:20 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
07:52:20 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

07:52:20 INFO  : Memory regions updated for context APU
07:52:20 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:52:20 INFO  : 'con' command is executed.
07:52:20 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

07:52:20 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
07:52:34 INFO  : Disconnected from the channel tcfchan#9.
07:52:35 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
07:52:35 INFO  : 'fpga -state' command is executed.
07:52:35 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:52:35 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
07:52:35 INFO  : 'jtag frequency' command is executed.
07:52:35 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
07:52:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:52:40 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
07:52:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:52:40 INFO  : 'stop' command is executed.
07:52:41 INFO  : 'ps7_init' command is executed.
07:52:41 INFO  : 'ps7_post_config' command is executed.
07:52:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:52:41 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
07:52:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:52:43 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
07:52:43 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

07:52:43 INFO  : Memory regions updated for context APU
07:52:43 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:52:43 INFO  : 'con' command is executed.
07:52:43 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

07:52:43 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
07:54:58 INFO  : Disconnected from the channel tcfchan#10.
07:54:58 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
07:54:58 INFO  : 'fpga -state' command is executed.
07:55:00 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:55:00 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
07:55:00 INFO  : 'jtag frequency' command is executed.
07:55:00 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
07:55:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:55:05 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
07:55:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:55:05 INFO  : 'stop' command is executed.
07:55:06 INFO  : 'ps7_init' command is executed.
07:55:06 INFO  : 'ps7_post_config' command is executed.
07:55:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:55:06 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
07:55:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:55:09 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
07:55:09 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

07:55:09 INFO  : Memory regions updated for context APU
07:55:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:55:09 INFO  : 'con' command is executed.
07:55:09 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

07:55:09 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
07:55:17 INFO  : Disconnected from the channel tcfchan#11.
07:55:17 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
07:55:17 INFO  : 'fpga -state' command is executed.
07:55:19 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
07:55:19 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
07:55:19 INFO  : 'jtag frequency' command is executed.
07:55:19 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
07:55:19 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:55:24 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
07:55:24 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
07:55:24 INFO  : 'stop' command is executed.
07:55:26 INFO  : 'ps7_init' command is executed.
07:55:26 INFO  : 'ps7_post_config' command is executed.
07:55:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:55:26 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
07:55:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:55:28 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
07:55:28 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

07:55:28 INFO  : Memory regions updated for context APU
07:55:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
07:55:28 INFO  : 'con' command is executed.
07:55:28 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

07:55:28 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:03:27 INFO  : Disconnected from the channel tcfchan#12.
08:03:27 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:03:27 INFO  : 'fpga -state' command is executed.
08:03:30 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:03:30 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:03:30 INFO  : 'jtag frequency' command is executed.
08:03:30 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:03:30 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:03:35 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:03:35 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:03:36 INFO  : 'stop' command is executed.
08:03:36 INFO  : 'ps7_init' command is executed.
08:03:36 INFO  : 'ps7_post_config' command is executed.
08:03:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:03:37 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:03:37 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:03:39 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:03:39 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:03:39 INFO  : Memory regions updated for context APU
08:03:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:03:39 INFO  : 'con' command is executed.
08:03:39 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:03:39 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:03:48 INFO  : Disconnected from the channel tcfchan#13.
08:03:48 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:03:48 INFO  : 'fpga -state' command is executed.
08:03:54 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:03:55 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:03:55 INFO  : 'jtag frequency' command is executed.
08:03:55 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:03:55 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:04:00 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:04:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:04:00 INFO  : 'stop' command is executed.
08:04:01 INFO  : 'ps7_init' command is executed.
08:04:01 INFO  : 'ps7_post_config' command is executed.
08:04:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:04:01 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:04:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:04:03 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:04:03 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:04:03 INFO  : Memory regions updated for context APU
08:04:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:04:03 INFO  : 'con' command is executed.
08:04:03 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:04:03 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:06:36 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:06:36 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:06:53 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:06:59 INFO  : Disconnected from the channel tcfchan#14.
08:07:00 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:07:00 INFO  : 'fpga -state' command is executed.
08:07:00 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:07:00 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:07:00 INFO  : 'jtag frequency' command is executed.
08:07:00 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:07:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:07:05 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:07:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:07:05 INFO  : 'stop' command is executed.
08:07:06 INFO  : 'ps7_init' command is executed.
08:07:06 INFO  : 'ps7_post_config' command is executed.
08:07:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:07:06 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:07:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:07:08 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:07:08 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:07:09 INFO  : Memory regions updated for context APU
08:07:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:07:09 INFO  : 'con' command is executed.
08:07:09 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:07:09 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:07:54 INFO  : Disconnected from the channel tcfchan#15.
08:07:54 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:07:54 INFO  : 'fpga -state' command is executed.
08:07:54 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:07:54 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:07:54 INFO  : 'jtag frequency' command is executed.
08:07:54 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:07:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:08:00 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:08:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:08:00 INFO  : 'stop' command is executed.
08:08:01 INFO  : 'ps7_init' command is executed.
08:08:01 INFO  : 'ps7_post_config' command is executed.
08:08:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:08:01 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:08:01 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:08:03 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:08:03 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:08:03 INFO  : Memory regions updated for context APU
08:08:03 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:08:03 INFO  : 'con' command is executed.
08:08:03 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:08:03 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:13:41 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:13:42 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:13:58 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:14:18 INFO  : Disconnected from the channel tcfchan#16.
08:14:18 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:14:18 INFO  : 'fpga -state' command is executed.
08:14:18 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:14:19 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:14:19 INFO  : 'jtag frequency' command is executed.
08:14:19 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:14:19 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:14:24 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:14:24 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:14:24 INFO  : 'stop' command is executed.
08:14:25 INFO  : 'ps7_init' command is executed.
08:14:26 INFO  : 'ps7_post_config' command is executed.
08:14:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:14:26 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:14:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:14:28 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:14:28 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:14:28 INFO  : Memory regions updated for context APU
08:14:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:14:28 INFO  : 'con' command is executed.
08:14:28 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:14:28 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:14:40 INFO  : Disconnected from the channel tcfchan#17.
08:14:40 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:14:40 INFO  : 'fpga -state' command is executed.
08:14:40 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:14:41 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:14:41 INFO  : 'jtag frequency' command is executed.
08:14:41 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:14:41 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:14:46 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:14:46 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:14:46 INFO  : 'stop' command is executed.
08:14:47 INFO  : 'ps7_init' command is executed.
08:14:47 INFO  : 'ps7_post_config' command is executed.
08:14:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:14:47 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:14:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:14:50 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:14:50 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:14:50 INFO  : Memory regions updated for context APU
08:14:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:14:50 INFO  : 'con' command is executed.
08:14:50 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:14:50 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:16:14 INFO  : Disconnected from the channel tcfchan#18.
08:16:14 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:16:14 INFO  : 'fpga -state' command is executed.
08:16:17 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:16:18 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:16:18 INFO  : 'jtag frequency' command is executed.
08:16:18 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:16:18 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:16:23 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:16:23 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:16:23 INFO  : 'stop' command is executed.
08:16:24 INFO  : 'ps7_init' command is executed.
08:16:24 INFO  : 'ps7_post_config' command is executed.
08:16:24 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:16:24 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:16:24 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:16:26 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:16:26 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:16:26 INFO  : Memory regions updated for context APU
08:16:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:16:26 INFO  : 'con' command is executed.
08:16:26 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:16:26 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:16:38 INFO  : Disconnected from the channel tcfchan#19.
08:16:38 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:16:38 INFO  : 'fpga -state' command is executed.
08:16:41 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:16:41 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:16:41 INFO  : 'jtag frequency' command is executed.
08:16:41 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:16:41 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:16:46 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:16:46 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:16:46 INFO  : 'stop' command is executed.
08:16:47 INFO  : 'ps7_init' command is executed.
08:16:47 INFO  : 'ps7_post_config' command is executed.
08:16:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:16:47 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:16:47 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:16:50 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:16:50 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:16:50 INFO  : Memory regions updated for context APU
08:16:50 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:16:50 INFO  : 'con' command is executed.
08:16:50 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:16:50 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:18:37 INFO  : Disconnected from the channel tcfchan#20.
08:18:37 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:18:37 INFO  : 'fpga -state' command is executed.
08:18:38 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:18:38 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:18:38 INFO  : 'jtag frequency' command is executed.
08:18:38 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:18:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:18:44 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:18:44 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:18:44 INFO  : 'stop' command is executed.
08:18:45 INFO  : 'ps7_init' command is executed.
08:18:45 INFO  : 'ps7_post_config' command is executed.
08:18:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:18:45 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:18:45 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:18:48 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:18:48 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:18:48 INFO  : Memory regions updated for context APU
08:18:48 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:18:48 INFO  : 'con' command is executed.
08:18:48 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:18:48 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:20:00 INFO  : Disconnected from the channel tcfchan#21.
08:20:01 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:20:01 INFO  : 'fpga -state' command is executed.
08:20:06 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:20:06 INFO  : 'fpga -state' command is executed.
08:20:07 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:20:08 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:20:08 INFO  : 'jtag frequency' command is executed.
08:20:08 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:20:08 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:20:13 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:20:13 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:20:13 INFO  : 'stop' command is executed.
08:20:14 INFO  : 'ps7_init' command is executed.
08:20:14 INFO  : 'ps7_post_config' command is executed.
08:20:14 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:20:14 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:20:14 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:20:16 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:20:16 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:20:16 INFO  : Memory regions updated for context APU
08:20:16 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:20:16 INFO  : 'con' command is executed.
08:20:16 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:20:16 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:22:45 INFO  : Disconnected from the channel tcfchan#22.
08:22:45 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:22:45 INFO  : 'fpga -state' command is executed.
08:22:48 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:22:48 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:22:48 INFO  : 'jtag frequency' command is executed.
08:22:48 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:22:48 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:22:54 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:22:54 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:22:54 INFO  : 'stop' command is executed.
08:22:55 INFO  : 'ps7_init' command is executed.
08:22:55 INFO  : 'ps7_post_config' command is executed.
08:22:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:22:55 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:22:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:22:57 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:22:57 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:22:57 INFO  : Memory regions updated for context APU
08:22:57 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:22:57 INFO  : 'con' command is executed.
08:22:57 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:22:57 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:24:02 INFO  : Disconnected from the channel tcfchan#23.
08:24:02 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:24:03 INFO  : 'fpga -state' command is executed.
08:24:05 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:24:05 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:24:05 INFO  : 'jtag frequency' command is executed.
08:24:05 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:24:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:24:09 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:24:10 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:24:10 INFO  : 'stop' command is executed.
08:24:11 INFO  : 'ps7_init' command is executed.
08:24:11 INFO  : 'ps7_post_config' command is executed.
08:24:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:11 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:24:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:13 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:24:13 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:24:13 INFO  : Memory regions updated for context APU
08:24:13 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:13 INFO  : 'con' command is executed.
08:24:13 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:24:13 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
08:24:22 INFO  : Disconnected from the channel tcfchan#24.
08:24:22 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:24:22 INFO  : 'fpga -state' command is executed.
08:24:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:24:25 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:24:25 INFO  : 'jtag frequency' command is executed.
08:24:25 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:24:25 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:24:30 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:24:30 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:24:30 INFO  : 'stop' command is executed.
08:24:31 INFO  : 'ps7_init' command is executed.
08:24:31 INFO  : 'ps7_post_config' command is executed.
08:24:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:31 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:24:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:34 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:24:34 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

08:24:34 INFO  : Memory regions updated for context APU
08:24:34 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:24:34 INFO  : 'con' command is executed.
08:24:34 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:24:34 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
12:48:29 INFO  : Disconnected from the channel tcfchan#25.
08:09:32 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
08:09:33 INFO  : XSDB server has started successfully.
08:09:33 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
08:09:33 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
08:09:37 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1476857031000,  Project:1472657763000
08:09:37 INFO  : The hardware specification for project 'system_design_wrapper_hw_platform_0' is different from /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
08:09:37 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
08:09:44 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-ntpd.service-GlYC5l"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-colord.service-OrMFU2"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-rtkit-daemon.service-P2BMUk"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-ntpd.service-0uaYVW"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-colord.service-SIeBhJ"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-rtkit-daemon.service-HTwTaV"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-ntpd.service-HNREQo"

08:09:44 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-colord.service-jXmCG5"

08:09:45 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-rtkit-daemon.service-n0ghHp"

08:09:45 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

08:09:45 ERROR : Error updating BSP project MSS files.
08:09:46 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
08:09:47 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
08:09:48 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
08:09:49 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
08:09:49 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
08:09:49 INFO  : Clearing existing target manager status.
08:30:02 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1476858428000,  Project:1476857031000
08:30:02 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
08:30:04 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
08:30:12 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-ntpd.service-GlYC5l"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-colord.service-OrMFU2"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-rtkit-daemon.service-P2BMUk"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-ntpd.service-0uaYVW"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-colord.service-SIeBhJ"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-rtkit-daemon.service-HTwTaV"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-ntpd.service-HNREQo"

08:30:12 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-colord.service-jXmCG5"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-rtkit-daemon.service-n0ghHp"

08:30:12 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

08:30:13 ERROR : Error updating BSP project MSS files.
08:30:14 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
08:30:14 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
08:30:15 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
08:30:16 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
08:30:17 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
08:30:17 INFO  : Clearing existing target manager status.
08:30:17 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
08:30:26 WARN  : Linker script will not be updated automatically. Users need to update it manually.
08:34:40 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:34:40 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:34:57 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
08:35:20 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

08:35:20 ERROR :  [Common 17-39] 'hsi::current_sw_design' failed due to earlier errors.
08:35:20 ERROR : (XSDB Server)ERROR: [Hsi 55-1558] Software Design system system is not found

08:35:20 INFO  : Unable to read in MSS file /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/standalone_bsp_0/system.mss : null
08:35:20 ERROR : Failed to closesw "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/standalone_bsp_0/system.mss"
Reason: Cannot close sw design '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/standalone_bsp_0/system.mss'.
Design is not opened in the current session.


08:35:26 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:35:26 INFO  : 'fpga -state' command is executed.
08:35:26 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:35:27 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:35:27 INFO  : 'jtag frequency' command is executed.
08:35:27 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:35:27 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:35:27 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:35:27 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:35:27 INFO  : 'stop' command is executed.
08:35:28 INFO  : 'ps7_init' command is executed.
08:35:28 INFO  : 'ps7_post_config' command is executed.
08:35:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:35:28 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:35:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:35:30 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:35:30 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

08:35:30 INFO  : Memory regions updated for context APU
08:35:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:35:30 INFO  : 'con' command is executed.
08:35:30 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:35:30 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
08:44:24 INFO  : Disconnected from the channel tcfchan#1.
08:44:24 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
08:44:24 INFO  : 'fpga -state' command is executed.
08:44:24 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
08:44:24 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
08:44:24 INFO  : 'jtag frequency' command is executed.
08:44:24 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
08:44:24 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:44:24 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
08:44:24 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
08:44:24 INFO  : 'stop' command is executed.
08:44:25 INFO  : 'ps7_init' command is executed.
08:44:25 INFO  : 'ps7_post_config' command is executed.
08:44:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:44:26 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
08:44:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:44:27 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
08:44:27 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

08:44:27 INFO  : Memory regions updated for context APU
08:44:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
08:44:27 INFO  : 'con' command is executed.
08:44:27 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

08:44:27 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:11:09 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1476860887000,  Project:1476858428000
09:11:09 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
09:11:12 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
09:11:21 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-ntpd.service-GlYC5l"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-colord.service-OrMFU2"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-rtkit-daemon.service-P2BMUk"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-ntpd.service-0uaYVW"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-colord.service-SIeBhJ"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-rtkit-daemon.service-HTwTaV"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-ntpd.service-HNREQo"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-colord.service-jXmCG5"

09:11:21 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-rtkit-daemon.service-n0ghHp"

09:11:21 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

09:11:21 ERROR : Error updating BSP project MSS files.
09:11:22 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
09:11:23 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
09:11:24 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
09:11:24 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
09:11:25 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
09:11:25 INFO  : Clearing existing target manager status.
09:11:25 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
09:11:26 WARN  : Linker script will not be updated automatically. Users need to update it manually.
09:12:26 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:12:26 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:12:43 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:12:50 INFO  : Disconnected from the channel tcfchan#2.
09:12:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:12:51 INFO  : 'fpga -state' command is executed.
09:12:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:12:51 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:12:51 INFO  : 'jtag frequency' command is executed.
09:12:51 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:12:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:12:51 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:12:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:12:51 INFO  : 'stop' command is executed.
09:12:52 INFO  : 'ps7_init' command is executed.
09:12:52 INFO  : 'ps7_post_config' command is executed.
09:12:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:12:52 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:12:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:12:54 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:12:54 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:12:54 INFO  : Memory regions updated for context APU
09:12:54 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:12:54 INFO  : 'con' command is executed.
09:12:54 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:12:54 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:37:51 INFO  : Disconnected from the channel tcfchan#3.
09:37:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:37:51 INFO  : 'fpga -state' command is executed.
09:37:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:37:51 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:37:51 INFO  : 'jtag frequency' command is executed.
09:37:51 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:37:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:37:51 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:37:51 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:37:51 INFO  : 'stop' command is executed.
09:37:52 INFO  : 'ps7_init' command is executed.
09:37:52 INFO  : 'ps7_post_config' command is executed.
09:37:52 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:37:53 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:37:53 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:37:54 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:37:54 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:37:54 INFO  : Memory regions updated for context APU
09:37:54 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:37:54 INFO  : 'con' command is executed.
09:37:54 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:37:54 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:41:52 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:41:52 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:42:09 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
09:42:16 INFO  : Disconnected from the channel tcfchan#4.
09:42:16 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:42:16 INFO  : 'fpga -state' command is executed.
09:42:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:42:17 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:42:17 INFO  : 'jtag frequency' command is executed.
09:42:17 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:42:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:42:17 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:42:17 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:42:17 INFO  : 'stop' command is executed.
09:42:18 INFO  : 'ps7_init' command is executed.
09:42:18 INFO  : 'ps7_post_config' command is executed.
09:42:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:42:18 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:42:18 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:42:19 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:42:19 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:42:19 INFO  : Memory regions updated for context APU
09:42:19 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:42:19 INFO  : 'con' command is executed.
09:42:19 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:42:19 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:51:25 INFO  : Disconnected from the channel tcfchan#5.
09:51:25 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:51:25 INFO  : 'fpga -state' command is executed.
09:51:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:51:26 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:51:26 INFO  : 'jtag frequency' command is executed.
09:51:26 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:51:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:51:26 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:51:26 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:51:26 INFO  : 'stop' command is executed.
09:51:27 INFO  : 'ps7_init' command is executed.
09:51:27 INFO  : 'ps7_post_config' command is executed.
09:51:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:51:27 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:51:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:51:28 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:51:28 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:51:28 INFO  : Memory regions updated for context APU
09:51:29 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:51:29 INFO  : 'con' command is executed.
09:51:29 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:51:29 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
09:52:08 INFO  : Disconnected from the channel tcfchan#6.
09:52:08 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
09:52:08 INFO  : 'fpga -state' command is executed.
09:52:08 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
09:52:08 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
09:52:08 INFO  : 'jtag frequency' command is executed.
09:52:08 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
09:52:08 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:52:08 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
09:52:08 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
09:52:09 INFO  : 'stop' command is executed.
09:52:10 INFO  : 'ps7_init' command is executed.
09:52:10 INFO  : 'ps7_post_config' command is executed.
09:52:10 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:52:10 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
09:52:10 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:52:11 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
09:52:11 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

09:52:11 INFO  : Memory regions updated for context APU
09:52:11 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
09:52:11 INFO  : 'con' command is executed.
09:52:11 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

09:52:11 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
10:02:37 INFO  : Disconnected from the channel tcfchan#7.
10:02:38 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:02:38 INFO  : 'fpga -state' command is executed.
10:02:38 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:02:38 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:02:38 INFO  : 'jtag frequency' command is executed.
10:02:38 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:02:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:02:38 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:02:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:02:38 INFO  : 'stop' command is executed.
10:02:39 INFO  : 'ps7_init' command is executed.
10:02:39 INFO  : 'ps7_post_config' command is executed.
10:02:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:02:39 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:02:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:02:41 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:02:41 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

10:02:41 INFO  : Memory regions updated for context APU
10:02:41 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:02:41 INFO  : 'con' command is executed.
10:02:41 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:02:41 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
10:14:05 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1476864796000,  Project:1476860887000
10:14:05 INFO  : Project system_design_wrapper_hw_platform_0's source hardware specification located at /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf is now different from the local copy.
		 The local copy will be replaced with the source specification and your workspace will be updated.
10:14:07 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
10:14:15 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
10:14:16 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

10:14:16 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

10:14:16 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

10:14:16 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

10:14:16 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-ntpd.service-GlYC5l"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-colord.service-OrMFU2"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-rtkit-daemon.service-P2BMUk"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-ntpd.service-0uaYVW"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-colord.service-SIeBhJ"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-rtkit-daemon.service-HTwTaV"

10:14:16 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-ntpd.service-HNREQo"

10:14:16 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-colord.service-jXmCG5"

10:14:16 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-a91a2f63fe0b4084ab257b59ccbf692e-rtkit-daemon.service-n0ghHp"

10:14:16 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

10:14:16 ERROR : Error updating BSP project MSS files.
10:14:16 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
10:14:17 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
10:14:18 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
10:14:19 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
10:14:19 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
10:14:19 INFO  : Clearing existing target manager status.
10:14:19 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
10:14:20 WARN  : Linker script will not be updated automatically. Users need to update it manually.
10:14:46 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:14:46 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:15:04 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
10:16:10 INFO  : Disconnected from the channel tcfchan#8.
10:16:11 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:16:11 INFO  : 'fpga -state' command is executed.
10:16:11 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:16:11 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:16:11 INFO  : 'jtag frequency' command is executed.
10:16:11 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:16:11 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:16:11 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:16:11 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:16:11 INFO  : 'stop' command is executed.
10:16:12 INFO  : 'ps7_init' command is executed.
10:16:12 INFO  : 'ps7_post_config' command is executed.
10:16:12 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:16:12 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:16:12 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:16:14 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:16:14 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

10:16:14 INFO  : Memory regions updated for context APU
10:16:14 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:16:14 INFO  : 'con' command is executed.
10:16:14 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:16:14 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
10:35:59 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:36:00 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:36:17 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
10:36:25 INFO  : Disconnected from the channel tcfchan#9.
10:36:25 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
10:36:25 INFO  : 'fpga -state' command is executed.
10:36:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
10:36:25 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
10:36:25 INFO  : 'jtag frequency' command is executed.
10:36:25 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
10:36:25 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:36:25 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
10:36:25 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
10:36:25 INFO  : 'stop' command is executed.
10:36:26 INFO  : 'ps7_init' command is executed.
10:36:26 INFO  : 'ps7_post_config' command is executed.
10:36:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:36:26 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
10:36:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:36:28 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
10:36:28 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

10:36:28 INFO  : Memory regions updated for context APU
10:36:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
10:36:28 INFO  : 'con' command is executed.
10:36:28 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

10:36:28 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
15:11:46 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
15:11:47 INFO  : XSDB server has started successfully.
15:11:48 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
15:11:48 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
17:32:22 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
17:32:25 INFO  : XSDB server has started successfully.
17:32:25 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
17:32:25 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
17:32:30 INFO  : SDK has detected change in the last modified timestamps for source hardware specification file Source:1476977360000,  Project:1476864796000
17:32:30 INFO  : The hardware specification for project 'system_design_wrapper_hw_platform_0' is different from /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
17:32:30 INFO  : Copied contents of /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf into /system_design_wrapper_hw_platform_0/system.hdf.
17:32:41 INFO  : Synchronizing projects in the workspace with the hardware platform specification changes.
17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/.esd-483"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-ntpd.service-YHpD0s"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-colord.service-SBYSOj"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f6fdbb2e19194308b58963bd22a13eaf-rtkit-daemon.service-05N4oo"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-06188aed88844c8ca16e38f612c3d2b2-ntpd.service-GcLfav"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-ntpd.service-GlYC5l"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-colord.service-OrMFU2"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-30baa8a09fe44c7e81d3c4551379caf1-rtkit-daemon.service-P2BMUk"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-ntpd.service-0uaYVW"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-colord.service-SIeBhJ"
ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-9ddcfc68a0e5432bab5de72ad81270d3-rtkit-daemon.service-HTwTaV"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f2144cc8ac4c49668bcad2c4fa465d41-ntpd.service-EKQYiB"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f2144cc8ac4c49668bcad2c4fa465d41-colord.service-tGLpSF"

17:32:42 ERROR : (XSDB Server)ERROR: [Hsi 55-1433] Error boost::filesystem::directory_iterator::construct: Permission denied: "/tmp/systemd-private-f2144cc8ac4c49668bcad2c4fa465d41-rtkit-daemon.service-nhbnMH"

17:32:42 ERROR : Failed to call sync_sw_with_hw_change
Reason: ERROR: [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.

17:32:42 ERROR : Error updating BSP project MSS files.
17:32:43 INFO  : Updating hardware inferred compiler options for Dhrystone_FASEC.
17:32:44 INFO  : Updating hardware inferred compiler options for Hello_FASEC.
17:32:45 INFO  : Updating hardware inferred compiler options for I2C_tests_FASEC.
17:32:46 INFO  : Updating hardware inferred compiler options for Mem-Test_FASEC.
17:32:47 INFO  : Updating hardware inferred compiler options for Periph-Test_FASEC.
17:32:47 INFO  : Clearing existing target manager status.
17:32:50 INFO  : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
17:33:06 WARN  : Linker script will not be updated automatically. Users need to update it manually.
17:34:02 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:34:25 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:34:25 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:34:43 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
17:35:02 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:35:02 INFO  : 'fpga -state' command is executed.
17:35:02 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:35:03 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:35:03 INFO  : 'jtag frequency' command is executed.
17:35:03 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:35:03 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:35:03 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:35:03 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:35:03 INFO  : 'stop' command is executed.
17:35:04 INFO  : 'ps7_init' command is executed.
17:35:04 INFO  : 'ps7_post_config' command is executed.
17:35:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:35:04 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:35:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:35:06 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:35:06 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

17:35:06 INFO  : Memory regions updated for context APU
17:35:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:35:06 INFO  : 'con' command is executed.
17:35:06 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:35:06 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
18:28:07 INFO  : Disconnected from the channel tcfchan#1.
18:28:08 ERROR : Unexpected error while parsing XMD response : com.google.gson.JsonSyntaxException: com.google.gson.stream.MalformedJsonException: invalid number or unquoted string near 
12:49:22 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
12:49:24 INFO  : XSDB server has started successfully.
12:49:25 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
12:49:28 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
16:03:50 INFO  : Launching XSDB server: xsdb -n -interactive /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/temp_xsdb_launch_script.tcl
16:03:52 INFO  : XSDB server has started successfully.
16:03:53 INFO  : Processing command line option -hwspec /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper.hdf.
16:03:55 INFO  : Checking for hwspec changes in the project system_design_wrapper_hw_platform_0.
16:27:16 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:27:41 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:27:41 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:27:59 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
16:28:59 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:28:59 INFO  : 'fpga -state' command is executed.
16:28:59 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:29:00 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:29:00 INFO  : 'jtag frequency' command is executed.
16:29:00 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:29:00 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:29:01 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:29:01 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:29:01 INFO  : 'stop' command is executed.
16:29:02 INFO  : 'ps7_init' command is executed.
16:29:02 INFO  : 'ps7_post_config' command is executed.
16:29:02 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:29:02 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:29:02 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:29:04 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:29:04 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/I2C_tests_FASEC/Debug/I2C_tests_FASEC.elf
----------------End of Script----------------

16:29:04 INFO  : Memory regions updated for context APU
16:29:04 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:29:04 INFO  : 'con' command is executed.
16:29:04 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:29:04 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_i2c_tests_fasec.elf.tcl'
16:33:18 INFO  : Disconnected from the channel tcfchan#1.
16:33:19 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:33:19 INFO  : 'fpga -state' command is executed.
16:33:19 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:33:19 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:33:19 INFO  : 'jtag frequency' command is executed.
16:33:19 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:33:19 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:33:24 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:33:24 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:33:24 INFO  : 'stop' command is executed.
16:33:25 INFO  : 'ps7_init' command is executed.
16:33:25 INFO  : 'ps7_post_config' command is executed.
16:33:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:33:26 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:33:26 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:33:28 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:33:28 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:33:28 INFO  : Memory regions updated for context APU
16:33:28 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:33:28 INFO  : 'con' command is executed.
16:33:28 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:33:28 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
16:36:49 INFO  : Disconnected from the channel tcfchan#2.
16:36:49 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:36:50 INFO  : 'fpga -state' command is executed.
16:36:50 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:36:50 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:36:50 INFO  : 'jtag frequency' command is executed.
16:36:50 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:36:50 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:36:55 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:36:55 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:36:55 INFO  : 'stop' command is executed.
16:36:57 INFO  : 'ps7_init' command is executed.
16:36:57 INFO  : 'ps7_post_config' command is executed.
16:36:57 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:36:57 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:36:57 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:36:59 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:36:59 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:36:59 INFO  : Memory regions updated for context APU
16:36:59 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:36:59 INFO  : 'con' command is executed.
16:36:59 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:36:59 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
16:43:22 INFO  : Disconnected from the channel tcfchan#3.
16:43:22 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:43:22 INFO  : 'fpga -state' command is executed.
16:43:22 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:43:22 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:43:22 INFO  : 'jtag frequency' command is executed.
16:43:22 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:43:22 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:43:28 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:43:28 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:43:28 INFO  : 'stop' command is executed.
16:43:29 INFO  : 'ps7_init' command is executed.
16:43:29 INFO  : 'ps7_post_config' command is executed.
16:43:29 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:43:29 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:43:30 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:43:32 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:43:32 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:43:32 INFO  : Memory regions updated for context APU
16:43:32 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:43:32 INFO  : 'con' command is executed.
16:43:32 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:43:32 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
16:47:51 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:47:51 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:48:09 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
16:48:20 INFO  : Disconnected from the channel tcfchan#4.
16:48:20 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:48:20 INFO  : 'fpga -state' command is executed.
16:48:20 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:48:20 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:48:20 INFO  : 'jtag frequency' command is executed.
16:48:20 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:48:20 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:48:25 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:48:25 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:48:25 INFO  : 'stop' command is executed.
16:48:26 INFO  : 'ps7_init' command is executed.
16:48:26 INFO  : 'ps7_post_config' command is executed.
16:48:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:48:27 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:48:27 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:48:29 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:48:29 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:48:29 INFO  : Memory regions updated for context APU
16:48:29 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:48:29 INFO  : 'con' command is executed.
16:48:29 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:48:29 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
16:48:41 INFO  : Disconnected from the channel tcfchan#5.
16:48:42 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:48:42 INFO  : 'fpga -state' command is executed.
16:48:42 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:48:42 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:48:42 INFO  : 'jtag frequency' command is executed.
16:48:42 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:48:42 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:48:48 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:48:48 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:48:48 INFO  : 'stop' command is executed.
16:48:49 INFO  : 'ps7_init' command is executed.
16:48:49 INFO  : 'ps7_post_config' command is executed.
16:48:49 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:48:49 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:48:49 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:48:51 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:48:51 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:48:51 INFO  : Memory regions updated for context APU
16:48:51 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:48:51 INFO  : 'con' command is executed.
16:48:51 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:48:51 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
16:49:24 INFO  : Disconnected from the channel tcfchan#6.
16:49:24 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:49:24 INFO  : 'fpga -state' command is executed.
16:49:24 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:49:24 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:49:24 INFO  : 'jtag frequency' command is executed.
16:49:24 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:49:24 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:49:30 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:49:30 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:49:30 INFO  : 'stop' command is executed.
16:49:31 INFO  : 'ps7_init' command is executed.
16:49:31 INFO  : 'ps7_post_config' command is executed.
16:49:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:49:31 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:49:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:49:33 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:49:33 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:49:33 INFO  : Memory regions updated for context APU
16:49:33 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:49:33 INFO  : 'con' command is executed.
16:49:33 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:49:33 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
16:50:55 INFO  : Disconnected from the channel tcfchan#7.
16:50:56 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:50:56 INFO  : 'fpga -state' command is executed.
16:51:15 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:51:15 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:51:33 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
16:51:40 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
16:51:40 INFO  : 'fpga -state' command is executed.
16:51:40 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
16:51:40 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
16:51:40 INFO  : 'jtag frequency' command is executed.
16:51:40 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
16:51:40 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:51:40 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
16:51:41 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
16:51:41 INFO  : 'stop' command is executed.
16:51:42 INFO  : 'ps7_init' command is executed.
16:51:42 INFO  : 'ps7_post_config' command is executed.
16:51:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:51:42 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
16:51:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:51:44 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
16:51:44 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

16:51:44 INFO  : Memory regions updated for context APU
16:51:44 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
16:51:44 INFO  : 'con' command is executed.
16:51:44 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

16:51:44 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:13:13 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:13:13 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:13:30 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
17:13:58 INFO  : Disconnected from the channel tcfchan#8.
17:13:59 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:13:59 INFO  : 'fpga -state' command is executed.
17:13:59 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:13:59 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:13:59 INFO  : 'jtag frequency' command is executed.
17:13:59 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:13:59 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:14:05 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:14:05 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:14:05 INFO  : 'stop' command is executed.
17:14:06 INFO  : 'ps7_init' command is executed.
17:14:06 INFO  : 'ps7_post_config' command is executed.
17:14:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:14:06 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:14:06 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:14:09 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:14:09 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:14:09 INFO  : Memory regions updated for context APU
17:14:09 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:14:09 INFO  : 'con' command is executed.
17:14:09 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:14:09 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:17:46 INFO  : Disconnected from the channel tcfchan#9.
17:17:46 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:17:46 INFO  : 'fpga -state' command is executed.
17:17:46 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:17:47 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:17:47 INFO  : 'jtag frequency' command is executed.
17:17:47 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:17:47 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:17:53 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:17:53 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:17:53 INFO  : 'stop' command is executed.
17:17:54 INFO  : 'ps7_init' command is executed.
17:17:54 INFO  : 'ps7_post_config' command is executed.
17:17:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:17:55 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:17:55 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:17:57 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:17:57 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:17:57 INFO  : Memory regions updated for context APU
17:17:57 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:17:57 INFO  : 'con' command is executed.
17:17:57 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:17:57 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:19:58 INFO  : Disconnected from the channel tcfchan#10.
17:19:58 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:19:58 INFO  : 'fpga -state' command is executed.
17:19:58 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:19:58 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:19:58 INFO  : 'jtag frequency' command is executed.
17:19:58 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:19:58 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:20:04 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:20:04 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:20:04 INFO  : 'stop' command is executed.
17:20:05 INFO  : 'ps7_init' command is executed.
17:20:05 INFO  : 'ps7_post_config' command is executed.
17:20:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:20:05 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:20:05 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:20:08 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:20:08 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:20:08 INFO  : Memory regions updated for context APU
17:20:08 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:20:08 INFO  : 'con' command is executed.
17:20:08 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:20:08 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:20:42 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:20:42 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:20:59 INFO  : FPGA configured successfully with bitstream "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system_design_wrapper.bit"
17:22:06 INFO  : Disconnected from the channel tcfchan#11.
17:22:06 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:22:06 INFO  : 'fpga -state' command is executed.
17:22:06 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:22:07 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:22:07 INFO  : 'jtag frequency' command is executed.
17:22:07 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:22:07 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:22:13 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:22:13 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:22:13 INFO  : 'stop' command is executed.
17:22:15 INFO  : 'ps7_init' command is executed.
17:22:15 INFO  : 'ps7_post_config' command is executed.
17:22:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:22:15 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:22:15 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:22:17 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:22:17 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:22:17 INFO  : Memory regions updated for context APU
17:22:17 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:22:17 INFO  : 'con' command is executed.
17:22:17 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:22:17 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:41:31 INFO  : Disconnected from the channel tcfchan#12.
17:41:31 INFO  : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901" && level==0} -index 1' command is executed.
17:41:31 INFO  : 'fpga -state' command is executed.
17:41:31 INFO  : Connected to target on host '127.0.0.1' and port '3121'.
17:41:32 INFO  : Jtag cable 'Platform Cable USB II 0000150f6b7901' is selected.
17:41:32 INFO  : 'jtag frequency' command is executed.
17:41:32 INFO  : Sourcing of '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl' is done.
17:41:32 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:41:38 INFO  : Hardware design information is loaded from '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf'.
17:41:38 INFO  : 'targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0' command is executed.
17:41:38 INFO  : 'stop' command is executed.
17:41:39 INFO  : 'ps7_init' command is executed.
17:41:39 INFO  : 'ps7_post_config' command is executed.
17:41:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:41:39 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.
17:41:39 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:41:42 INFO  : The application '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf' is downloaded to processor 'ps7_cortexa9_0'.
17:41:42 INFO  : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/ps7_init.tcl
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
loadhw /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/system_design_wrapper_hw_platform_0/system.hdf
targets -set -filter {name =~"APU" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
dow /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/Periph-Test_FASEC/Debug/Periph-Test_FASEC.elf
----------------End of Script----------------

17:41:42 INFO  : Memory regions updated for context APU
17:41:42 INFO  : Context for processor 'ps7_cortexa9_0' is selected.
17:41:42 INFO  : 'con' command is executed.
17:41:42 INFO  : ----------------XSDB Script (After Launch)----------------
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB II 0000150f6b7901"} -index 0
con
----------------End of Script----------------

17:41:42 INFO  : Launch script is exported to file '/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.sdk/.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)/system_debugger_on_local_periph-test_fasec.elf.tcl'
17:52:47 INFO  : Disconnected from the channel tcfchan#13.
