Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 20:33:30 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:3.2.8) from (Rev. 36) to (Rev. 37)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 20:26:05 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.7 (Rev. 35) to user.org:user:fasec_hwtest:3.2.8 (Rev. 36)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 19:06:50 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the conversion of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:3.2.7 (Rev. 35)) to Vivado generation flows.






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 19:06:49 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'

1. Summary
----------

SUCCESS in the conversion of system_design_axi_wb_i2c_master_2_0 (cern.ch:ip:axi_wb_i2c_master:3.2.0 (Rev. 8)) to Vivado generation flows.






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 19:06:49 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_1_0'

1. Summary
----------

SUCCESS in the conversion of system_design_axi_wb_i2c_master_1_0 (cern.ch:ip:axi_wb_i2c_master:3.2.0 (Rev. 8)) to Vivado generation flows.






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 19:06:49 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_1'

1. Summary
----------

SUCCESS in the conversion of system_design_axi_wb_i2c_master_0_1 (cern.ch:ip:axi_wb_i2c_master:3.2.0 (Rev. 8)) to Vivado generation flows.






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:04 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_xlconstant_6_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_xlconstant_6_0 (xilinx.com:ip:xlconstant:1.1) from (Rev. 2) to (Rev. 4)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:04 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_xlconstant_3_2'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_xlconstant_3_2 (xilinx.com:ip:xlconstant:1.1) from (Rev. 2) to (Rev. 4)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Warnings
-----------

WARNING: The upgraded user parameter set contained parameters that could not be mapped on to the upgraded IP. When checking the upgrade script, note that parameter names are case sensitive.


3. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_xlconstant_3_2'. These changes may impact your design.


-Upgraded port 'dout' width 1 differs from original width 16


4. Customization warnings
-------------------------

The normal upgrade process failed due to validation failures in the given configuration. Attempting partial upgrade to set as many user parameters as possible. Please check the parameters whose values were not applied.

Customization errors found on 'system_design_xlconstant_3_2'. Restoring to previous valid configuration.


5. Debug Commands
-----------------

  The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
  You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.

create_ip -vlnv xilinx.com:ip:xlconstant:1.1 -user_name system_design_xlconstant_3_2
set_property -dict "\
  CONFIG.CONST_VAL {1101111010101101} \
  CONFIG.CONST_WIDTH {16} \
  CONFIG.Component_Name {system_design_xlconstant_3_2} " [get_ips system_design_xlconstant_3_2]







Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:04 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_xlconcat_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_xlconcat_0_0 (xilinx.com:ip:xlconcat:2.1) from (Rev. 2) to (Rev. 1)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:04 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_xadc_wiz_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_xadc_wiz_0_0 (xilinx.com:ip:xadc_wiz:3.3) from (Rev. 2) to (Rev. 5)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:04 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the conversion of system_design_wrc_1p_kintex7_0_0 (CERN:wrc:wrc_1p_kintex7:3.2.1 (Rev. 17)) to Vivado generation flows.






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:04 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_rst_wrc_1p_kintex7_0_62M_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_rst_wrc_1p_kintex7_0_62M_0 (xilinx.com:ip:proc_sys_reset:5.0) from (Rev. 10) to (Rev. 12)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:04 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_rst_processing_system7_0_100M_2'

1. Summary
----------

SUCCESS in the upgrade of system_design_rst_processing_system7_0_100M_2 (xilinx.com:ip:proc_sys_reset:5.0) from (Rev. 10) to (Rev. 12)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:04 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_processing_system7_0_axi_periph_3'

1. Summary
----------

SUCCESS in the upgrade of system_design_processing_system7_0_axi_periph_3 (xilinx.com:ip:axi_interconnect:2.1) from (Rev. 12) to (Rev. 17)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:03 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_processing_system7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5) from (Rev. 3) to (Rev. 6)

2. Upgrade messages
-------------------

WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_EN_PTP_ENET0 with default value 1 : a parameter called PCW_EN_PTP_ENET0 already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_EN_PTP_ENET0 with default value 1 : a parameter called PCW_EN_PTP_ENET0 already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP0_NUM_WRITE_THREADS with default value 4 : a parameter called PCW_GP0_NUM_WRITE_THREADS already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP0_NUM_READ_THREADS with default value 4 : a parameter called PCW_GP0_NUM_READ_THREADS already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP1_NUM_WRITE_THREADS with default value 4 : a parameter called PCW_GP1_NUM_WRITE_THREADS already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP1_NUM_READ_THREADS with default value 4 : a parameter called PCW_GP1_NUM_READ_THREADS already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP0_EN_MODIFIABLE_TXN with default value 0 : a parameter called PCW_GP0_EN_MODIFIABLE_TXN already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP1_EN_MODIFIABLE_TXN with default value 0 : a parameter called PCW_GP1_EN_MODIFIABLE_TXN already exists in processing_system7_v5_5






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:03 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_uartlite_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_uartlite_0_0 (xilinx.com:ip:axi_uartlite:2.0) from (Rev. 15) to (Rev. 20)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:03 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_interconnect_1_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_interconnect_1_0 (xilinx.com:ip:axi_interconnect:2.1) from (Rev. 12) to (Rev. 17)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:03 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_interconnect_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_interconnect_0_0 (xilinx.com:ip:axi_interconnect:2.1) from (Rev. 12) to (Rev. 17)






Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr  4 18:39:19 MDT 2018
| Date         : Tue Jun 26 18:51:03 2018
| Host         : lapte24154 running 64-bit openSUSE Leap 42.3
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_dma_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_dma_0_0 (xilinx.com:ip:axi_dma:7.1) from (Rev. 12) to (Rev. 17)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:50:39 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the update of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:3.2.7 (Rev. 35)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:24 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_xadc_wiz_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_xadc_wiz_0_0 (xilinx.com:ip:xadc_wiz:3.3) to (Rev. 2)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:24 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the update of system_design_wrc_1p_kintex7_0_0 (CERN:wrc:wrc_1p_kintex7:3.2.1 (Rev. 17)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:24 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_rst_wrc_1p_kintex7_0_62M_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_rst_wrc_1p_kintex7_0_62M_0 (xilinx.com:ip:proc_sys_reset:5.0) from (Rev. 9) to (Rev. 10)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:24 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_rst_processing_system7_0_100M_2'

1. Summary
----------

SUCCESS in the upgrade of system_design_rst_processing_system7_0_100M_2 (xilinx.com:ip:proc_sys_reset:5.0) from (Rev. 9) to (Rev. 10)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:24 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_processing_system7_0_axi_periph_3'

1. Summary
----------

SUCCESS in the upgrade of system_design_processing_system7_0_axi_periph_3 (xilinx.com:ip:axi_interconnect:2.1) from (Rev. 10) to (Rev. 12)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:24 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_processing_system7_0_0'

1. Summary
----------

SUCCESS in the update of system_design_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5 (Rev. 3)) to current project options.

2. Upgrade messages
-------------------

WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_EN_PTP_ENET0 with default value 1 : a parameter called PCW_EN_PTP_ENET0 already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_EN_PTP_ENET0 with default value 1 : a parameter called PCW_EN_PTP_ENET0 already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP0_NUM_WRITE_THREADS with default value 4 : a parameter called PCW_GP0_NUM_WRITE_THREADS already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP0_NUM_READ_THREADS with default value 4 : a parameter called PCW_GP0_NUM_READ_THREADS already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP1_NUM_WRITE_THREADS with default value 4 : a parameter called PCW_GP1_NUM_WRITE_THREADS already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP1_NUM_READ_THREADS with default value 4 : a parameter called PCW_GP1_NUM_READ_THREADS already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP0_EN_MODIFIABLE_TXN with default value 0 : a parameter called PCW_GP0_EN_MODIFIABLE_TXN already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_GP1_EN_MODIFIABLE_TXN with default value 0 : a parameter called PCW_GP1_EN_MODIFIABLE_TXN already exists in processing_system7_v5_5






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:24 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_uartlite_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_axi_uartlite_0_0 (xilinx.com:ip:axi_uartlite:2.0) from (Rev. 13) to (Rev. 15)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Interface Information
------------------------

Detected external interface differences while upgrading 'system_design_axi_uartlite_0_0'.



3. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_axi_uartlite_0_0'. These changes may impact your design.



4. Customization warnings
-------------------------

Upgrade target IP does not have parameter ID for 'NUM_WRITE_OUTSTANDING'

Upgrade target IP does not have parameter ID for 'NUM_READ_OUTSTANDING'


5. Debug Commands
-----------------

  The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
  You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.

create_ip -vlnv xilinx.com:ip:axi_uartlite:2.0 -user_name system_design_axi_uartlite_0_0
set_property -dict "\
  CONFIG.ACLK.ASSOCIATED_BUSIF {S_AXI} \
  CONFIG.ACLK.ASSOCIATED_RESET {s_axi_aresetn} \
  CONFIG.ARESETN.POLARITY {ACTIVE_LOW} \
  CONFIG.C_BAUDRATE {115200} \
  CONFIG.C_DATA_BITS {8} \
  CONFIG.C_ODD_PARITY {0} \
  CONFIG.C_S_AXI_ACLK_FREQ_HZ {100000000} \
  CONFIG.C_S_AXI_ACLK_FREQ_HZ_d {100.0} \
  CONFIG.C_USE_PARITY {0} \
  CONFIG.Component_Name {system_design_axi_uartlite_0_0} \
  CONFIG.INTERRUPT.SENSITIVITY {EDGE_RISING} \
  CONFIG.PARITY {No_Parity} \
  CONFIG.UART.BOARD.ASSOCIATED_PARAM {UARTLITE_BOARD_INTERFACE} \
  CONFIG.UARTLITE_BOARD_INTERFACE {Custom} \
  CONFIG.USE_BOARD_FLOW {false} " [get_ips system_design_axi_uartlite_0_0]







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:23 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_interconnect_1_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_interconnect_1_0 (xilinx.com:ip:axi_interconnect:2.1) from (Rev. 10) to (Rev. 12)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:23 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_interconnect_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_interconnect_0_0 (xilinx.com:ip:axi_interconnect:2.1) from (Rev. 10) to (Rev. 12)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Wed Mar  7 14:46:23 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_dma_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_axi_dma_0_0 (xilinx.com:ip:axi_dma:7.1) from (Rev. 10) to (Rev. 12)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Interface Information
------------------------

Detected external interface differences while upgrading 'system_design_axi_dma_0_0'.



3. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_axi_dma_0_0'. These changes may impact your design.



4. Customization warnings
-------------------------

Upgrade target IP does not have parameter ID for 'NUM_WRITE_OUTSTANDING'

Upgrade target IP does not have parameter ID for 'NUM_READ_OUTSTANDING'


5. Debug Commands
-----------------

  The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
  You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.

create_ip -vlnv xilinx.com:ip:axi_dma:7.1 -user_name system_design_axi_dma_0_0
set_property -dict "\
  CONFIG.AXI_RESETN.POLARITY {ACTIVE_LOW} \
  CONFIG.Component_Name {system_design_axi_dma_0_0} \
  CONFIG.MM2S_CNTRL_RESET_OUT_N.POLARITY {ACTIVE_LOW} \
  CONFIG.MM2S_INTROUT.SENSITIVITY {LEVEL_HIGH} \
  CONFIG.MM2S_PRMRY_RESET_OUT_N.POLARITY {ACTIVE_LOW} \
  CONFIG.M_AXI_MM2S_CLK.ASSOCIATED_BUSIF {M_AXI_MM2S:M_AXIS_MM2S:M_AXIS_CNTRL} \
  CONFIG.M_AXI_MM2S_CLK.ASSOCIATED_RESET {mm2s_prmry_reset_out_n:mm2s_cntrl_reset_out_n} \
  CONFIG.M_AXI_S2MM.NUM_WRITE_OUTSTANDING {2} \
  CONFIG.M_AXI_S2MM.SUPPORTS_NARROW_BURST {0} \
  CONFIG.M_AXI_S2MM_CLK.ASSOCIATED_BUSIF {M_AXI_S2MM:S_AXIS_S2MM:S_AXIS_STS} \
  CONFIG.M_AXI_S2MM_CLK.ASSOCIATED_RESET {s2mm_prmry_reset_out_n:s2mm_sts_reset_out_n} \
  CONFIG.M_AXI_SG_CLK.ASSOCIATED_BUSIF {M_AXI_SG} \
  CONFIG.S2MM_INTROUT.SENSITIVITY {LEVEL_HIGH} \
  CONFIG.S2MM_PRMRY_RESET_OUT_N.POLARITY {ACTIVE_LOW} \
  CONFIG.S2MM_STS_RESET_OUT_N.POLARITY {ACTIVE_LOW} \
  CONFIG.S_AXI_LITE_ACLK.ASSOCIATED_BUSIF {S_AXI_LITE} \
  CONFIG.S_AXI_LITE_ACLK.ASSOCIATED_RESET {axi_resetn} \
  CONFIG.c_addr_width {32} \
  CONFIG.c_dlytmr_resolution {125} \
  CONFIG.c_enable_multi_channel {0} \
  CONFIG.c_include_mm2s {0} \
  CONFIG.c_include_mm2s_dre {0} \
  CONFIG.c_include_mm2s_sf {1} \
  CONFIG.c_include_s2mm {1} \
  CONFIG.c_include_s2mm_dre {1} \
  CONFIG.c_include_s2mm_sf {1} \
  CONFIG.c_include_sg {0} \
  CONFIG.c_m_axi_mm2s_data_width {32} \
  CONFIG.c_m_axi_s2mm_data_width {32} \
  CONFIG.c_m_axis_mm2s_tdata_width {32} \
  CONFIG.c_micro_dma {0} \
  CONFIG.c_mm2s_burst_size {16} \
  CONFIG.c_num_mm2s_channels {1} \
  CONFIG.c_num_s2mm_channels {1} \
  CONFIG.c_prmry_is_aclk_async {0} \
  CONFIG.c_s2mm_burst_size {16} \
  CONFIG.c_s_axis_s2mm_tdata_width {16} \
  CONFIG.c_sg_include_stscntrl_strm {0} \
  CONFIG.c_sg_length_width {14} \
  CONFIG.c_sg_use_stsapp_length {0} " [get_ips system_design_axi_dma_0_0]







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
| Date         : Fri Feb 16 14:57:47 2018
| Host         : lapte23307 running 64-bit CentOS Linux release 7.4.1708 (Core)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the update of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:3.2.7 (Rev. 35)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Oct 12 09:58:56 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.2
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.6 (Rev. 34) to user.org:user:fasec_hwtest:3.2.7 (Rev. 35)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Oct 11 14:50:33 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.2
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_axi_wb_i2c_master_2_0 from cern.ch:ip:axi_wb_i2c_master:3.1.2 (Rev. 6) to cern.ch:ip:axi_wb_i2c_master:3.2.0 (Rev. 8)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Interface Information
------------------------

Detected external interface differences while upgrading 'system_design_axi_wb_i2c_master_2_0'.


-Upgrade has added interface 'i2c_master' (xilinx.com:interface:iic:1.0)


3. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_axi_wb_i2c_master_2_0'. These changes may impact your design.


-Upgrade has removed port 'i2c_scl_io'

-Upgrade has removed port 'i2c_sda_io'

-Upgrade has added port 'i2c_scl_i'

-Upgrade has added port 'i2c_scl_o'

-Upgrade has added port 'i2c_scl_t'

-Upgrade has added port 'i2c_sda_i'

-Upgrade has added port 'i2c_sda_o'

-Upgrade has added port 'i2c_sda_t'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Oct 11 14:50:33 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.2
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_1'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_axi_wb_i2c_master_0_1 from cern.ch:ip:axi_wb_i2c_master:3.1.2 (Rev. 6) to cern.ch:ip:axi_wb_i2c_master:3.2.0 (Rev. 8)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Interface Information
------------------------

Detected external interface differences while upgrading 'system_design_axi_wb_i2c_master_0_1'.


-Upgrade has added interface 'i2c_master' (xilinx.com:interface:iic:1.0)


3. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_axi_wb_i2c_master_0_1'. These changes may impact your design.


-Upgrade has removed port 'i2c_scl_io'

-Upgrade has removed port 'i2c_sda_io'

-Upgrade has added port 'i2c_scl_i'

-Upgrade has added port 'i2c_scl_o'

-Upgrade has added port 'i2c_scl_t'

-Upgrade has added port 'i2c_sda_i'

-Upgrade has added port 'i2c_sda_o'

-Upgrade has added port 'i2c_sda_t'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Oct 11 12:10:04 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.2
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the update of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:3.2.6 (Rev. 34)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Oct 11 12:10:04 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.2
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_2_0 from cern.ch:ip:axi_wb_i2c_master:3.1.1 (Rev. 5) to cern.ch:ip:axi_wb_i2c_master:3.1.2 (Rev. 6)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Oct 11 12:10:04 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.2
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_1'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_1 from cern.ch:ip:axi_wb_i2c_master:3.1.1 (Rev. 5) to cern.ch:ip:axi_wb_i2c_master:3.1.2 (Rev. 6)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Jun 21 08:28:07 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.2
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.5 (Rev. 33) to user.org:user:fasec_hwtest:3.2.6 (Rev. 34)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Jun 20 19:59:10 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.2
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.4 (Rev. 32) to user.org:user:fasec_hwtest:3.2.5 (Rev. 33)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed May 24 08:22:07 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:3.2.0 (Rev. 16) to CERN:wrc:wrc_1p_kintex7:3.2.1 (Rev. 17)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri May 12 15:46:32 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.3 (Rev. 31) to user.org:user:fasec_hwtest:3.2.4 (Rev. 32)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu May 11 20:33:49 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.2 (Rev. 30) to user.org:user:fasec_hwtest:3.2.3 (Rev. 31)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu May 11 18:13:15 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.1 (Rev. 29) to user.org:user:fasec_hwtest:3.2.2 (Rev. 30)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu May 11 16:52:53 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.0 (Rev. 27) to user.org:user:fasec_hwtest:3.2.1 (Rev. 29)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Apr 13 09:57:06 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the update of system_design_wrc_1p_kintex7_0_0 (CERN:wrc:wrc_1p_kintex7:3.2.0 (Rev. 16)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Apr 13 09:57:06 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'

1. Summary
----------

SUCCESS in the update of system_design_axi_wb_i2c_master_2_0 (cern.ch:ip:axi_wb_i2c_master:3.1.1 (Rev. 5)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Apr 13 09:57:06 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_1'

1. Summary
----------

SUCCESS in the update of system_design_axi_wb_i2c_master_0_1 (cern.ch:ip:axi_wb_i2c_master:3.1.1 (Rev. 5)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Apr 13 09:49:04 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the update of system_design_wrc_1p_kintex7_0_0 (CERN:wrc:wrc_1p_kintex7:3.2.0 (Rev. 16)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Apr 12 11:12:07 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:3.1.0 (Rev. 15) to CERN:wrc:wrc_1p_kintex7:3.2.0 (Rev. 16)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_wrc_1p_kintex7_0_0'. These changes may impact your design.


-Upgrade has removed port 'clk_dmtd_b'

-Upgrade has removed port 'clk_ref_b'

-Upgrade has removed port 'clk_rx_rbclk_b'

-Upgrade has added port 'clk_dmtd_o'

-Upgrade has added port 'clk_ref_o'

-Upgrade has added port 'clk_rx_rbclk_o'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Apr 12 11:12:07 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.1.0 (Rev. 26) to user.org:user:fasec_hwtest:3.2.0 (Rev. 27)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_fasec_hwtest_0_0'. These changes may impact your design.


-Upgrade has removed port 'FMC1_GP0_b'

-Upgrade has removed port 'FMC1_GP1_b'

-Upgrade has removed port 'FMC1_GP2_b'

-Upgrade has removed port 'FMC2_GP0_b'

-Upgrade has removed port 'FMC2_GP1_b'

-Upgrade has removed port 'FMC2_GP2_b'

-Upgrade has added port 'FMC1_GP0_i'

-Upgrade has added port 'FMC1_GP1_i'

-Upgrade has added port 'FMC1_GP2_i'

-Upgrade has added port 'FMC2_GP0_i'

-Upgrade has added port 'FMC2_GP1_i'

-Upgrade has added port 'FMC2_GP2_i'

-Upgrade has added port 'intr_led_o'

-Upgrade has added port 'intr_o'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Mon Mar 27 12:41:27 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:3.0 (Rev. 14) to CERN:wrc:wrc_1p_kintex7:3.1.0 (Rev. 15)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_wrc_1p_kintex7_0_0'. These changes may impact your design.


-Upgrade has removed port 'clk_dmtd_o'

-Upgrade has removed port 'clk_ref_o'

-Upgrade has removed port 'clk_rx_rbclk_o'

-Upgrade has added port 'clk_dmtd_b'

-Upgrade has added port 'clk_ref_b'

-Upgrade has added port 'clk_rx_rbclk_b'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Mon Mar 27 12:04:12 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:2.3.1 (Rev. 13) to CERN:wrc:wrc_1p_kintex7:3.0 (Rev. 14)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_wrc_1p_kintex7_0_0'. These changes may impact your design.


-Upgrade has removed port 'clk_aux_n_i'

-Upgrade has removed port 'clk_aux_p_i'

-Upgrade has added port 'clk_dmtd_o'

-Upgrade has added port 'clk_ref_o'

-Upgrade has added port 'clk_rx_rbclk_o'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Mon Mar 27 12:04:12 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.0.1 (Rev. 25) to user.org:user:fasec_hwtest:3.1.0 (Rev. 26)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Mar 23 21:33:44 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:2.3 (Rev. 12) to CERN:wrc:wrc_1p_kintex7:2.3.1 (Rev. 13)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Mar 23 21:33:30 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.0 (Rev. 24) to user.org:user:fasec_hwtest:3.0.1 (Rev. 25)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Mar 23 21:33:30 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_2_0 from cern.ch:ip:axi_wb_i2c_master:3.1 (Rev. 4) to cern.ch:ip:axi_wb_i2c_master:3.1.1 (Rev. 5)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Mar 23 21:33:30 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_1'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_1 from cern.ch:ip:axi_wb_i2c_master:3.1 (Rev. 4) to cern.ch:ip:axi_wb_i2c_master:3.1.1 (Rev. 5)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Mar 23 19:43:50 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:2.2 (Rev. 11) to CERN:wrc:wrc_1p_kintex7:2.3 (Rev. 12)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Mar 22 11:59:22 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:2.1 (Rev. 10) to CERN:wrc:wrc_1p_kintex7:2.2 (Rev. 11)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Mar 21 09:57:14 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_2_0 from cern.ch:ip:axi_wb_i2c_master:3.0 (Rev. 2) to cern.ch:ip:axi_wb_i2c_master:3.1 (Rev. 4)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Mar 21 09:57:14 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_1'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_1 from cern.ch:ip:axi_wb_i2c_master:3.0 (Rev. 2) to cern.ch:ip:axi_wb_i2c_master:3.1 (Rev. 4)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Mar 21 09:48:44 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:2.0 (Rev. 9) to CERN:wrc:wrc_1p_kintex7:2.1 (Rev. 10)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Mar 21 09:16:22 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:1.4.1 (Rev. 8) to CERN:wrc:wrc_1p_kintex7:2.0 (Rev. 9)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Interface Information
------------------------

Detected external interface differences while upgrading 'system_design_wrc_1p_kintex7_0_0'.


-Upgrade has added interface 's00_axi' (xilinx.com:interface:aximm:1.0)

-Upgrade has added interface 's00_clk' (xilinx.com:signal:clock:1.0)

-Upgrade has added interface 's00_resetn' (xilinx.com:signal:reset:1.0)


3. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_wrc_1p_kintex7_0_0'. These changes may impact your design.


-Upgrade has removed port 'clk_25m_vcxo_i'

-Upgrade has added port 'axi_int_o'

-Upgrade has added port 'clk_20m_vcxo_i'

-Upgrade has added port 's00_axi_aclk_o'

-Upgrade has added port 's00_axi_araddr'

-Upgrade has added port 's00_axi_aresetn'

-Upgrade has added port 's00_axi_arprot'

-Upgrade has added port 's00_axi_arready'

-Upgrade has added port 's00_axi_arvalid'

-Upgrade has added port 's00_axi_awaddr'

-Upgrade has added port 's00_axi_awprot'

-Upgrade has added port 's00_axi_awready'

-Upgrade has added port 's00_axi_awvalid'

-Upgrade has added port 's00_axi_bready'

-Upgrade has added port 's00_axi_bresp'

-Upgrade has added port 's00_axi_bvalid'

-Upgrade has added port 's00_axi_rdata'

-Upgrade has added port 's00_axi_rready'

-Upgrade has added port 's00_axi_rresp'

-Upgrade has added port 's00_axi_rvalid'

-Upgrade has added port 's00_axi_wdata'

-Upgrade has added port 's00_axi_wready'

-Upgrade has added port 's00_axi_wstrb'

-Upgrade has added port 's00_axi_wvalid'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Mar 21 09:16:22 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.9 (Rev. 23) to user.org:user:fasec_hwtest:3.0 (Rev. 24)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Mar 17 16:22:53 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:1.4 (Rev. 7) to CERN:wrc:wrc_1p_kintex7:1.4.1 (Rev. 8)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Mar 15 14:40:57 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:1.3.1 (Rev. 6) to CERN:wrc:wrc_1p_kintex7:1.4 (Rev. 7)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_wrc_1p_kintex7_0_0'. These changes may impact your design.


-Upgrade has removed port 'clk_100mhz_i'

-Upgrade has removed port 'pll_cs_n_o'

-Upgrade has removed port 'pll_ld_i'

-Upgrade has removed port 'pll_refsel_o'

-Upgrade has removed port 'pll_reset_n_o'

-Upgrade has removed port 'pll_sck_o'

-Upgrade has removed port 'pll_sdi_o'

-Upgrade has removed port 'pll_sdo_i'

-Upgrade has removed port 'pll_status_i'

-Upgrade has removed port 'pll_sync_n_o'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Mar 15 11:00:55 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:1.3 (Rev. 5) to CERN:wrc:wrc_1p_kintex7:1.3.1 (Rev. 6)

2. Interface Information
------------------------

Detected external interface differences while upgrading 'system_design_wrc_1p_kintex7_0_0'.


-Upgrade has removed interface 'clk_aux_i'

-Upgrade has removed interface 'gtp_dedicated_clk_i'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Mar 14 17:45:10 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:1.2 (Rev. 4) to CERN:wrc:wrc_1p_kintex7:1.3 (Rev. 5)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Mar 14 17:25:59 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:1.1 (Rev. 3) to CERN:wrc:wrc_1p_kintex7:1.2 (Rev. 4)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Mar 14 16:36:03 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:1.0 (Rev. 2) to CERN:wrc:wrc_1p_kintex7:1.1 (Rev. 3)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Interface Information
------------------------

Detected external interface differences while upgrading 'system_design_wrc_1p_kintex7_0_0'.


-Upgrade has added interface 'clk_aux_i' (xilinx.com:interface:diff_clock:1.0)

-Upgrade has added interface 'gtp_dedicated_clk_i' (xilinx.com:interface:diff_clock:1.0)

-Upgrade has added interface 'gtp_wr' (xilinx.com:interface:sfp:1.0)

-Upgrade has added interface 'uart_wr' (xilinx.com:interface:uart:1.0)


3. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_wrc_1p_kintex7_0_0'. These changes may impact your design.


-Upgrade has removed port 'clk_100mhz_n_i'

-Upgrade has removed port 'clk_100mhz_p_i'

-Upgrade has added port 'clk_100mhz_i'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Feb 17 10:12:02 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.8.1 (Rev. 22) to user.org:user:fasec_hwtest:2.9 (Rev. 23)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Feb 17 10:12:02 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_2_0 from user.org:user:axi_wb_i2c_master:2.5.1 (Rev. 1) to user.org:user:axi_wb_i2c_master:2.5.2 (Rev. 1)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Feb 17 10:12:02 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_1_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_1_0 from user.org:user:axi_wb_i2c_master:2.5.1 (Rev. 1) to user.org:user:axi_wb_i2c_master:2.5.2 (Rev. 1)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Feb 17 10:12:02 2017
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_0 from user.org:user:axi_wb_i2c_master:2.5.1 (Rev. 1) to user.org:user:axi_wb_i2c_master:2.5.2 (Rev. 1)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Dec 15 08:50:05 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.8 (Rev. 21) to user.org:user:fasec_hwtest:2.8.1 (Rev. 22)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Dec 14 13:20:54 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.7.2 (Rev. 20) to user.org:user:fasec_hwtest:2.8 (Rev. 21)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Dec 13 12:35:51 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.7.1 (Rev. 19) to user.org:user:fasec_hwtest:2.7.2 (Rev. 20)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Nov 30 09:45:58 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.7.0 (Rev. 18) to user.org:user:fasec_hwtest:2.7.1 (Rev. 19)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Nov 29 15:59:35 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.6.2 (Rev. 17) to user.org:user:fasec_hwtest:2.7.0 (Rev. 18)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Nov 24 11:01:57 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.6.1 (Rev. 16) to user.org:user:fasec_hwtest:2.6.2 (Rev. 17)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Nov 24 10:13:18 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.6 (Rev. 15) to user.org:user:fasec_hwtest:2.6.1 (Rev. 16)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Nov 24 10:08:43 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.5.2 (Rev. 14) to user.org:user:fasec_hwtest:2.6 (Rev. 15)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_fasec_hwtest_0_0'. These changes may impact your design.


-Upgrade has added port 'dig_in1_i'

-Upgrade has added port 'dig_in2_i'

-Upgrade has added port 'dig_in3_n_i'

-Upgrade has added port 'dig_in4_n_i'

-Upgrade has added port 'dig_out5_n'

-Upgrade has added port 'dig_out6_n'

-Upgrade has added port 'dig_outs_i'

-Upgrade has added port 'gem_status_vector_i'

-Upgrade has added port 'watchdog_pl_o'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Nov 24 10:08:43 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_2_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_2_0 from user.org:user:axi_wb_i2c_master:2.5 (Rev. 1) to user.org:user:axi_wb_i2c_master:2.5.1 (Rev. 1)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Nov 24 10:08:43 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_1_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_1_0 from user.org:user:axi_wb_i2c_master:2.5 (Rev. 1) to user.org:user:axi_wb_i2c_master:2.5.1 (Rev. 1)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Nov 24 10:08:43 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_0 from user.org:user:axi_wb_i2c_master:2.5 (Rev. 1) to user.org:user:axi_wb_i2c_master:2.5.1 (Rev. 1)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Oct 19 10:09:22 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.5.1 (Rev. 13) to user.org:user:fasec_hwtest:2.5.2 (Rev. 14)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Oct 19 09:03:50 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.5 (Rev. 12) to user.org:user:fasec_hwtest:2.5.1 (Rev. 13)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Oct 19 08:22:08 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.4 (Rev. 11) to user.org:user:fasec_hwtest:2.5 (Rev. 12)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Oct 18 18:46:25 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.3 (Rev. 10) to user.org:user:fasec_hwtest:2.4 (Rev. 11)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_fasec_hwtest_0_0'. These changes may impact your design.


-Upgrade has added port 'FMC1_GP0_b'

-Upgrade has added port 'FMC1_GP1_b'

-Upgrade has added port 'FMC1_GP2_b'

-Upgrade has added port 'FMC1_GP3_b'

-Upgrade has added port 'FMC2_GP0_b'

-Upgrade has added port 'FMC2_GP1_b'

-Upgrade has added port 'FMC2_GP2_b'

-Upgrade has added port 'FMC2_GP3_b'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 17:21:00 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.2.3 (Rev. 9) to user.org:user:fasec_hwtest:2.3 (Rev. 10)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 17:16:01 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:2.2.3) from (Rev. 8) to (Rev. 9)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 16:53:03 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.2.2 (Rev. 7) to user.org:user:fasec_hwtest:2.2.3 (Rev. 8)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 16:50:54 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.2.1 (Rev. 6) to user.org:user:fasec_hwtest:2.2.2 (Rev. 7)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 16:44:31 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_1_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_1_0 from user.org:user:axi_wb_i2c_master:2.4.2 (Rev. 9) to user.org:user:axi_wb_i2c_master:2.5 (Rev. 1)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 16:44:31 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_0 from user.org:user:axi_wb_i2c_master:2.4.2 (Rev. 9) to user.org:user:axi_wb_i2c_master:2.5 (Rev. 1)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 16:31:21 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_1_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_axi_wb_i2c_master_1_0 from user.org:user:axi_wb_i2c_master:2.3 (Rev. 6) to user.org:user:axi_wb_i2c_master:2.4.2 (Rev. 9)

After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality.

2. Warnings
-----------

WARNING: The upgraded user parameter set contained parameters that could not be mapped on to the upgraded IP. Note that parameter names and IDs are case sensitive.


3. Customization warnings
-------------------------

The normal upgrade process failed due to validation failures in the given configuration . Attempting partial upgrade.
This process will attempt to set as many user parameters as possible.Please check the parameters whose values were not applied

The normal upgrade process failed due to validation failures in the given configuration . Attempting partial upgrade.
This process will attempt to set as many user parameters as possible.Please check the parameters whose values were not applied

The normal upgrade process failed due to validation failures in the given configuration . Attempting partial upgrade.
This process will attempt to set as many user parameters as possible.Please check the parameters whose values were not applied


4. Debug Commands
-----------------

  The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
  You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.

create_ip -vlnv user.org:user:axi_wb_i2c_master:2.4.2 -user_name system_design_axi_wb_i2c_master_1_0
set_property -dict "\
  CONFIG.C_S00_AXI_ADDR_WIDTH 32 \
  CONFIG.C_S00_AXI_BASEADDR 0xFFFFFFFF \
  CONFIG.C_S00_AXI_DATA_WIDTH 32 \
  CONFIG.C_S00_AXI_HIGHADDR 0x00000000 \
  CONFIG.Component_Name system_design_axi_wb_i2c_master_1_0 " [get_ips system_design_axi_wb_i2c_master_1_0]







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 16:31:21 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_axi_wb_i2c_master_0_0 from user.org:user:axi_wb_i2c_master:2.3 (Rev. 6) to user.org:user:axi_wb_i2c_master:2.4.2 (Rev. 9)

After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality.

2. Warnings
-----------

WARNING: The upgraded user parameter set contained parameters that could not be mapped on to the upgraded IP. Note that parameter names and IDs are case sensitive.


3. Customization warnings
-------------------------

The normal upgrade process failed due to validation failures in the given configuration . Attempting partial upgrade.
This process will attempt to set as many user parameters as possible.Please check the parameters whose values were not applied

The normal upgrade process failed due to validation failures in the given configuration . Attempting partial upgrade.
This process will attempt to set as many user parameters as possible.Please check the parameters whose values were not applied

The normal upgrade process failed due to validation failures in the given configuration . Attempting partial upgrade.
This process will attempt to set as many user parameters as possible.Please check the parameters whose values were not applied


4. Debug Commands
-----------------

  The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
  You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.

create_ip -vlnv user.org:user:axi_wb_i2c_master:2.4.2 -user_name system_design_axi_wb_i2c_master_0_0
set_property -dict "\
  CONFIG.C_S00_AXI_ADDR_WIDTH 32 \
  CONFIG.C_S00_AXI_BASEADDR 0xFFFFFFFF \
  CONFIG.C_S00_AXI_DATA_WIDTH 32 \
  CONFIG.C_S00_AXI_HIGHADDR 0x00000000 \
  CONFIG.Component_Name system_design_axi_wb_i2c_master_0_0 " [get_ips system_design_axi_wb_i2c_master_0_0]







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Wed Aug 31 09:59:17 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.1 (Rev. 4) to user.org:user:fasec_hwtest:2.2.1 (Rev. 6)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Tue Aug 30 11:30:50 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:2.0 (Rev. 3) to user.org:user:fasec_hwtest:2.1 (Rev. 4)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_fasec_hwtest_0_0'. These changes may impact your design.


-Upgrade has removed port 'FMC1_CLK0C2M_N'

-Upgrade has removed port 'FMC1_CLK0C2M_P'

-Upgrade has removed port 'FMC1_CLK0M2C_N'

-Upgrade has removed port 'FMC1_CLK0M2C_P'

-Upgrade has removed port 'FMC1_PRSNTM2C_n'

-Upgrade has removed port 'FMC2_CLK0C2M_N'

-Upgrade has removed port 'FMC2_CLK0C2M_P'

-Upgrade has removed port 'FMC2_CLK0M2C_N'

-Upgrade has removed port 'FMC2_CLK0M2C_P'

-Upgrade has removed port 'FMC2_PRSNTM2C_n'

-Upgrade has added port 'FMC1_CLK0C2M_N_o'

-Upgrade has added port 'FMC1_CLK0C2M_P_o'

-Upgrade has added port 'FMC1_CLK0M2C_N_i'

-Upgrade has added port 'FMC1_CLK0M2C_P_i'

-Upgrade has added port 'FMC1_PRSNTM2C_n_i'

-Upgrade has added port 'FMC2_CLK0C2M_N_o'

-Upgrade has added port 'FMC2_CLK0C2M_P_o'

-Upgrade has added port 'FMC2_CLK0M2C_N_i'

-Upgrade has added port 'FMC2_CLK0M2C_P_i'

-Upgrade has added port 'FMC2_PRSNTM2C_n_i'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Mon Aug 29 11:14:55 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:1.0 (Rev. 2) to user.org:user:fasec_hwtest:2.0 (Rev. 3)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Interface Information
------------------------

Detected external interface differences while upgrading 'system_design_fasec_hwtest_0_0'.


-Upgrade has added interface 'S00_AXI' (xilinx.com:interface:aximm:1.0)

-Upgrade has added interface 's00_axi_aclk' (xilinx.com:signal:clock:1.0)

-Upgrade has added interface 's00_axi_aresetn' (xilinx.com:signal:reset:1.0)


3. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_fasec_hwtest_0_0'. These changes may impact your design.


-Upgrade has removed port 'clk_i'

-Upgrade has added port 'FMC1_CLK0C2M_N'

-Upgrade has added port 'FMC1_CLK0C2M_P'

-Upgrade has added port 'FMC1_CLK0M2C_N'

-Upgrade has added port 'FMC1_CLK0M2C_P'

-Upgrade has added port 'FMC1_LA_N_b'

-Upgrade has added port 'FMC1_LA_P_b'

-Upgrade has added port 'FMC1_PRSNTM2C_n'

-Upgrade has added port 'FMC2_CLK0C2M_N'

-Upgrade has added port 'FMC2_CLK0C2M_P'

-Upgrade has added port 'FMC2_CLK0M2C_N'

-Upgrade has added port 'FMC2_CLK0M2C_P'

-Upgrade has added port 'FMC2_LA_N_b'

-Upgrade has added port 'FMC2_LA_P_b'

-Upgrade has added port 'FMC2_PRSNTM2C_n'

-Upgrade has added port 'osc100_clk_i'

-Upgrade has added port 'ps_clk_i'

-Upgrade has added port 's00_axi_aclk'

-Upgrade has added port 's00_axi_araddr'

-Upgrade has added port 's00_axi_aresetn'

-Upgrade has added port 's00_axi_arprot'

-Upgrade has added port 's00_axi_arready'

-Upgrade has added port 's00_axi_arvalid'

-Upgrade has added port 's00_axi_awaddr'

-Upgrade has added port 's00_axi_awprot'

-Upgrade has added port 's00_axi_awready'

-Upgrade has added port 's00_axi_awvalid'

-Upgrade has added port 's00_axi_bready'

-Upgrade has added port 's00_axi_bresp'

-Upgrade has added port 's00_axi_bvalid'

-Upgrade has added port 's00_axi_rdata'

-Upgrade has added port 's00_axi_rready'

-Upgrade has added port 's00_axi_rresp'

-Upgrade has added port 's00_axi_rvalid'

-Upgrade has added port 's00_axi_wdata'

-Upgrade has added port 's00_axi_wready'

-Upgrade has added port 's00_axi_wstrb'

-Upgrade has added port 's00_axi_wvalid'







Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Aug 26 17:54:55 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_fasec_hwtest_0_0'

1. Summary
----------

SUCCESS in the update of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:1.0 (Rev. 2)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Aug 26 17:54:55 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_1_0'

1. Summary
----------

SUCCESS in the update of system_design_axi_wb_i2c_master_1_0 (user.org:user:axi_wb_i2c_master:2.3 (Rev. 6)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Aug 26 17:54:55 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

SUCCESS in the update of system_design_axi_wb_i2c_master_0_0 (user.org:user:axi_wb_i2c_master:2.3 (Rev. 6)) to current project options.






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Aug 26 17:47:30 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_1_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_1_0 from user.org:user:axi_wb_i2c_master:2.2 (Rev. 5) to user.org:user:axi_wb_i2c_master:2.3 (Rev. 6)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Fri Aug 26 17:47:30 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_0 from user.org:user:axi_wb_i2c_master:2.2 (Rev. 5) to user.org:user:axi_wb_i2c_master:2.3 (Rev. 6)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Aug 25 17:51:42 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_0 from user.org:user:axi_wb_i2c_master:2.1 (Rev. 4) to user.org:user:axi_wb_i2c_master:2.2 (Rev. 5)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Aug 25 16:21:38 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

SUCCESS in the upgrade of system_design_axi_wb_i2c_master_0_0 from user.org:user:axi_wb_i2c_master:2.0 (Rev. 3) to user.org:user:axi_wb_i2c_master:2.1 (Rev. 4)






Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
| Date         : Thu Aug 25 08:52:29 2016
| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command      : upgrade_ip
| Device       : xc7z030ffg676-2
------------------------------------------------------------------------------------

Upgrade Log for IP 'system_design_axi_wb_i2c_master_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of system_design_axi_wb_i2c_master_0_0 from user.org:user:axi_wb_i2c_master:1.0 (Rev. 2) to user.org:user:axi_wb_i2c_master:2.0 (Rev. 3)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Connection Warnings
----------------------

Detected external port differences while upgrading 'system_design_axi_wb_i2c_master_0_0'. These changes may impact your design.


-Upgrade has removed port 'i2c_scl_i'

-Upgrade has removed port 'i2c_scl_o'

-Upgrade has removed port 'i2c_sda_i'

-Upgrade has removed port 'i2c_sda_o'

-Upgrade has added port 'i2c_scl_io'

-Upgrade has added port 'i2c_sda_io'


