fmc_adc_100ms_csr

FMC ADC 100MS/s core registers

Wishbone slave for FMC ADC 100MS/s core

1. Memory map summary

2. Register description

2.1. ctl

Control register

• fsm_cmd [rw]: State machine commands (ignore on read)
  1: ACQ_START (start acquisition, only when FSM is idle)
  2: ACQ_STOP (stop acquisition, anytime)
• fmc_clk_oe [rw]: FMC Si750 output enable
• offset_dac_clr_n [rw]: Offset DACs clear (active low)
• man_bitslip [rw]: Manual serdes bitslip (ignore on read)
• test_data_en [rw]: Enable test data
  Write the DDR RAM address counter value instead of ADC data to DDR.
  Note that no timetags are appended at the end of test data.
• trig_led [rw]: Manual TRIG LED
  Manual control of the front panel TRIG LED
• acq_led [rw]: Manual ACQ LED
  Manual control of the front panel ACQ LED
• clear_trig_stat [rw]: Clear trigger status
  Write 1 to clear the last trigger status register. Auto-resets to zero.

2.2. sta

Status register

• fsm [ro]: State machine status
  States:
  0: illegal
  1: IDLE
  2: PRE_TRIG
  3: WAIT_TRIG
  4: POST_TRIG
  5: TRIG_TAG
  6: DECR_SHOT
  7: illegal
• serdes_pll [ro]: SerDes PLL status
  Sampling clock recovery PLL.
  0: not locked
  1: locked
• serdes_synced [ro]: SerDes synchronization status
  0: bitslip in progress
  1: serdes synchronized
• acq_cfg [ro]: Acquisition configuration status
  0: Unauthorised acquisition configuration (will prevent acquisition to start)
  1: Valid acquisition configuration
  - Shot number > 0
  - Post-trigger sample > 0

2.3. trig_stat

Trigger status

• ext [ro]: External trigger input
  0: not triggered
  1: triggered
• sw [ro]: Software trigger
  0: not triggered
  1: triggered
• time [ro]: Timetag trigger
  0: not triggered
  1: triggered
• ch1 [ro]: Channel 1 internal threshold trigger
  0: not triggered
  1: triggered
• ch2 [ro]: Channel 2 internal threshold trigger
  0: not triggered
  1: triggered
• ch3 [ro]: Channel 3 internal threshold trigger
  0: not triggered
  1: triggered
• ch4 [ro]: Channel 4 internal threshold trigger
  0: not triggered
  1: triggered

2.4. trig_en

Trigger enable

• ext [rw]: External trigger input
  0: disable
  1: enable
• sw [rw]: Software trigger
  0: disable
  1: enable
• time [rw]: Timetag trigger
  0: disable
  1: enable
• alt_time [rw]: Alternate timetag trigger
  0: disable
  1: enable
• ch1 [rw]: Channel 1 internal threshold trigger
  0: disable
  1: enable
• ch2 [rw]: Channel 2 internal threshold trigger
  0: disable
  1: enable
• ch3 [rw]: Channel 3 internal threshold trigger
  0: disable
  1: enable
• ch4 [rw]: Channel 4 internal threshold trigger
  0: disable
  1: enable
• fwd_ext [rw]: Forward external trigger to trigger out
  0: disable
  1: enable
• fwd_ch1 [rw]: Forward channel 1 internal threshold trigger to trigger out
  0: disable
  1: enable
• fwd_ch2 [rw]: Forward channel 2 internal threshold trigger to trigger out
  0: disable
  1: enable
• fwd_ch3 [rw]: Forward channel 3 internal threshold trigger to trigger out
  0: disable
  1: enable
• fwd_ch4 [rw]: Forward channel 4 internal threshold trigger to trigger out
  0: disable
  1: enable

2.5. trig_pol

Trigger polarity

• ext [rw]: External trigger input
  0: positive edge/slope
  1: negative edge/slope
• ch1 [rw]: Channel 1 internal threshold trigger
  0: positive edge/slope
  1: negative edge/slope
• ch2 [rw]: Channel 2 internal threshold trigger
  0: positive edge/slope
  1: negative edge/slope
• ch3 [rw]: Channel 3 internal threshold trigger
  0: positive edge/slope
  1: negative edge/slope
• ch4 [rw]: Channel 4 internal threshold trigger
  0: positive edge/slope
  1: negative edge/slope

2.6. ext_trig_dly

External trigger delay

• ext_trig_dly [rw]: External trigger delay

2.7. sw_trig

Software trigger

• sw_trig [wo]: Software trigger

2.8. shots

Number of shots

• nbr [rw]: Number of shots
  Number of shots required in multi-shot mode, set to one for single-shot mode.
• remain [rw]: Remaining shots counter
  Counts the number of remaining shots to acquire.

2.9. multi_depth

Multi-shot sample depth register

• multi_depth [ro]: Multi-shot sample depth register

2.10. trig_pos

Trigger address register

• trig_pos [ro]: Trigger address register

2.11. fs_freq

Sampling clock frequency

• fs_freq [ro]: Sampling clock frequency

2.12. undersample

Undersampling ratio

• undersample [rw]: Undersampling ratio

2.13. pre_samples

Pre-trigger samples

• pre_samples [rw]: Pre-trigger samples

2.14. post_samples

Post-trigger samples

• post_samples [rw]: Post-trigger samples

2.15. samples_cnt

Samples counter

• samples_cnt [ro]: Samples counter

2.16. ch1_ctl

Channel 1 control register

• ssr [rw]: Solid state relays control for channel 1
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

2.17. ch1_sta

Channel 1 status register

• val [ro]: Channel 1 current ADC value
  Current ADC raw value. The format is binary two\'s complement.

2.18. ch1_calib

Channel 1 calibration register

• gain [rw]: Gain calibration for channel 1
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
• offset [rw]: Offset calibration for channel 1
  Offset applied to all data coming from the ADC. The format is binary two\'s complement.

2.19. ch1_sat

Channel 1 saturation register

• val [rw]: Saturation value for channel 1
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

2.20. ch1_trig_thres

Channel 1 trigger threshold configuration register

• val [rw]: Threshold for internal trigger
  Treated as binary two\'s complement and compared to raw ADC data.
• hyst [rw]: Internal trigger threshold hysteresis
  Configures the internal trigger threshold hysteresis.
  The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.

2.21. ch1_trig_dly

Channel 1 trigger delay

• ch1_trig_dly [rw]: Channel 1 trigger delay

2.22. ch2_ctl

Channel 2 control register

• ssr [rw]: Solid state relays control for channel 2
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

2.23. ch2_sta

Channel 2 status register

• val [ro]: Channel 2 current ACD value
  Current ADC raw value. The format is binary two\'s complement.

2.24. ch2_calib

Channel 2 calibration register

• gain [rw]: Gain calibration for channel 2
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
• offset [rw]: Offset calibration for channel 2
  Offset applied to all data coming from the ADC. The format is binary two\'s complement.

2.25. ch2_sat

Channel 2 saturation register

• val [rw]: Saturation value for channel 2
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

2.26. ch2_trig_thres

Channel 2 trigger threshold configuration register

• val [rw]: Threshold for internal trigger
  Treated as binary two\'s complement and compared to raw ADC data.
• hyst [rw]: Internal trigger threshold hysteresis
  Configures the internal trigger threshold hysteresis.
  The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.

2.27. ch2_trig_dly

Channel 2 trigger delay

• ch2_trig_dly [rw]: Channel 2 trigger delay

2.28. ch3_ctl

Channel 3 control register

• ssr [rw]: Solid state relays control for channel 3
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

2.29. ch3_sta

Channel 3 status register

• val [ro]: Channel 3 current ADC value
  Current ADC raw value. The format is binary two\'s complement.

2.30. ch3_calib

Channel 3 calibration register

• gain [rw]: Gain calibration for channel 3
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
• offset [rw]: Offset calibration for channel 3
  Offset applied to all data coming from the ADC. The format is binary two\'s complement.

2.31. ch3_sat

Channel 3 saturation register

• val [rw]: Saturation value for channel 3
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

2.32. ch3_trig_thres

Channel 3 trigger threshold configuration register

• val [rw]: Threshold for internal trigger
  Treated as binary two\'s complement and compared to raw ADC data.
• hyst [rw]: Internal trigger threshold hysteresis
  Configures the internal trigger threshold hysteresis.
  The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.

2.33. ch3_trig_dly

Channel 3 trigger delay

• ch3_trig_dly [rw]: Channel 3 trigger delay

2.34. ch4_ctl

Channel 4 control register

• ssr [rw]: Solid state relays control for channel 4
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

2.35. ch4_sta

Channel 4 status register

• val [ro]: Channel 4 current ADC value
  Current ADC raw value. The format is binary two\'s complement.

2.36. ch4_calib

Channel 4 gain calibration register

• gain [rw]: Gain calibration for channel 4
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
• offset [rw]: Offset calibration for channel 4
  Offset applied to all data coming from the ADC. The format is binary two\'s complement.

2.37. ch4_sat

Channel 4 saturation register

• val [rw]: Saturation value for channel 4
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

2.38. ch4_trig_thres

Channel 4 trigger threshold configuration register

• val [rw]: Threshold for internal trigger
  Treated as binary two\'s complement and compared to raw ADC data.
• hyst [rw]: Internal trigger threshold hysteresis
  Configures the internal trigger threshold hysteresis.
  The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.

2.39. ch4_trig_dly

Channel 4 trigger delay

• ch4_trig_dly [rw]: Channel 4 trigger delay