-- Do not edit; this file was generated by Cheby using these options:
--  -i fmc_adc_100Ms_csr.cheby --gen-hdl=fmc_adc_100Ms_csr.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

package fmc_adc_100ms_csr_pkg is
  type t_fmc_adc_100ms_csr_master_out is record
    ctl_fsm_cmd      : std_logic_vector(1 downto 0);
    ctl_fmc_clk_oe   : std_logic;
    ctl_offset_dac_clr_n : std_logic;
    ctl_man_bitslip  : std_logic;
    ctl_test_data_en : std_logic;
    ctl_trig_led     : std_logic;
    ctl_acq_led      : std_logic;
    ctl_clear_trig_stat : std_logic;
    ctl_wr           : std_logic;
    trig_en_ext      : std_logic;
    trig_en_sw       : std_logic;
    trig_en_time     : std_logic;
    trig_en_aux_time : std_logic;
    trig_en_ch1      : std_logic;
    trig_en_ch2      : std_logic;
    trig_en_ch3      : std_logic;
    trig_en_ch4      : std_logic;
    trig_pol_ext     : std_logic;
    trig_pol_ch1     : std_logic;
    trig_pol_ch2     : std_logic;
    trig_pol_ch3     : std_logic;
    trig_pol_ch4     : std_logic;
    ext_trig_dly     : std_logic_vector(31 downto 0);
    sw_trig          : std_logic_vector(31 downto 0);
    sw_trig_wr       : std_logic;
    shots_nbr        : std_logic_vector(15 downto 0);
    shots_remain     : std_logic_vector(15 downto 0);
    downsample       : std_logic_vector(31 downto 0);
    pre_samples      : std_logic_vector(31 downto 0);
    post_samples     : std_logic_vector(31 downto 0);
    ch1_ctl_ssr      : std_logic_vector(6 downto 0);
    ch1_calib_gain   : std_logic_vector(15 downto 0);
    ch1_calib_offset : std_logic_vector(15 downto 0);
    ch1_sat_val      : std_logic_vector(14 downto 0);
    ch1_trig_thres_val : std_logic_vector(15 downto 0);
    ch1_trig_thres_hyst : std_logic_vector(15 downto 0);
    ch1_trig_dly     : std_logic_vector(31 downto 0);
    ch2_ctl_ssr      : std_logic_vector(6 downto 0);
    ch2_calib_gain   : std_logic_vector(15 downto 0);
    ch2_calib_offset : std_logic_vector(15 downto 0);
    ch2_sat_val      : std_logic_vector(14 downto 0);
    ch2_trig_thres_val : std_logic_vector(15 downto 0);
    ch2_trig_thres_hyst : std_logic_vector(15 downto 0);
    ch2_trig_dly     : std_logic_vector(31 downto 0);
    ch3_ctl_ssr      : std_logic_vector(6 downto 0);
    ch3_calib_gain   : std_logic_vector(15 downto 0);
    ch3_calib_offset : std_logic_vector(15 downto 0);
    ch3_sat_val      : std_logic_vector(14 downto 0);
    ch3_trig_thres_val : std_logic_vector(15 downto 0);
    ch3_trig_thres_hyst : std_logic_vector(15 downto 0);
    ch3_trig_dly     : std_logic_vector(31 downto 0);
    ch4_ctl_ssr      : std_logic_vector(6 downto 0);
    ch4_calib_gain   : std_logic_vector(15 downto 0);
    ch4_calib_offset : std_logic_vector(15 downto 0);
    ch4_sat_val      : std_logic_vector(14 downto 0);
    ch4_trig_thres_val : std_logic_vector(15 downto 0);
    ch4_trig_thres_hyst : std_logic_vector(15 downto 0);
    ch4_trig_dly     : std_logic_vector(31 downto 0);
  end record t_fmc_adc_100ms_csr_master_out;
  subtype t_fmc_adc_100ms_csr_slave_in is t_fmc_adc_100ms_csr_master_out;

  type t_fmc_adc_100ms_csr_slave_out is record
    ctl_fsm_cmd      : std_logic_vector(1 downto 0);
    ctl_man_bitslip  : std_logic;
    ctl_clear_trig_stat : std_logic;
    sta_fsm          : std_logic_vector(2 downto 0);
    sta_serdes_pll   : std_logic;
    sta_serdes_synced : std_logic;
    sta_acq_cfg      : std_logic;
    trig_stat_ext    : std_logic;
    trig_stat_sw     : std_logic;
    trig_stat_time   : std_logic;
    trig_stat_ch1    : std_logic;
    trig_stat_ch2    : std_logic;
    trig_stat_ch3    : std_logic;
    trig_stat_ch4    : std_logic;
    trig_en_sw       : std_logic;
    trig_en_aux_time : std_logic;
    shots_remain     : std_logic_vector(15 downto 0);
    multi_depth      : std_logic_vector(31 downto 0);
    trig_pos         : std_logic_vector(31 downto 0);
    fs_freq          : std_logic_vector(31 downto 0);
    samples_cnt      : std_logic_vector(31 downto 0);
    ch1_sta_val      : std_logic_vector(15 downto 0);
    ch2_sta_val      : std_logic_vector(15 downto 0);
    ch3_sta_val      : std_logic_vector(15 downto 0);
    ch4_sta_val      : std_logic_vector(15 downto 0);
  end record t_fmc_adc_100ms_csr_slave_out;
  subtype t_fmc_adc_100ms_csr_master_in is t_fmc_adc_100ms_csr_slave_out;
end fmc_adc_100ms_csr_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.fmc_adc_100ms_csr_pkg.all;

entity fmc_adc_100ms_csr is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- Wires and registers
    fmc_adc_100ms_csr_i  : in    t_fmc_adc_100ms_csr_master_in;
    fmc_adc_100ms_csr_o  : out   t_fmc_adc_100ms_csr_master_out
  );
end fmc_adc_100ms_csr;

architecture syn of fmc_adc_100ms_csr is
  signal rd_int                         : std_logic;
  signal wr_int                         : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal ctl_fmc_clk_oe_reg             : std_logic;
  signal ctl_offset_dac_clr_n_reg       : std_logic;
  signal ctl_test_data_en_reg           : std_logic;
  signal ctl_trig_led_reg               : std_logic;
  signal ctl_acq_led_reg                : std_logic;
  signal trig_en_ext_reg                : std_logic;
  signal trig_en_time_reg               : std_logic;
  signal trig_en_ch1_reg                : std_logic;
  signal trig_en_ch2_reg                : std_logic;
  signal trig_en_ch3_reg                : std_logic;
  signal trig_en_ch4_reg                : std_logic;
  signal trig_pol_ext_reg               : std_logic;
  signal trig_pol_ch1_reg               : std_logic;
  signal trig_pol_ch2_reg               : std_logic;
  signal trig_pol_ch3_reg               : std_logic;
  signal trig_pol_ch4_reg               : std_logic;
  signal ext_trig_dly_reg               : std_logic_vector(31 downto 0);
  signal shots_nbr_reg                  : std_logic_vector(15 downto 0);
  signal downsample_reg                 : std_logic_vector(31 downto 0);
  signal pre_samples_reg                : std_logic_vector(31 downto 0);
  signal post_samples_reg               : std_logic_vector(31 downto 0);
  signal ch1_ctl_ssr_reg                : std_logic_vector(6 downto 0);
  signal ch1_calib_gain_reg             : std_logic_vector(15 downto 0);
  signal ch1_calib_offset_reg           : std_logic_vector(15 downto 0);
  signal ch1_sat_val_reg                : std_logic_vector(14 downto 0);
  signal ch1_trig_thres_val_reg         : std_logic_vector(15 downto 0);
  signal ch1_trig_thres_hyst_reg        : std_logic_vector(15 downto 0);
  signal ch1_trig_dly_reg               : std_logic_vector(31 downto 0);
  signal ch2_ctl_ssr_reg                : std_logic_vector(6 downto 0);
  signal ch2_calib_gain_reg             : std_logic_vector(15 downto 0);
  signal ch2_calib_offset_reg           : std_logic_vector(15 downto 0);
  signal ch2_sat_val_reg                : std_logic_vector(14 downto 0);
  signal ch2_trig_thres_val_reg         : std_logic_vector(15 downto 0);
  signal ch2_trig_thres_hyst_reg        : std_logic_vector(15 downto 0);
  signal ch2_trig_dly_reg               : std_logic_vector(31 downto 0);
  signal ch3_ctl_ssr_reg                : std_logic_vector(6 downto 0);
  signal ch3_calib_gain_reg             : std_logic_vector(15 downto 0);
  signal ch3_calib_offset_reg           : std_logic_vector(15 downto 0);
  signal ch3_sat_val_reg                : std_logic_vector(14 downto 0);
  signal ch3_trig_thres_val_reg         : std_logic_vector(15 downto 0);
  signal ch3_trig_thres_hyst_reg        : std_logic_vector(15 downto 0);
  signal ch3_trig_dly_reg               : std_logic_vector(31 downto 0);
  signal ch4_ctl_ssr_reg                : std_logic_vector(6 downto 0);
  signal ch4_calib_gain_reg             : std_logic_vector(15 downto 0);
  signal ch4_calib_offset_reg           : std_logic_vector(15 downto 0);
  signal ch4_sat_val_reg                : std_logic_vector(14 downto 0);
  signal ch4_trig_thres_val_reg         : std_logic_vector(15 downto 0);
  signal ch4_trig_thres_hyst_reg        : std_logic_vector(15 downto 0);
  signal ch4_trig_dly_reg               : std_logic_vector(31 downto 0);
  signal reg_rdat_int                   : std_logic_vector(31 downto 0);
  signal rd_ack1_int                    : std_logic;
begin

  -- WB decode signals
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- Assign outputs
  fmc_adc_100ms_csr_o.ctl_fmc_clk_oe <= ctl_fmc_clk_oe_reg;
  fmc_adc_100ms_csr_o.ctl_offset_dac_clr_n <= ctl_offset_dac_clr_n_reg;
  fmc_adc_100ms_csr_o.ctl_test_data_en <= ctl_test_data_en_reg;
  fmc_adc_100ms_csr_o.ctl_trig_led <= ctl_trig_led_reg;
  fmc_adc_100ms_csr_o.ctl_acq_led <= ctl_acq_led_reg;
  fmc_adc_100ms_csr_o.trig_en_ext <= trig_en_ext_reg;
  fmc_adc_100ms_csr_o.trig_en_time <= trig_en_time_reg;
  fmc_adc_100ms_csr_o.trig_en_ch1 <= trig_en_ch1_reg;
  fmc_adc_100ms_csr_o.trig_en_ch2 <= trig_en_ch2_reg;
  fmc_adc_100ms_csr_o.trig_en_ch3 <= trig_en_ch3_reg;
  fmc_adc_100ms_csr_o.trig_en_ch4 <= trig_en_ch4_reg;
  fmc_adc_100ms_csr_o.trig_pol_ext <= trig_pol_ext_reg;
  fmc_adc_100ms_csr_o.trig_pol_ch1 <= trig_pol_ch1_reg;
  fmc_adc_100ms_csr_o.trig_pol_ch2 <= trig_pol_ch2_reg;
  fmc_adc_100ms_csr_o.trig_pol_ch3 <= trig_pol_ch3_reg;
  fmc_adc_100ms_csr_o.trig_pol_ch4 <= trig_pol_ch4_reg;
  fmc_adc_100ms_csr_o.ext_trig_dly <= ext_trig_dly_reg;
  fmc_adc_100ms_csr_o.shots_nbr <= shots_nbr_reg;
  fmc_adc_100ms_csr_o.downsample <= downsample_reg;
  fmc_adc_100ms_csr_o.pre_samples <= pre_samples_reg;
  fmc_adc_100ms_csr_o.post_samples <= post_samples_reg;
  fmc_adc_100ms_csr_o.ch1_ctl_ssr <= ch1_ctl_ssr_reg;
  fmc_adc_100ms_csr_o.ch1_calib_gain <= ch1_calib_gain_reg;
  fmc_adc_100ms_csr_o.ch1_calib_offset <= ch1_calib_offset_reg;
  fmc_adc_100ms_csr_o.ch1_sat_val <= ch1_sat_val_reg;
  fmc_adc_100ms_csr_o.ch1_trig_thres_val <= ch1_trig_thres_val_reg;
  fmc_adc_100ms_csr_o.ch1_trig_thres_hyst <= ch1_trig_thres_hyst_reg;
  fmc_adc_100ms_csr_o.ch1_trig_dly <= ch1_trig_dly_reg;
  fmc_adc_100ms_csr_o.ch2_ctl_ssr <= ch2_ctl_ssr_reg;
  fmc_adc_100ms_csr_o.ch2_calib_gain <= ch2_calib_gain_reg;
  fmc_adc_100ms_csr_o.ch2_calib_offset <= ch2_calib_offset_reg;
  fmc_adc_100ms_csr_o.ch2_sat_val <= ch2_sat_val_reg;
  fmc_adc_100ms_csr_o.ch2_trig_thres_val <= ch2_trig_thres_val_reg;
  fmc_adc_100ms_csr_o.ch2_trig_thres_hyst <= ch2_trig_thres_hyst_reg;
  fmc_adc_100ms_csr_o.ch2_trig_dly <= ch2_trig_dly_reg;
  fmc_adc_100ms_csr_o.ch3_ctl_ssr <= ch3_ctl_ssr_reg;
  fmc_adc_100ms_csr_o.ch3_calib_gain <= ch3_calib_gain_reg;
  fmc_adc_100ms_csr_o.ch3_calib_offset <= ch3_calib_offset_reg;
  fmc_adc_100ms_csr_o.ch3_sat_val <= ch3_sat_val_reg;
  fmc_adc_100ms_csr_o.ch3_trig_thres_val <= ch3_trig_thres_val_reg;
  fmc_adc_100ms_csr_o.ch3_trig_thres_hyst <= ch3_trig_thres_hyst_reg;
  fmc_adc_100ms_csr_o.ch3_trig_dly <= ch3_trig_dly_reg;
  fmc_adc_100ms_csr_o.ch4_ctl_ssr <= ch4_ctl_ssr_reg;
  fmc_adc_100ms_csr_o.ch4_calib_gain <= ch4_calib_gain_reg;
  fmc_adc_100ms_csr_o.ch4_calib_offset <= ch4_calib_offset_reg;
  fmc_adc_100ms_csr_o.ch4_sat_val <= ch4_sat_val_reg;
  fmc_adc_100ms_csr_o.ch4_trig_thres_val <= ch4_trig_thres_val_reg;
  fmc_adc_100ms_csr_o.ch4_trig_thres_hyst <= ch4_trig_thres_hyst_reg;
  fmc_adc_100ms_csr_o.ch4_trig_dly <= ch4_trig_dly_reg;

  -- Process for write requests.
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wr_ack_int <= '0';
        fmc_adc_100ms_csr_o.ctl_wr <= '0';
        ctl_fmc_clk_oe_reg <= '0';
        ctl_offset_dac_clr_n_reg <= '0';
        ctl_test_data_en_reg <= '0';
        ctl_trig_led_reg <= '0';
        ctl_acq_led_reg <= '0';
        trig_en_ext_reg <= '0';
        trig_en_time_reg <= '0';
        trig_en_ch1_reg <= '0';
        trig_en_ch2_reg <= '0';
        trig_en_ch3_reg <= '0';
        trig_en_ch4_reg <= '0';
        trig_pol_ext_reg <= '0';
        trig_pol_ch1_reg <= '0';
        trig_pol_ch2_reg <= '0';
        trig_pol_ch3_reg <= '0';
        trig_pol_ch4_reg <= '0';
        ext_trig_dly_reg <= "00000000000000000000000000000000";
        fmc_adc_100ms_csr_o.sw_trig_wr <= '0';
        shots_nbr_reg <= "0000000000000000";
        downsample_reg <= "00000000000000000000000000000000";
        pre_samples_reg <= "00000000000000000000000000000000";
        post_samples_reg <= "00000000000000000000000000000000";
        ch1_ctl_ssr_reg <= "0000000";
        ch1_calib_gain_reg <= "0000000000000000";
        ch1_calib_offset_reg <= "0000000000000000";
        ch1_sat_val_reg <= "000000000000000";
        ch1_trig_thres_val_reg <= "0000000000000000";
        ch1_trig_thres_hyst_reg <= "0000000000000000";
        ch1_trig_dly_reg <= "00000000000000000000000000000000";
        ch2_ctl_ssr_reg <= "0000000";
        ch2_calib_gain_reg <= "0000000000000000";
        ch2_calib_offset_reg <= "0000000000000000";
        ch2_sat_val_reg <= "000000000000000";
        ch2_trig_thres_val_reg <= "0000000000000000";
        ch2_trig_thres_hyst_reg <= "0000000000000000";
        ch2_trig_dly_reg <= "00000000000000000000000000000000";
        ch3_ctl_ssr_reg <= "0000000";
        ch3_calib_gain_reg <= "0000000000000000";
        ch3_calib_offset_reg <= "0000000000000000";
        ch3_sat_val_reg <= "000000000000000";
        ch3_trig_thres_val_reg <= "0000000000000000";
        ch3_trig_thres_hyst_reg <= "0000000000000000";
        ch3_trig_dly_reg <= "00000000000000000000000000000000";
        ch4_ctl_ssr_reg <= "0000000";
        ch4_calib_gain_reg <= "0000000000000000";
        ch4_calib_offset_reg <= "0000000000000000";
        ch4_sat_val_reg <= "000000000000000";
        ch4_trig_thres_val_reg <= "0000000000000000";
        ch4_trig_thres_hyst_reg <= "0000000000000000";
        ch4_trig_dly_reg <= "00000000000000000000000000000000";
      else
        wr_ack_int <= '0';
        fmc_adc_100ms_csr_o.ctl_wr <= '0';
        fmc_adc_100ms_csr_o.sw_trig_wr <= '0';
        case wb_i.adr(8 downto 2) is
        when "0000000" => 
          -- Register ctl
          fmc_adc_100ms_csr_o.ctl_wr <= wr_int;
          if wr_int = '1' then
            fmc_adc_100ms_csr_o.ctl_fsm_cmd <= wb_i.dat(1 downto 0);
            ctl_fmc_clk_oe_reg <= wb_i.dat(2);
            ctl_offset_dac_clr_n_reg <= wb_i.dat(3);
            fmc_adc_100ms_csr_o.ctl_man_bitslip <= wb_i.dat(4);
            ctl_test_data_en_reg <= wb_i.dat(5);
            ctl_trig_led_reg <= wb_i.dat(6);
            ctl_acq_led_reg <= wb_i.dat(7);
            fmc_adc_100ms_csr_o.ctl_clear_trig_stat <= wb_i.dat(8);
          end if;
          wr_ack_int <= wr_int;
        when "0000001" => 
          -- Register sta
        when "0000010" => 
          -- Register trig_stat
        when "0000011" => 
          -- Register trig_en
          if wr_int = '1' then
            trig_en_ext_reg <= wb_i.dat(0);
            fmc_adc_100ms_csr_o.trig_en_sw <= wb_i.dat(1);
            trig_en_time_reg <= wb_i.dat(4);
            fmc_adc_100ms_csr_o.trig_en_aux_time <= wb_i.dat(5);
            trig_en_ch1_reg <= wb_i.dat(8);
            trig_en_ch2_reg <= wb_i.dat(9);
            trig_en_ch3_reg <= wb_i.dat(10);
            trig_en_ch4_reg <= wb_i.dat(11);
          end if;
          wr_ack_int <= wr_int;
        when "0000100" => 
          -- Register trig_pol
          if wr_int = '1' then
            trig_pol_ext_reg <= wb_i.dat(0);
            trig_pol_ch1_reg <= wb_i.dat(8);
            trig_pol_ch2_reg <= wb_i.dat(9);
            trig_pol_ch3_reg <= wb_i.dat(10);
            trig_pol_ch4_reg <= wb_i.dat(11);
          end if;
          wr_ack_int <= wr_int;
        when "0000101" => 
          -- Register ext_trig_dly
          if wr_int = '1' then
            ext_trig_dly_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "0000110" => 
          -- Register sw_trig
          fmc_adc_100ms_csr_o.sw_trig_wr <= wr_int;
          if wr_int = '1' then
            fmc_adc_100ms_csr_o.sw_trig <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "0000111" => 
          -- Register shots
          if wr_int = '1' then
            shots_nbr_reg <= wb_i.dat(15 downto 0);
            fmc_adc_100ms_csr_o.shots_remain <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "0001000" => 
          -- Register multi_depth
        when "0001001" => 
          -- Register trig_pos
        when "0001010" => 
          -- Register fs_freq
        when "0001011" => 
          -- Register downsample
          if wr_int = '1' then
            downsample_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "0001100" => 
          -- Register pre_samples
          if wr_int = '1' then
            pre_samples_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "0001101" => 
          -- Register post_samples
          if wr_int = '1' then
            post_samples_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "0001110" => 
          -- Register samples_cnt
        when "0100000" => 
          -- Register ch1_ctl
          if wr_int = '1' then
            ch1_ctl_ssr_reg <= wb_i.dat(6 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "0100001" => 
          -- Register ch1_sta
        when "0100010" => 
          -- Register ch1_calib
          if wr_int = '1' then
            ch1_calib_gain_reg <= wb_i.dat(15 downto 0);
            ch1_calib_offset_reg <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "0100011" => 
          -- Register ch1_sat
          if wr_int = '1' then
            ch1_sat_val_reg <= wb_i.dat(14 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "0100100" => 
          -- Register ch1_trig_thres
          if wr_int = '1' then
            ch1_trig_thres_val_reg <= wb_i.dat(15 downto 0);
            ch1_trig_thres_hyst_reg <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "0100101" => 
          -- Register ch1_trig_dly
          if wr_int = '1' then
            ch1_trig_dly_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "0110000" => 
          -- Register ch2_ctl
          if wr_int = '1' then
            ch2_ctl_ssr_reg <= wb_i.dat(6 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "0110001" => 
          -- Register ch2_sta
        when "0110010" => 
          -- Register ch2_calib
          if wr_int = '1' then
            ch2_calib_gain_reg <= wb_i.dat(15 downto 0);
            ch2_calib_offset_reg <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "0110011" => 
          -- Register ch2_sat
          if wr_int = '1' then
            ch2_sat_val_reg <= wb_i.dat(14 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "0110100" => 
          -- Register ch2_trig_thres
          if wr_int = '1' then
            ch2_trig_thres_val_reg <= wb_i.dat(15 downto 0);
            ch2_trig_thres_hyst_reg <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "0110101" => 
          -- Register ch2_trig_dly
          if wr_int = '1' then
            ch2_trig_dly_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "1000000" => 
          -- Register ch3_ctl
          if wr_int = '1' then
            ch3_ctl_ssr_reg <= wb_i.dat(6 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "1000001" => 
          -- Register ch3_sta
        when "1000010" => 
          -- Register ch3_calib
          if wr_int = '1' then
            ch3_calib_gain_reg <= wb_i.dat(15 downto 0);
            ch3_calib_offset_reg <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "1000011" => 
          -- Register ch3_sat
          if wr_int = '1' then
            ch3_sat_val_reg <= wb_i.dat(14 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "1000100" => 
          -- Register ch3_trig_thres
          if wr_int = '1' then
            ch3_trig_thres_val_reg <= wb_i.dat(15 downto 0);
            ch3_trig_thres_hyst_reg <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "1000101" => 
          -- Register ch3_trig_dly
          if wr_int = '1' then
            ch3_trig_dly_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when "1010000" => 
          -- Register ch4_ctl
          if wr_int = '1' then
            ch4_ctl_ssr_reg <= wb_i.dat(6 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "1010001" => 
          -- Register ch4_sta
        when "1010010" => 
          -- Register ch4_calib
          if wr_int = '1' then
            ch4_calib_gain_reg <= wb_i.dat(15 downto 0);
            ch4_calib_offset_reg <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "1010011" => 
          -- Register ch4_sat
          if wr_int = '1' then
            ch4_sat_val_reg <= wb_i.dat(14 downto 0);
          end if;
          wr_ack_int <= wr_int;
        when "1010100" => 
          -- Register ch4_trig_thres
          if wr_int = '1' then
            ch4_trig_thres_val_reg <= wb_i.dat(15 downto 0);
            ch4_trig_thres_hyst_reg <= wb_i.dat(31 downto 16);
          end if;
          wr_ack_int <= wr_int;
        when "1010101" => 
          -- Register ch4_trig_dly
          if wr_int = '1' then
            ch4_trig_dly_reg <= wb_i.dat;
          end if;
          wr_ack_int <= wr_int;
        when others =>
          wr_ack_int <= wr_int;
        end case;
      end if;
    end if;
  end process;

  -- Process for registers read.
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack1_int <= '0';
      else
        reg_rdat_int <= (others => 'X');
        case wb_i.adr(8 downto 2) is
        when "0000000" => 
          -- ctl
          reg_rdat_int(1 downto 0) <= fmc_adc_100ms_csr_i.ctl_fsm_cmd;
          reg_rdat_int(2) <= ctl_fmc_clk_oe_reg;
          reg_rdat_int(3) <= ctl_offset_dac_clr_n_reg;
          reg_rdat_int(4) <= fmc_adc_100ms_csr_i.ctl_man_bitslip;
          reg_rdat_int(5) <= ctl_test_data_en_reg;
          reg_rdat_int(6) <= ctl_trig_led_reg;
          reg_rdat_int(7) <= ctl_acq_led_reg;
          reg_rdat_int(8) <= fmc_adc_100ms_csr_i.ctl_clear_trig_stat;
          rd_ack1_int <= rd_int;
        when "0000001" => 
          -- sta
          reg_rdat_int(2 downto 0) <= fmc_adc_100ms_csr_i.sta_fsm;
          reg_rdat_int(3) <= fmc_adc_100ms_csr_i.sta_serdes_pll;
          reg_rdat_int(4) <= fmc_adc_100ms_csr_i.sta_serdes_synced;
          reg_rdat_int(5) <= fmc_adc_100ms_csr_i.sta_acq_cfg;
          rd_ack1_int <= rd_int;
        when "0000010" => 
          -- trig_stat
          reg_rdat_int(0) <= fmc_adc_100ms_csr_i.trig_stat_ext;
          reg_rdat_int(1) <= fmc_adc_100ms_csr_i.trig_stat_sw;
          reg_rdat_int(4) <= fmc_adc_100ms_csr_i.trig_stat_time;
          reg_rdat_int(8) <= fmc_adc_100ms_csr_i.trig_stat_ch1;
          reg_rdat_int(9) <= fmc_adc_100ms_csr_i.trig_stat_ch2;
          reg_rdat_int(10) <= fmc_adc_100ms_csr_i.trig_stat_ch3;
          reg_rdat_int(11) <= fmc_adc_100ms_csr_i.trig_stat_ch4;
          rd_ack1_int <= rd_int;
        when "0000011" => 
          -- trig_en
          reg_rdat_int(0) <= trig_en_ext_reg;
          reg_rdat_int(1) <= fmc_adc_100ms_csr_i.trig_en_sw;
          reg_rdat_int(4) <= trig_en_time_reg;
          reg_rdat_int(5) <= fmc_adc_100ms_csr_i.trig_en_aux_time;
          reg_rdat_int(8) <= trig_en_ch1_reg;
          reg_rdat_int(9) <= trig_en_ch2_reg;
          reg_rdat_int(10) <= trig_en_ch3_reg;
          reg_rdat_int(11) <= trig_en_ch4_reg;
          rd_ack1_int <= rd_int;
        when "0000100" => 
          -- trig_pol
          reg_rdat_int(0) <= trig_pol_ext_reg;
          reg_rdat_int(8) <= trig_pol_ch1_reg;
          reg_rdat_int(9) <= trig_pol_ch2_reg;
          reg_rdat_int(10) <= trig_pol_ch3_reg;
          reg_rdat_int(11) <= trig_pol_ch4_reg;
          rd_ack1_int <= rd_int;
        when "0000101" => 
          -- ext_trig_dly
          reg_rdat_int <= ext_trig_dly_reg;
          rd_ack1_int <= rd_int;
        when "0000110" => 
          -- sw_trig
          rd_ack1_int <= rd_int;
        when "0000111" => 
          -- shots
          reg_rdat_int(15 downto 0) <= shots_nbr_reg;
          reg_rdat_int(31 downto 16) <= fmc_adc_100ms_csr_i.shots_remain;
          rd_ack1_int <= rd_int;
        when "0001000" => 
          -- multi_depth
          reg_rdat_int <= fmc_adc_100ms_csr_i.multi_depth;
          rd_ack1_int <= rd_int;
        when "0001001" => 
          -- trig_pos
          reg_rdat_int <= fmc_adc_100ms_csr_i.trig_pos;
          rd_ack1_int <= rd_int;
        when "0001010" => 
          -- fs_freq
          reg_rdat_int <= fmc_adc_100ms_csr_i.fs_freq;
          rd_ack1_int <= rd_int;
        when "0001011" => 
          -- downsample
          reg_rdat_int <= downsample_reg;
          rd_ack1_int <= rd_int;
        when "0001100" => 
          -- pre_samples
          reg_rdat_int <= pre_samples_reg;
          rd_ack1_int <= rd_int;
        when "0001101" => 
          -- post_samples
          reg_rdat_int <= post_samples_reg;
          rd_ack1_int <= rd_int;
        when "0001110" => 
          -- samples_cnt
          reg_rdat_int <= fmc_adc_100ms_csr_i.samples_cnt;
          rd_ack1_int <= rd_int;
        when "0100000" => 
          -- ch1_ctl
          reg_rdat_int(6 downto 0) <= ch1_ctl_ssr_reg;
          rd_ack1_int <= rd_int;
        when "0100001" => 
          -- ch1_sta
          reg_rdat_int(15 downto 0) <= fmc_adc_100ms_csr_i.ch1_sta_val;
          rd_ack1_int <= rd_int;
        when "0100010" => 
          -- ch1_calib
          reg_rdat_int(15 downto 0) <= ch1_calib_gain_reg;
          reg_rdat_int(31 downto 16) <= ch1_calib_offset_reg;
          rd_ack1_int <= rd_int;
        when "0100011" => 
          -- ch1_sat
          reg_rdat_int(14 downto 0) <= ch1_sat_val_reg;
          rd_ack1_int <= rd_int;
        when "0100100" => 
          -- ch1_trig_thres
          reg_rdat_int(15 downto 0) <= ch1_trig_thres_val_reg;
          reg_rdat_int(31 downto 16) <= ch1_trig_thres_hyst_reg;
          rd_ack1_int <= rd_int;
        when "0100101" => 
          -- ch1_trig_dly
          reg_rdat_int <= ch1_trig_dly_reg;
          rd_ack1_int <= rd_int;
        when "0110000" => 
          -- ch2_ctl
          reg_rdat_int(6 downto 0) <= ch2_ctl_ssr_reg;
          rd_ack1_int <= rd_int;
        when "0110001" => 
          -- ch2_sta
          reg_rdat_int(15 downto 0) <= fmc_adc_100ms_csr_i.ch2_sta_val;
          rd_ack1_int <= rd_int;
        when "0110010" => 
          -- ch2_calib
          reg_rdat_int(15 downto 0) <= ch2_calib_gain_reg;
          reg_rdat_int(31 downto 16) <= ch2_calib_offset_reg;
          rd_ack1_int <= rd_int;
        when "0110011" => 
          -- ch2_sat
          reg_rdat_int(14 downto 0) <= ch2_sat_val_reg;
          rd_ack1_int <= rd_int;
        when "0110100" => 
          -- ch2_trig_thres
          reg_rdat_int(15 downto 0) <= ch2_trig_thres_val_reg;
          reg_rdat_int(31 downto 16) <= ch2_trig_thres_hyst_reg;
          rd_ack1_int <= rd_int;
        when "0110101" => 
          -- ch2_trig_dly
          reg_rdat_int <= ch2_trig_dly_reg;
          rd_ack1_int <= rd_int;
        when "1000000" => 
          -- ch3_ctl
          reg_rdat_int(6 downto 0) <= ch3_ctl_ssr_reg;
          rd_ack1_int <= rd_int;
        when "1000001" => 
          -- ch3_sta
          reg_rdat_int(15 downto 0) <= fmc_adc_100ms_csr_i.ch3_sta_val;
          rd_ack1_int <= rd_int;
        when "1000010" => 
          -- ch3_calib
          reg_rdat_int(15 downto 0) <= ch3_calib_gain_reg;
          reg_rdat_int(31 downto 16) <= ch3_calib_offset_reg;
          rd_ack1_int <= rd_int;
        when "1000011" => 
          -- ch3_sat
          reg_rdat_int(14 downto 0) <= ch3_sat_val_reg;
          rd_ack1_int <= rd_int;
        when "1000100" => 
          -- ch3_trig_thres
          reg_rdat_int(15 downto 0) <= ch3_trig_thres_val_reg;
          reg_rdat_int(31 downto 16) <= ch3_trig_thres_hyst_reg;
          rd_ack1_int <= rd_int;
        when "1000101" => 
          -- ch3_trig_dly
          reg_rdat_int <= ch3_trig_dly_reg;
          rd_ack1_int <= rd_int;
        when "1010000" => 
          -- ch4_ctl
          reg_rdat_int(6 downto 0) <= ch4_ctl_ssr_reg;
          rd_ack1_int <= rd_int;
        when "1010001" => 
          -- ch4_sta
          reg_rdat_int(15 downto 0) <= fmc_adc_100ms_csr_i.ch4_sta_val;
          rd_ack1_int <= rd_int;
        when "1010010" => 
          -- ch4_calib
          reg_rdat_int(15 downto 0) <= ch4_calib_gain_reg;
          reg_rdat_int(31 downto 16) <= ch4_calib_offset_reg;
          rd_ack1_int <= rd_int;
        when "1010011" => 
          -- ch4_sat
          reg_rdat_int(14 downto 0) <= ch4_sat_val_reg;
          rd_ack1_int <= rd_int;
        when "1010100" => 
          -- ch4_trig_thres
          reg_rdat_int(15 downto 0) <= ch4_trig_thres_val_reg;
          reg_rdat_int(31 downto 16) <= ch4_trig_thres_hyst_reg;
          rd_ack1_int <= rd_int;
        when "1010101" => 
          -- ch4_trig_dly
          reg_rdat_int <= ch4_trig_dly_reg;
          rd_ack1_int <= rd_int;
        when others =>
          reg_rdat_int <= (others => 'X');
          rd_ack1_int <= rd_int;
        end case;
      end if;
    end if;
  end process;

  -- Process for read requests.
  process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
    -- By default ack read requests
    wb_o.dat <= (others => '0');
    case wb_i.adr(8 downto 2) is
    when "0000000" => 
      -- ctl
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0000001" => 
      -- sta
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0000010" => 
      -- trig_stat
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0000011" => 
      -- trig_en
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0000100" => 
      -- trig_pol
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0000101" => 
      -- ext_trig_dly
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0000110" => 
      -- sw_trig
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0000111" => 
      -- shots
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0001000" => 
      -- multi_depth
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0001001" => 
      -- trig_pos
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0001010" => 
      -- fs_freq
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0001011" => 
      -- downsample
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0001100" => 
      -- pre_samples
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0001101" => 
      -- post_samples
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0001110" => 
      -- samples_cnt
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0100000" => 
      -- ch1_ctl
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0100001" => 
      -- ch1_sta
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0100010" => 
      -- ch1_calib
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0100011" => 
      -- ch1_sat
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0100100" => 
      -- ch1_trig_thres
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0100101" => 
      -- ch1_trig_dly
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0110000" => 
      -- ch2_ctl
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0110001" => 
      -- ch2_sta
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0110010" => 
      -- ch2_calib
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0110011" => 
      -- ch2_sat
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0110100" => 
      -- ch2_trig_thres
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "0110101" => 
      -- ch2_trig_dly
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1000000" => 
      -- ch3_ctl
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1000001" => 
      -- ch3_sta
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1000010" => 
      -- ch3_calib
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1000011" => 
      -- ch3_sat
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1000100" => 
      -- ch3_trig_thres
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1000101" => 
      -- ch3_trig_dly
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1010000" => 
      -- ch4_ctl
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1010001" => 
      -- ch4_sta
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1010010" => 
      -- ch4_calib
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1010011" => 
      -- ch4_sat
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1010100" => 
      -- ch4_trig_thres
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when "1010101" => 
      -- ch4_trig_dly
      wb_o.dat <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
    when others =>
      rd_ack_int <= rd_int;
    end case;
  end process;
end syn;
