# fmc_adc_100ms_csr

### FMC ADC 100MS/s core registers

Wishbone slave for FMC ADC 100MS/s core

### 1. Memory map summary

HW address | Type | Name | HDL prefix | C prefix
--- | --- | --- | --- | ---
0x000 | REG | ctl | ctl | ctl
0x004 | REG | sta | sta | sta
0x008 | REG | trig_stat | trig_stat | trig_stat
0x00c | REG | trig_en | trig_en | trig_en
0x010 | REG | trig_pol | trig_pol | trig_pol
0x014 | REG | ext_trig_dly | ext_trig_dly | ext_trig_dly
0x018 | REG | sw_trig | sw_trig | sw_trig
0x01c | REG | shots | shots | shots
0x020 | REG | multi_depth | multi_depth | multi_depth
0x024 | REG | trig_pos | trig_pos | trig_pos
0x028 | REG | fs_freq | fs_freq | fs_freq
0x02c | REG | downsample | downsample | downsample
0x030 | REG | pre_samples | pre_samples | pre_samples
0x034 | REG | post_samples | post_samples | post_samples
0x038 | REG | samples_cnt | samples_cnt | samples_cnt
0x080 | REG | ch1_ctl | ch1_ctl | ch1_ctl
0x084 | REG | ch1_sta | ch1_sta | ch1_sta
0x088 | REG | ch1_calib | ch1_calib | ch1_calib
0x08c | REG | ch1_sat | ch1_sat | ch1_sat
0x090 | REG | ch1_trig_thres | ch1_trig_thres | ch1_trig_thres
0x094 | REG | ch1_trig_dly | ch1_trig_dly | ch1_trig_dly
0x0c0 | REG | ch2_ctl | ch2_ctl | ch2_ctl
0x0c4 | REG | ch2_sta | ch2_sta | ch2_sta
0x0c8 | REG | ch2_calib | ch2_calib | ch2_calib
0x0cc | REG | ch2_sat | ch2_sat | ch2_sat
0x0d0 | REG | ch2_trig_thres | ch2_trig_thres | ch2_trig_thres
0x0d4 | REG | ch2_trig_dly | ch2_trig_dly | ch2_trig_dly
0x100 | REG | ch3_ctl | ch3_ctl | ch3_ctl
0x104 | REG | ch3_sta | ch3_sta | ch3_sta
0x108 | REG | ch3_calib | ch3_calib | ch3_calib
0x10c | REG | ch3_sat | ch3_sat | ch3_sat
0x110 | REG | ch3_trig_thres | ch3_trig_thres | ch3_trig_thres
0x114 | REG | ch3_trig_dly | ch3_trig_dly | ch3_trig_dly
0x140 | REG | ch4_ctl | ch4_ctl | ch4_ctl
0x144 | REG | ch4_sta | ch4_sta | ch4_sta
0x148 | REG | ch4_calib | ch4_calib | ch4_calib
0x14c | REG | ch4_sat | ch4_sat | ch4_sat
0x150 | REG | ch4_trig_thres | ch4_trig_thres | ch4_trig_thres
0x154 | REG | ch4_trig_dly | ch4_trig_dly | ch4_trig_dly

### 2. Register description

### 2.1. ctl

HW prefix: | ctl
HW address: | 0x0
C prefix: | ctl
C block offset: | 0x0

Control register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | clear_trig_stat
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
acq_led | trig_led | test_data_en | man_bitslip | offset_dac_clr_n | fmc_clk_oe | fsm_cmd[1:0]

- fsm_cmd [rw]: State machine commands (ignore on read)
  1: ACQ_START (start acquisition, only when FSM is idle)
  2: ACQ_STOP (stop acquisition, anytime)
- fmc_clk_oe [rw]: FMC Si750 output enable
- offset_dac_clr_n [rw]: Offset DACs clear (active low)
- man_bitslip [rw]: Manual serdes bitslip (ignore on read)
- test_data_en [rw]: Enable test data
  Write the DDR RAM address counter value instead of ADC data to DDR.
  Note that no timetags are appended at the end of test data.
- trig_led [rw]: Manual TRIG LED
  Manual control of the front panel TRIG LED
- acq_led [rw]: Manual ACQ LED
  Manual control of the front panel ACQ LED
- clear_trig_stat [rw]: Clear trigger status
  Write 1 to clear the last trigger status register. Auto-resets to zero.

### 2.2. sta

HW prefix: | sta
HW address: | 0x4
C prefix: | sta
C block offset: | 0x4

Status register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | acq_cfg | serdes_synced | serdes_pll | fsm[2:0]

- fsm [ro]: State machine status
  States:
  0: illegal
  1: IDLE
  2: PRE_TRIG
  3: WAIT_TRIG
  4: POST_TRIG
  5: TRIG_TAG
  6: DECR_SHOT
  7: illegal
- serdes_pll [ro]: SerDes PLL status
  Sampling clock recovery PLL.
  0: not locked
  1: locked
- serdes_synced [ro]: SerDes synchronization status
  0: bitslip in progress
  1: serdes synchronized
- acq_cfg [ro]: Acquisition configuration status
  0: Unauthorised acquisition configuration (will prevent acquisition to start)
  1: Valid acquisition configuration
  - Shot number > 0
  - Post-trigger sample > 0

### 2.3. trig_stat

HW prefix: | trig_stat
HW address: | 0x8
C prefix: | trig_stat
C block offset: | 0x8

Trigger status

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | ch4 | ch3 | ch2 | ch1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | time | - | - | sw | ext

- ext [ro]: External trigger input
  0: not triggered
  1: triggered
- sw [ro]: Software trigger
  0: not triggered
  1: triggered
- time [ro]: Timetag trigger
  0: not triggered
  1: triggered
- ch1 [ro]: Channel 1 internal threshold trigger
  0: not triggered
  1: triggered
- ch2 [ro]: Channel 2 internal threshold trigger
  0: not triggered
  1: triggered
- ch3 [ro]: Channel 3 internal threshold trigger
  0: not triggered
  1: triggered
- ch4 [ro]: Channel 4 internal threshold trigger
  0: not triggered
  1: triggered

### 2.4. trig_en

HW prefix: | trig_en
HW address: | 0xc
C prefix: | trig_en
C block offset: | 0xc

Trigger enable

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | ch4 | ch3 | ch2 | ch1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | aux_time | time | - | - | sw | ext

- ext [rw]: External trigger input
  0: disable
  1: enable
- sw [rw]: Software trigger
  Always enabled
- time [rw]: Timetag trigger
  0: disable
  1: enable
- aux_time [rw]: Auxiliary timetag trigger
  Always enabled
- ch1 [rw]: Channel 1 internal threshold trigger
  0: disable
  1: enable
- ch2 [rw]: Channel 2 internal threshold trigger
  0: disable
  1: enable
- ch3 [rw]: Channel 3 internal threshold trigger
  0: disable
  1: enable
- ch4 [rw]: Channel 4 internal threshold trigger
  0: disable
  1: enable

### 2.5. trig_pol

HW prefix: | trig_pol
HW address: | 0x10
C prefix: | trig_pol
C block offset: | 0x10

Trigger polarity

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | ch4 | ch3 | ch2 | ch1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | ext

- ext [rw]: External trigger input
  0: positive edge/slope
  1: negative edge/slope
- ch1 [rw]: Channel 1 internal threshold trigger
  0: positive edge/slope
  1: negative edge/slope
- ch2 [rw]: Channel 2 internal threshold trigger
  0: positive edge/slope
  1: negative edge/slope
- ch3 [rw]: Channel 3 internal threshold trigger
  0: positive edge/slope
  1: negative edge/slope
- ch4 [rw]: Channel 4 internal threshold trigger
  0: positive edge/slope
  1: negative edge/slope

### 2.6. ext_trig_dly

HW prefix: | ext_trig_dly
HW address: | 0x14
C prefix: | ext_trig_dly
C block offset: | 0x14

External trigger delay

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ext_trig_dly[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ext_trig_dly[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ext_trig_dly[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ext_trig_dly[7:0]

- ext_trig_dly [rw]: External trigger delay

### 2.7. sw_trig

HW prefix: | sw_trig
HW address: | 0x18
C prefix: | sw_trig
C block offset: | 0x18

Software trigger

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
sw_trig[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
sw_trig[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
sw_trig[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
sw_trig[7:0]

- sw_trig [wo]: Software trigger

### 2.8. shots

HW prefix: | shots
HW address: | 0x1c
C prefix: | shots
C block offset: | 0x1c

Number of shots

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
remain[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
remain[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
nbr[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
nbr[7:0]

- nbr [rw]: Number of shots
  Number of shots required in multi-shot mode, set to one for single-shot mode.
- remain [rw]: Remaining shots counter
  Counts the number of remaining shots to acquire.

### 2.9. multi_depth

HW prefix: | multi_depth
HW address: | 0x20
C prefix: | multi_depth
C block offset: | 0x20

Multi-shot sample depth register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
multi_depth[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
multi_depth[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
multi_depth[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
multi_depth[7:0]

- multi_depth [ro]: Multi-shot sample depth register

### 2.10. trig_pos

HW prefix: | trig_pos
HW address: | 0x24
C prefix: | trig_pos
C block offset: | 0x24

Trigger address register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
trig_pos[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
trig_pos[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
trig_pos[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
trig_pos[7:0]

- trig_pos [ro]: Trigger address register

### 2.11. fs_freq

HW prefix: | fs_freq
HW address: | 0x28
C prefix: | fs_freq
C block offset: | 0x28

Sampling clock frequency

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
fs_freq[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
fs_freq[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
fs_freq[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
fs_freq[7:0]

- fs_freq [ro]: Sampling clock frequency

### 2.12. downsample

HW prefix: | downsample
HW address: | 0x2c
C prefix: | downsample
C block offset: | 0x2c

Downsampling ratio

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
downsample[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
downsample[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
downsample[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
downsample[7:0]

- downsample [rw]: Downsampling ratio

### 2.13. pre_samples

HW prefix: | pre_samples
HW address: | 0x30
C prefix: | pre_samples
C block offset: | 0x30

Pre-trigger samples

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
pre_samples[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
pre_samples[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
pre_samples[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
pre_samples[7:0]

- pre_samples [rw]: Pre-trigger samples

### 2.14. post_samples

HW prefix: | post_samples
HW address: | 0x34
C prefix: | post_samples
C block offset: | 0x34

Post-trigger samples

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
post_samples[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
post_samples[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
post_samples[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
post_samples[7:0]

- post_samples [rw]: Post-trigger samples

### 2.15. samples_cnt

HW prefix: | samples_cnt
HW address: | 0x38
C prefix: | samples_cnt
C block offset: | 0x38

Samples counter

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
samples_cnt[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
samples_cnt[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
samples_cnt[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
samples_cnt[7:0]

- samples_cnt [ro]: Samples counter

### 2.16. ch1_ctl

HW prefix: | ch1_ctl
HW address: | 0x80
C prefix: | ch1_ctl
C block offset: | 0x80

Channel 1 control register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | ssr[6:0]

- ssr [rw]: Solid state relays control for channel 1
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

### 2.17. ch1_sta

HW prefix: | ch1_sta
HW address: | 0x84
C prefix: | ch1_sta
C block offset: | 0x84

Channel 1 status register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
val[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [ro]: Channel 1 current ADC value
  Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
  configured for "offset binary". The FMC-ADC driver when loaded, will change this to
  binary two\'s complement.

### 2.18. ch1_calib

HW prefix: | ch1_calib
HW address: | 0x88
C prefix: | ch1_calib
C block offset: | 0x88

Channel 1 calibration register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
offset[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
offset[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
gain[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
gain[7:0]

- gain [rw]: Gain calibration for channel 1
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- offset [rw]: Offset calibration for channel 1
  Offset applied to all data coming from the ADC. The format is binary two\'s complement.

### 2.19. ch1_sat

HW prefix: | ch1_sat
HW address: | 0x8c
C prefix: | ch1_sat
C block offset: | 0x8c

Channel 1 saturation register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | val[14:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [rw]: Saturation value for channel 1
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

### 2.20. ch1_trig_thres

HW prefix: | ch1_trig_thres
HW address: | 0x90
C prefix: | ch1_trig_thres
C block offset: | 0x90

Channel 1 trigger threshold configuration register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
hyst[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
hyst[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
val[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [rw]: Threshold for internal trigger
  Treated as binary two\'s complement and compared to raw ADC data.
- hyst [rw]: Internal trigger threshold hysteresis
  Configures the internal trigger threshold hysteresis.
  The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.

### 2.21. ch1_trig_dly

HW prefix: | ch1_trig_dly
HW address: | 0x94
C prefix: | ch1_trig_dly
C block offset: | 0x94

Channel 1 trigger delay

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ch1_trig_dly[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ch1_trig_dly[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ch1_trig_dly[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ch1_trig_dly[7:0]

- ch1_trig_dly [rw]: Channel 1 trigger delay

### 2.22. ch2_ctl

HW prefix: | ch2_ctl
HW address: | 0xc0
C prefix: | ch2_ctl
C block offset: | 0xc0

Channel 2 control register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | ssr[6:0]

- ssr [rw]: Solid state relays control for channel 2
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

### 2.23. ch2_sta

HW prefix: | ch2_sta
HW address: | 0xc4
C prefix: | ch2_sta
C block offset: | 0xc4

Channel 2 status register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
val[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [ro]: Channel 2 current ACD value
  Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
  configured for "offset binary". The FMC-ADC driver when loaded, will change this to
  binary two\'s complement.

### 2.24. ch2_calib

HW prefix: | ch2_calib
HW address: | 0xc8
C prefix: | ch2_calib
C block offset: | 0xc8

Channel 2 calibration register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
offset[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
offset[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
gain[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
gain[7:0]

- gain [rw]: Gain calibration for channel 2
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- offset [rw]: Offset calibration for channel 2
  Offset applied to all data coming from the ADC. The format is binary two\'s complement.

### 2.25. ch2_sat

HW prefix: | ch2_sat
HW address: | 0xcc
C prefix: | ch2_sat
C block offset: | 0xcc

Channel 2 saturation register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | val[14:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [rw]: Saturation value for channel 2
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

### 2.26. ch2_trig_thres

HW prefix: | ch2_trig_thres
HW address: | 0xd0
C prefix: | ch2_trig_thres
C block offset: | 0xd0

Channel 2 trigger threshold configuration register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
hyst[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
hyst[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
val[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [rw]: Threshold for internal trigger
  Treated as binary two\'s complement and compared to raw ADC data.
- hyst [rw]: Internal trigger threshold hysteresis
  Configures the internal trigger threshold hysteresis.
  The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.

### 2.27. ch2_trig_dly

HW prefix: | ch2_trig_dly
HW address: | 0xd4
C prefix: | ch2_trig_dly
C block offset: | 0xd4

Channel 2 trigger delay

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ch2_trig_dly[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ch2_trig_dly[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ch2_trig_dly[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ch2_trig_dly[7:0]

- ch2_trig_dly [rw]: Channel 2 trigger delay

### 2.28. ch3_ctl

HW prefix: | ch3_ctl
HW address: | 0x100
C prefix: | ch3_ctl
C block offset: | 0x100

Channel 3 control register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | ssr[6:0]

- ssr [rw]: Solid state relays control for channel 3
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

### 2.29. ch3_sta

HW prefix: | ch3_sta
HW address: | 0x104
C prefix: | ch3_sta
C block offset: | 0x104

Channel 3 status register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
val[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [ro]: Channel 3 current ADC value
  Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
  configured for "offset binary". The FMC-ADC driver when loaded, will change this to
  binary two\'s complement.

### 2.30. ch3_calib

HW prefix: | ch3_calib
HW address: | 0x108
C prefix: | ch3_calib
C block offset: | 0x108

Channel 3 calibration register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
offset[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
offset[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
gain[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
gain[7:0]

- gain [rw]: Gain calibration for channel 3
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- offset [rw]: Offset calibration for channel 3
  Offset applied to all data coming from the ADC. The format is binary two\'s complement.

### 2.31. ch3_sat

HW prefix: | ch3_sat
HW address: | 0x10c
C prefix: | ch3_sat
C block offset: | 0x10c

Channel 3 saturation register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | val[14:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [rw]: Saturation value for channel 3
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

### 2.32. ch3_trig_thres

HW prefix: | ch3_trig_thres
HW address: | 0x110
C prefix: | ch3_trig_thres
C block offset: | 0x110

Channel 3 trigger threshold configuration register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
hyst[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
hyst[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
val[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [rw]: Threshold for internal trigger
  Treated as binary two\'s complement and compared to raw ADC data.
- hyst [rw]: Internal trigger threshold hysteresis
  Configures the internal trigger threshold hysteresis.
  The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.

### 2.33. ch3_trig_dly

HW prefix: | ch3_trig_dly
HW address: | 0x114
C prefix: | ch3_trig_dly
C block offset: | 0x114

Channel 3 trigger delay

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ch3_trig_dly[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ch3_trig_dly[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ch3_trig_dly[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ch3_trig_dly[7:0]

- ch3_trig_dly [rw]: Channel 3 trigger delay

### 2.34. ch4_ctl

HW prefix: | ch4_ctl
HW address: | 0x140
C prefix: | ch4_ctl
C block offset: | 0x140

Channel 4 control register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | ssr[6:0]

- ssr [rw]: Solid state relays control for channel 4
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

### 2.35. ch4_sta

HW prefix: | ch4_sta
HW address: | 0x144
C prefix: | ch4_sta
C block offset: | 0x144

Channel 4 status register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
val[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [ro]: Channel 4 current ADC value
  Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
  configured for "offset binary". The FMC-ADC driver when loaded, will change this to
  binary two\'s complement.

### 2.36. ch4_calib

HW prefix: | ch4_calib
HW address: | 0x148
C prefix: | ch4_calib
C block offset: | 0x148

Channel 4 gain calibration register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
offset[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
offset[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
gain[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
gain[7:0]

- gain [rw]: Gain calibration for channel 4
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- offset [rw]: Offset calibration for channel 4
  Offset applied to all data coming from the ADC. The format is binary two\'s complement.

### 2.37. ch4_sat

HW prefix: | ch4_sat
HW address: | 0x14c
C prefix: | ch4_sat
C block offset: | 0x14c

Channel 4 saturation register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | val[14:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [rw]: Saturation value for channel 4
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

### 2.38. ch4_trig_thres

HW prefix: | ch4_trig_thres
HW address: | 0x150
C prefix: | ch4_trig_thres
C block offset: | 0x150

Channel 4 trigger threshold configuration register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
hyst[15:8]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
hyst[7:0]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
val[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
val[7:0]

- val [rw]: Threshold for internal trigger
  Treated as binary two\'s complement and compared to raw ADC data.
- hyst [rw]: Internal trigger threshold hysteresis
  Configures the internal trigger threshold hysteresis.
  The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.

### 2.39. ch4_trig_dly

HW prefix: | ch4_trig_dly
HW address: | 0x154
C prefix: | ch4_trig_dly
C block offset: | 0x154

Channel 4 trigger delay

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ch4_trig_dly[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ch4_trig_dly[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ch4_trig_dly[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ch4_trig_dly[7:0]

- ch4_trig_dly [rw]: Channel 4 trigger delay