# alt_trigout

### FMC ADC alt trigger out registers

### 1. Memory map summary

HW address | Type | Name | HDL prefix | C prefix
--- | --- | --- | --- | ---
0x00 | REG | status | status | status
0x08 | REG | ts_mask_sec | ts_mask_sec | ts_mask_sec
0x10 | REG | ts_cycles | ts_cycles | ts_cycles

### 2. Register description

### 2.1. status

HW prefix: | status
HW address: | 0x0
C prefix: | status
C block offset: | 0x0

Status register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | ts_present
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | wr_valid | wr_link | wr_enable

- wr_enable [ro]: Set when WR is enabled
- wr_link [ro]: WR link status
- wr_valid [ro]: Set when WR time is valid
- ts_present [ro]: Set when the timestamp fifo is not empty

### 2.2. ts_mask_sec

HW prefix: | ts_mask_sec
HW address: | 0x8
C prefix: | ts_mask_sec
C block offset: | 0x8

Time (seconds) of the last event

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56
- | - | - | - | - | - | - | ext_mask
55 | 54 | 53 | 52 | 51 | 50 | 49 | 48
- | - | - | - | ch4_mask | ch3_mask | ch2_mask | ch1_mask
47 | 46 | 45 | 44 | 43 | 42 | 41 | 40
- | - | - | - | - | - | - | -
39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
ts_sec[39:32]
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ts_sec[31:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ts_sec[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ts_sec[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ts_sec[7:0]

- ts_sec [ro]: Seconds part of the timestamp
- ch1_mask [ro]: Set if channel 1 triggered
- ch2_mask [ro]: Set if channel 2 triggered
- ch3_mask [ro]: Set if channel 3 triggered
- ch4_mask [ro]: Set if channel 4 triggered
- ext_mask [ro]: Set if external trigger

### 2.3. ts_cycles

HW prefix: | ts_cycles
HW address: | 0x10
C prefix: | ts_cycles
C block offset: | 0x10

Cycles part of timestamp fifo.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | cycles[27:24]
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
cycles[23:16]
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
cycles[15:8]
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
cycles[7:0]

- cycles [ro]: Cycles