ddr3_ctrl Project Status
Project File: | spec_fmc_adc_100Ms.xise | Parser Errors: | No Errors
Module Name: | ddr3_ctrl | Implementation State: | New

Target Device:

xc6slx45t-3fgg484

- Errors:

Product Version:

ISE 12.2

- Warnings:

Design Goal:</dif>

Balanced

- Routing Results:

Design Strategy:</dif>

Xilinx Default (unlocked)

- Timing Constraints:

Environment:</dif>

- Final Timing Score:

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 02/24/2011 - 10:27:57