spec_top Project Status (03/09/2011 - 11:19:20)
Project File: | spec_fmc_adc_100Ms.xise | Parser Errors: | No Errors
Module Name: | spec_top | Implementation State: | Programming File Generated

Target Device:

xc6slx45t-3fgg484

- Errors:

No Errors

Product Version:

ISE 12.2

- Warnings:

803 Warnings (15 new)

Design Goal:</dif>

Timing Performance

- Routing Results:

All Signals Completely Routed

Design Strategy:</dif>

Performance with IOB Packing

- Timing Constraints:

X 1 Failing Constraint

Environment:</dif>

System Settings

- Final Timing Score:

792 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 5,481 | 54,576 | 10% |
Number used as Flip Flops | 5,446 |  |  |
Number used as Latches | 35 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 3,980 | 27,288 | 14% |
Number used as logic | 3,535 | 27,288 | 12% |
Number using O6 output only | 2,434 |  |  |
Number using O5 output only | 83 |  |  |
Number using O5 and O6 | 1,018 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 8 | 6,408 | 1% |
Number used as Dual Port RAM | 0 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 8 |  |  |
Number using O6 output only | 8 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used exclusively as route-thrus | 437 |  |  |
Number with same-slice register load | 434 |  |  |
Number with same-slice carry load | 3 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 1,947 | 6,822 | 28% |
Number of LUT Flip Flop pairs used | 5,861 |  |  |
Number with an unused Flip Flop | 1,185 | 5,861 | 20% |
Number with an unused LUT | 1,881 | 5,861 | 32% |
Number of fully used LUT-FF pairs | 2,795 | 5,861 | 47% |
Number of unique control sets | 378 |  |  |
Number of slice register sites lost to control set restrictions | 1,655 | 54,576 | 3% |
Number of bonded IOBs | 178 | 296 | 60% |
Number of LOCed IOBs | 178 | 178 | 100% |
IOB Flip Flops | 40 |  |  |
Number of RAMB16BWERs | 11 | 116 | 9% |
Number of RAMB8BWERs | 0 | 232 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 3 | 32 | 9% |
Number used as BUFIO2s | 3 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2FBs | 1 |  |  |
Number used as BUFIO2FB_2CLKs | 0 |  |  |
Number of BUFG/BUFGMUXs | 8 | 16 | 50% |
Number used as BUFGs | 8 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 8 | 0% |
Number of ILOGIC2/ISERDES2s | 42 | 376 | 11% |
Number used as ILOGIC2s | 4 |  |  |
Number used as ISERDES2s | 38 |  |  |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 25 | 376 | 6% |
Number used as IODELAY2s | 2 |  |  |
Number used as IODRP2s | 1 |  |  |
Number used as IODRP2_MCBs | 22 |  |  |
Number of OLOGIC2/OSERDES2s | 102 | 376 | 27% |
Number used as OLOGIC2s | 36 |  |  |
Number used as OSERDES2s | 66 |  |  |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 256 | 0% |
Number of BUFPLLs | 2 | 8 | 25% |
Number of BUFPLL_MCBs | 1 | 4 | 25% |
Number of DSP48A1s | 0 | 58 | 0% |
Number of GTPA1_DUALs | 0 | 2 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 1 | 2 | 50% |
Number of PCIE_A1s | 0 | 1 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 4 | 4 | 100% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.65 |  |  |

Performance Summary | [-]
Final Timing Score: | 792 (Setup: 792, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | X 1 Failing Constraint |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Wed Mar 9 11:04:38 2011 | 0 | 724 Warnings (10 new) | 233 Infos (1 new)
Translation Report | Current | Wed Mar 9 11:05:05 2011 | 0 | 18 Warnings (5 new) | 19 Infos (0 new)
Map Report | Current | Wed Mar 9 11:11:34 2011 | 0 | 43 Warnings (0 new) | 10 Infos (0 new)
Place and Route Report | Current | Wed Mar 9 11:14:54 2011 | 0 | 8 Warnings (0 new) | 3 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Wed Mar 9 11:15:35 2011 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | Wed Mar 9 11:19:14 2011 | 0 | 10 Warnings (0 new) | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Log File | Current | Wed Mar 9 11:19:20 2011

Date Generated: 03/09/2011 - 11:19:20