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-- Title          : Wishbone slave core for FMC ADC 100MS/s core registers
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-- File           : ../fmc_adc_100Ms_csr.vhd
-- Author         : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created        : Thu Mar 21 13:57:25 2019
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.fmc_adc_100ms_csr_wbgen2_pkg.all;


entity fmc_adc_100ms_csr is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(7 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_err_o                                 : out    std_logic;
    wb_rty_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    fs_clk_i                                 : in     std_logic;
    regs_i                                   : in     t_fmc_adc_100ms_csr_in_registers;
    regs_o                                   : out    t_fmc_adc_100ms_csr_out_registers
  );
end fmc_adc_100ms_csr;

architecture syn of fmc_adc_100ms_csr is

signal fmc_adc_100ms_csr_ctl_fmc_clk_oe_int     : std_logic      ;
signal fmc_adc_100ms_csr_ctl_offset_dac_clr_n_int : std_logic      ;
signal fmc_adc_100ms_csr_ctl_man_bitslip_int    : std_logic      ;
signal fmc_adc_100ms_csr_ctl_man_bitslip_int_delay : std_logic      ;
signal fmc_adc_100ms_csr_ctl_man_bitslip_sync0  : std_logic      ;
signal fmc_adc_100ms_csr_ctl_man_bitslip_sync1  : std_logic      ;
signal fmc_adc_100ms_csr_ctl_man_bitslip_sync2  : std_logic      ;
signal fmc_adc_100ms_csr_ctl_test_data_en_int   : std_logic      ;
signal fmc_adc_100ms_csr_ctl_trig_led_int       : std_logic      ;
signal fmc_adc_100ms_csr_ctl_acq_led_int        : std_logic      ;
signal fmc_adc_100ms_csr_ctl_clear_trig_stat_dly0 : std_logic      ;
signal fmc_adc_100ms_csr_ctl_clear_trig_stat_int : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ext_int        : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ext_sync0      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ext_sync1      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_sw_int         : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_sw_sync0       : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_sw_sync1       : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_time_int       : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_time_sync0     : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_time_sync1     : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_alt_time_int   : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_alt_time_sync0 : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_alt_time_sync1 : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch1_int        : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch1_sync0      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch1_sync1      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch2_int        : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch2_sync0      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch2_sync1      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch3_int        : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch3_sync0      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch3_sync1      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch4_int        : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch4_sync0      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_ch4_sync1      : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_fwd_ext_int    : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_fwd_ch1_int    : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_fwd_ch2_int    : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_fwd_ch3_int    : std_logic      ;
signal fmc_adc_100ms_csr_trig_en_fwd_ch4_int    : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ext_int       : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ext_sync0     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ext_sync1     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch1_int       : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch1_sync0     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch1_sync1     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch2_int       : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch2_sync0     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch2_sync1     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch3_int       : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch3_sync0     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch3_sync1     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch4_int       : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch4_sync0     : std_logic      ;
signal fmc_adc_100ms_csr_trig_pol_ch4_sync1     : std_logic      ;
signal fmc_adc_100ms_csr_ext_trig_dly_int       : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_sw_trig_wr_int         : std_logic      ;
signal fmc_adc_100ms_csr_sw_trig_wr_int_delay   : std_logic      ;
signal fmc_adc_100ms_csr_sw_trig_wr_sync0       : std_logic      ;
signal fmc_adc_100ms_csr_sw_trig_wr_sync1       : std_logic      ;
signal fmc_adc_100ms_csr_sw_trig_wr_sync2       : std_logic      ;
signal fmc_adc_100ms_csr_shots_nb_int           : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_fs_freq_int            : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_fs_freq_lwb            : std_logic      ;
signal fmc_adc_100ms_csr_fs_freq_lwb_delay      : std_logic      ;
signal fmc_adc_100ms_csr_fs_freq_lwb_in_progress : std_logic      ;
signal fmc_adc_100ms_csr_fs_freq_lwb_s0         : std_logic      ;
signal fmc_adc_100ms_csr_fs_freq_lwb_s1         : std_logic      ;
signal fmc_adc_100ms_csr_fs_freq_lwb_s2         : std_logic      ;
signal fmc_adc_100ms_csr_sr_undersample_int     : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_sr_undersample_swb     : std_logic      ;
signal fmc_adc_100ms_csr_sr_undersample_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_sr_undersample_swb_s0  : std_logic      ;
signal fmc_adc_100ms_csr_sr_undersample_swb_s1  : std_logic      ;
signal fmc_adc_100ms_csr_sr_undersample_swb_s2  : std_logic      ;
signal fmc_adc_100ms_csr_pre_samples_int        : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_post_samples_int       : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_ch1_ctl_ssr_int        : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch1_sta_val_int        : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_sta_val_lwb        : std_logic      ;
signal fmc_adc_100ms_csr_ch1_sta_val_lwb_delay  : std_logic      ;
signal fmc_adc_100ms_csr_ch1_sta_val_lwb_in_progress : std_logic      ;
signal fmc_adc_100ms_csr_ch1_sta_val_lwb_s0     : std_logic      ;
signal fmc_adc_100ms_csr_ch1_sta_val_lwb_s1     : std_logic      ;
signal fmc_adc_100ms_csr_ch1_sta_val_lwb_s2     : std_logic      ;
signal fmc_adc_100ms_csr_ch1_gain_val_int       : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_offset_val_int     : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_sat_val_int        : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_thres_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s0 : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1 : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s2 : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0 : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 : std_logic      ;
signal fmc_adc_100ms_csr_ch1_trig_dly_int       : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_ch2_ctl_ssr_int        : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch2_sta_val_int        : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_sta_val_lwb        : std_logic      ;
signal fmc_adc_100ms_csr_ch2_sta_val_lwb_delay  : std_logic      ;
signal fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress : std_logic      ;
signal fmc_adc_100ms_csr_ch2_sta_val_lwb_s0     : std_logic      ;
signal fmc_adc_100ms_csr_ch2_sta_val_lwb_s1     : std_logic      ;
signal fmc_adc_100ms_csr_ch2_sta_val_lwb_s2     : std_logic      ;
signal fmc_adc_100ms_csr_ch2_gain_val_int       : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_offset_val_int     : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_sat_val_int        : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_thres_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s0 : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1 : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s2 : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0 : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 : std_logic      ;
signal fmc_adc_100ms_csr_ch2_trig_dly_int       : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_ch3_ctl_ssr_int        : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch3_sta_val_int        : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_sta_val_lwb        : std_logic      ;
signal fmc_adc_100ms_csr_ch3_sta_val_lwb_delay  : std_logic      ;
signal fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress : std_logic      ;
signal fmc_adc_100ms_csr_ch3_sta_val_lwb_s0     : std_logic      ;
signal fmc_adc_100ms_csr_ch3_sta_val_lwb_s1     : std_logic      ;
signal fmc_adc_100ms_csr_ch3_sta_val_lwb_s2     : std_logic      ;
signal fmc_adc_100ms_csr_ch3_gain_val_int       : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_offset_val_int     : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_sat_val_int        : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_thres_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s0 : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1 : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s2 : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0 : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 : std_logic      ;
signal fmc_adc_100ms_csr_ch3_trig_dly_int       : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_ch4_ctl_ssr_int        : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch4_sta_val_int        : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_sta_val_lwb        : std_logic      ;
signal fmc_adc_100ms_csr_ch4_sta_val_lwb_delay  : std_logic      ;
signal fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress : std_logic      ;
signal fmc_adc_100ms_csr_ch4_sta_val_lwb_s0     : std_logic      ;
signal fmc_adc_100ms_csr_ch4_sta_val_lwb_s1     : std_logic      ;
signal fmc_adc_100ms_csr_ch4_sta_val_lwb_s2     : std_logic      ;
signal fmc_adc_100ms_csr_ch4_gain_val_int       : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_offset_val_int     : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_sat_val_int        : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_thres_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s0 : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1 : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s2 : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0 : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 : std_logic      ;
signal fmc_adc_100ms_csr_ch4_trig_dly_int       : std_logic_vector(31 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(7 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments
  wrdata_reg <= wb_dat_i;
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      regs_o.ctl_fsm_cmd_wr_o <= '0';
      fmc_adc_100ms_csr_ctl_fmc_clk_oe_int <= '0';
      fmc_adc_100ms_csr_ctl_offset_dac_clr_n_int <= '0';
      fmc_adc_100ms_csr_ctl_man_bitslip_int <= '0';
      fmc_adc_100ms_csr_ctl_man_bitslip_int_delay <= '0';
      fmc_adc_100ms_csr_ctl_test_data_en_int <= '0';
      fmc_adc_100ms_csr_ctl_trig_led_int <= '0';
      fmc_adc_100ms_csr_ctl_acq_led_int <= '0';
      fmc_adc_100ms_csr_ctl_clear_trig_stat_int <= '0';
      fmc_adc_100ms_csr_trig_en_ext_int <= '0';
      fmc_adc_100ms_csr_trig_en_sw_int <= '0';
      fmc_adc_100ms_csr_trig_en_time_int <= '0';
      fmc_adc_100ms_csr_trig_en_alt_time_int <= '0';
      fmc_adc_100ms_csr_trig_en_ch1_int <= '0';
      fmc_adc_100ms_csr_trig_en_ch2_int <= '0';
      fmc_adc_100ms_csr_trig_en_ch3_int <= '0';
      fmc_adc_100ms_csr_trig_en_ch4_int <= '0';
      fmc_adc_100ms_csr_trig_en_fwd_ext_int <= '0';
      fmc_adc_100ms_csr_trig_en_fwd_ch1_int <= '0';
      fmc_adc_100ms_csr_trig_en_fwd_ch2_int <= '0';
      fmc_adc_100ms_csr_trig_en_fwd_ch3_int <= '0';
      fmc_adc_100ms_csr_trig_en_fwd_ch4_int <= '0';
      fmc_adc_100ms_csr_trig_pol_ext_int <= '0';
      fmc_adc_100ms_csr_trig_pol_ch1_int <= '0';
      fmc_adc_100ms_csr_trig_pol_ch2_int <= '0';
      fmc_adc_100ms_csr_trig_pol_ch3_int <= '0';
      fmc_adc_100ms_csr_trig_pol_ch4_int <= '0';
      fmc_adc_100ms_csr_ext_trig_dly_int <= "00000000000000000000000000000000";
      fmc_adc_100ms_csr_sw_trig_wr_int <= '0';
      fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '0';
      fmc_adc_100ms_csr_shots_nb_int <= "0000000000000000";
      fmc_adc_100ms_csr_fs_freq_lwb <= '0';
      fmc_adc_100ms_csr_fs_freq_lwb_delay <= '0';
      fmc_adc_100ms_csr_fs_freq_lwb_in_progress <= '0';
      fmc_adc_100ms_csr_sr_undersample_int <= "00000000000000000000000000000000";
      fmc_adc_100ms_csr_sr_undersample_swb <= '0';
      fmc_adc_100ms_csr_sr_undersample_swb_delay <= '0';
      fmc_adc_100ms_csr_pre_samples_int <= "00000000000000000000000000000000";
      fmc_adc_100ms_csr_post_samples_int <= "00000000000000000000000000000000";
      fmc_adc_100ms_csr_ch1_ctl_ssr_int <= "0000000";
      fmc_adc_100ms_csr_ch1_sta_val_lwb <= '0';
      fmc_adc_100ms_csr_ch1_sta_val_lwb_delay <= '0';
      fmc_adc_100ms_csr_ch1_sta_val_lwb_in_progress <= '0';
      fmc_adc_100ms_csr_ch1_gain_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch1_offset_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch1_sat_val_int <= "000000000000000";
      fmc_adc_100ms_csr_ch1_trig_thres_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch1_trig_thres_val_swb <= '0';
      fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay <= '0';
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb <= '0';
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay <= '0';
      fmc_adc_100ms_csr_ch1_trig_dly_int <= "00000000000000000000000000000000";
      fmc_adc_100ms_csr_ch2_ctl_ssr_int <= "0000000";
      fmc_adc_100ms_csr_ch2_sta_val_lwb <= '0';
      fmc_adc_100ms_csr_ch2_sta_val_lwb_delay <= '0';
      fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress <= '0';
      fmc_adc_100ms_csr_ch2_gain_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch2_offset_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch2_sat_val_int <= "000000000000000";
      fmc_adc_100ms_csr_ch2_trig_thres_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch2_trig_thres_val_swb <= '0';
      fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay <= '0';
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb <= '0';
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay <= '0';
      fmc_adc_100ms_csr_ch2_trig_dly_int <= "00000000000000000000000000000000";
      fmc_adc_100ms_csr_ch3_ctl_ssr_int <= "0000000";
      fmc_adc_100ms_csr_ch3_sta_val_lwb <= '0';
      fmc_adc_100ms_csr_ch3_sta_val_lwb_delay <= '0';
      fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress <= '0';
      fmc_adc_100ms_csr_ch3_gain_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch3_offset_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch3_sat_val_int <= "000000000000000";
      fmc_adc_100ms_csr_ch3_trig_thres_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch3_trig_thres_val_swb <= '0';
      fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay <= '0';
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb <= '0';
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay <= '0';
      fmc_adc_100ms_csr_ch3_trig_dly_int <= "00000000000000000000000000000000";
      fmc_adc_100ms_csr_ch4_ctl_ssr_int <= "0000000";
      fmc_adc_100ms_csr_ch4_sta_val_lwb <= '0';
      fmc_adc_100ms_csr_ch4_sta_val_lwb_delay <= '0';
      fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress <= '0';
      fmc_adc_100ms_csr_ch4_gain_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch4_offset_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch4_sat_val_int <= "000000000000000";
      fmc_adc_100ms_csr_ch4_trig_thres_val_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch4_trig_thres_val_swb <= '0';
      fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay <= '0';
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_int <= "0000000000000000";
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb <= '0';
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay <= '0';
      fmc_adc_100ms_csr_ch4_trig_dly_int <= "00000000000000000000000000000000";
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          regs_o.ctl_fsm_cmd_wr_o <= '0';
          fmc_adc_100ms_csr_ctl_clear_trig_stat_int <= '0';
          ack_in_progress <= '0';
        else
          regs_o.ctl_fsm_cmd_wr_o <= '0';
          fmc_adc_100ms_csr_ctl_man_bitslip_int <= fmc_adc_100ms_csr_ctl_man_bitslip_int_delay;
          fmc_adc_100ms_csr_ctl_man_bitslip_int_delay <= '0';
          fmc_adc_100ms_csr_sw_trig_wr_int <= fmc_adc_100ms_csr_sw_trig_wr_int_delay;
          fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '0';
          fmc_adc_100ms_csr_fs_freq_lwb <= fmc_adc_100ms_csr_fs_freq_lwb_delay;
          fmc_adc_100ms_csr_fs_freq_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_fs_freq_lwb_in_progress = '1')) then
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_fs_freq_int;
            fmc_adc_100ms_csr_fs_freq_lwb_in_progress <= '0';
          end if;
          fmc_adc_100ms_csr_sr_undersample_swb <= fmc_adc_100ms_csr_sr_undersample_swb_delay;
          fmc_adc_100ms_csr_sr_undersample_swb_delay <= '0';
          fmc_adc_100ms_csr_ch1_sta_val_lwb <= fmc_adc_100ms_csr_ch1_sta_val_lwb_delay;
          fmc_adc_100ms_csr_ch1_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch1_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch1_sta_val_int;
            fmc_adc_100ms_csr_ch1_sta_val_lwb_in_progress <= '0';
          end if;
          fmc_adc_100ms_csr_ch1_trig_thres_val_swb <= fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay;
          fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay <= '0';
          fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay;
          fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay <= '0';
          fmc_adc_100ms_csr_ch2_sta_val_lwb <= fmc_adc_100ms_csr_ch2_sta_val_lwb_delay;
          fmc_adc_100ms_csr_ch2_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch2_sta_val_int;
            fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress <= '0';
          end if;
          fmc_adc_100ms_csr_ch2_trig_thres_val_swb <= fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay;
          fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay <= '0';
          fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay;
          fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay <= '0';
          fmc_adc_100ms_csr_ch3_sta_val_lwb <= fmc_adc_100ms_csr_ch3_sta_val_lwb_delay;
          fmc_adc_100ms_csr_ch3_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch3_sta_val_int;
            fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress <= '0';
          end if;
          fmc_adc_100ms_csr_ch3_trig_thres_val_swb <= fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay;
          fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay <= '0';
          fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay;
          fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay <= '0';
          fmc_adc_100ms_csr_ch4_sta_val_lwb <= fmc_adc_100ms_csr_ch4_sta_val_lwb_delay;
          fmc_adc_100ms_csr_ch4_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch4_sta_val_int;
            fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress <= '0';
          end if;
          fmc_adc_100ms_csr_ch4_trig_thres_val_swb <= fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay;
          fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay <= '0';
          fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay;
          fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(7 downto 0) is
          when "00000000" => 
            if (wb_we_i = '1') then
              regs_o.ctl_fsm_cmd_wr_o <= '1';
              fmc_adc_100ms_csr_ctl_fmc_clk_oe_int <= wrdata_reg(2);
              fmc_adc_100ms_csr_ctl_offset_dac_clr_n_int <= wrdata_reg(3);
              fmc_adc_100ms_csr_ctl_man_bitslip_int <= wrdata_reg(4);
              fmc_adc_100ms_csr_ctl_man_bitslip_int_delay <= wrdata_reg(4);
              fmc_adc_100ms_csr_ctl_test_data_en_int <= wrdata_reg(5);
              fmc_adc_100ms_csr_ctl_trig_led_int <= wrdata_reg(6);
              fmc_adc_100ms_csr_ctl_acq_led_int <= wrdata_reg(7);
              fmc_adc_100ms_csr_ctl_clear_trig_stat_int <= wrdata_reg(8);
            end if;
            rddata_reg(2) <= fmc_adc_100ms_csr_ctl_fmc_clk_oe_int;
            rddata_reg(3) <= fmc_adc_100ms_csr_ctl_offset_dac_clr_n_int;
            rddata_reg(4) <= '0';
            rddata_reg(5) <= fmc_adc_100ms_csr_ctl_test_data_en_int;
            rddata_reg(6) <= fmc_adc_100ms_csr_ctl_trig_led_int;
            rddata_reg(7) <= fmc_adc_100ms_csr_ctl_acq_led_int;
            rddata_reg(8) <= '0';
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "00000001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(2 downto 0) <= regs_i.sta_fsm_i;
            rddata_reg(3) <= regs_i.sta_serdes_pll_i;
            rddata_reg(4) <= regs_i.sta_serdes_synced_i;
            rddata_reg(5) <= regs_i.sta_acq_cfg_i;
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= regs_i.trig_stat_ext_i;
            rddata_reg(1) <= regs_i.trig_stat_sw_i;
            rddata_reg(4) <= regs_i.trig_stat_time_i;
            rddata_reg(8) <= regs_i.trig_stat_ch1_i;
            rddata_reg(9) <= regs_i.trig_stat_ch2_i;
            rddata_reg(10) <= regs_i.trig_stat_ch3_i;
            rddata_reg(11) <= regs_i.trig_stat_ch4_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000011" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_trig_en_ext_int <= wrdata_reg(0);
              fmc_adc_100ms_csr_trig_en_sw_int <= wrdata_reg(1);
              fmc_adc_100ms_csr_trig_en_time_int <= wrdata_reg(4);
              fmc_adc_100ms_csr_trig_en_alt_time_int <= wrdata_reg(5);
              fmc_adc_100ms_csr_trig_en_ch1_int <= wrdata_reg(8);
              fmc_adc_100ms_csr_trig_en_ch2_int <= wrdata_reg(9);
              fmc_adc_100ms_csr_trig_en_ch3_int <= wrdata_reg(10);
              fmc_adc_100ms_csr_trig_en_ch4_int <= wrdata_reg(11);
              fmc_adc_100ms_csr_trig_en_fwd_ext_int <= wrdata_reg(16);
              fmc_adc_100ms_csr_trig_en_fwd_ch1_int <= wrdata_reg(24);
              fmc_adc_100ms_csr_trig_en_fwd_ch2_int <= wrdata_reg(25);
              fmc_adc_100ms_csr_trig_en_fwd_ch3_int <= wrdata_reg(26);
              fmc_adc_100ms_csr_trig_en_fwd_ch4_int <= wrdata_reg(27);
            end if;
            rddata_reg(0) <= fmc_adc_100ms_csr_trig_en_ext_int;
            rddata_reg(1) <= fmc_adc_100ms_csr_trig_en_sw_int;
            rddata_reg(4) <= fmc_adc_100ms_csr_trig_en_time_int;
            rddata_reg(5) <= fmc_adc_100ms_csr_trig_en_alt_time_int;
            rddata_reg(8) <= fmc_adc_100ms_csr_trig_en_ch1_int;
            rddata_reg(9) <= fmc_adc_100ms_csr_trig_en_ch2_int;
            rddata_reg(10) <= fmc_adc_100ms_csr_trig_en_ch3_int;
            rddata_reg(11) <= fmc_adc_100ms_csr_trig_en_ch4_int;
            rddata_reg(16) <= fmc_adc_100ms_csr_trig_en_fwd_ext_int;
            rddata_reg(24) <= fmc_adc_100ms_csr_trig_en_fwd_ch1_int;
            rddata_reg(25) <= fmc_adc_100ms_csr_trig_en_fwd_ch2_int;
            rddata_reg(26) <= fmc_adc_100ms_csr_trig_en_fwd_ch3_int;
            rddata_reg(27) <= fmc_adc_100ms_csr_trig_en_fwd_ch4_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "00000100" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_trig_pol_ext_int <= wrdata_reg(0);
              fmc_adc_100ms_csr_trig_pol_ch1_int <= wrdata_reg(8);
              fmc_adc_100ms_csr_trig_pol_ch2_int <= wrdata_reg(9);
              fmc_adc_100ms_csr_trig_pol_ch3_int <= wrdata_reg(10);
              fmc_adc_100ms_csr_trig_pol_ch4_int <= wrdata_reg(11);
            end if;
            rddata_reg(0) <= fmc_adc_100ms_csr_trig_pol_ext_int;
            rddata_reg(8) <= fmc_adc_100ms_csr_trig_pol_ch1_int;
            rddata_reg(9) <= fmc_adc_100ms_csr_trig_pol_ch2_int;
            rddata_reg(10) <= fmc_adc_100ms_csr_trig_pol_ch3_int;
            rddata_reg(11) <= fmc_adc_100ms_csr_trig_pol_ch4_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "00000101" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ext_trig_dly_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ext_trig_dly_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000110" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_sw_trig_wr_int <= '1';
              fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "00000111" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_shots_nb_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_shots_nb_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.multi_depth_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(15 downto 0) <= regs_i.shots_cnt_val_i;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.trig_pos_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001011" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc_adc_100ms_csr_fs_freq_lwb <= '1';
              fmc_adc_100ms_csr_fs_freq_lwb_delay <= '1';
              fmc_adc_100ms_csr_fs_freq_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "00001100" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_sr_undersample_int <= wrdata_reg(31 downto 0);
              fmc_adc_100ms_csr_sr_undersample_swb <= '1';
              fmc_adc_100ms_csr_sr_undersample_swb_delay <= '1';
            end if;
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_sr_undersample_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "00001101" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_pre_samples_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_pre_samples_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001110" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_post_samples_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_post_samples_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.samples_cnt_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100000" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch1_ctl_ssr_int <= wrdata_reg(6 downto 0);
            end if;
            rddata_reg(6 downto 0) <= fmc_adc_100ms_csr_ch1_ctl_ssr_int;
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc_adc_100ms_csr_ch1_sta_val_lwb <= '1';
              fmc_adc_100ms_csr_ch1_sta_val_lwb_delay <= '1';
              fmc_adc_100ms_csr_ch1_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "00100010" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch1_gain_val_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch1_gain_val_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100011" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch1_offset_val_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch1_offset_val_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100100" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch1_sat_val_int <= wrdata_reg(14 downto 0);
            end if;
            rddata_reg(14 downto 0) <= fmc_adc_100ms_csr_ch1_sat_val_int;
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100101" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch1_trig_thres_val_int <= wrdata_reg(15 downto 0);
              fmc_adc_100ms_csr_ch1_trig_thres_val_swb <= '1';
              fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay <= '1';
              fmc_adc_100ms_csr_ch1_trig_thres_hyst_int <= wrdata_reg(31 downto 16);
              fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb <= '1';
              fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay <= '1';
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch1_trig_thres_val_int;
            rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "00100110" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch1_trig_dly_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ch1_trig_dly_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000000" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch2_ctl_ssr_int <= wrdata_reg(6 downto 0);
            end if;
            rddata_reg(6 downto 0) <= fmc_adc_100ms_csr_ch2_ctl_ssr_int;
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc_adc_100ms_csr_ch2_sta_val_lwb <= '1';
              fmc_adc_100ms_csr_ch2_sta_val_lwb_delay <= '1';
              fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "01000010" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch2_gain_val_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch2_gain_val_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000011" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch2_offset_val_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch2_offset_val_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000100" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch2_sat_val_int <= wrdata_reg(14 downto 0);
            end if;
            rddata_reg(14 downto 0) <= fmc_adc_100ms_csr_ch2_sat_val_int;
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000101" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch2_trig_thres_val_int <= wrdata_reg(15 downto 0);
              fmc_adc_100ms_csr_ch2_trig_thres_val_swb <= '1';
              fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay <= '1';
              fmc_adc_100ms_csr_ch2_trig_thres_hyst_int <= wrdata_reg(31 downto 16);
              fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb <= '1';
              fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay <= '1';
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch2_trig_thres_val_int;
            rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "01000110" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch2_trig_dly_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ch2_trig_dly_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100000" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch3_ctl_ssr_int <= wrdata_reg(6 downto 0);
            end if;
            rddata_reg(6 downto 0) <= fmc_adc_100ms_csr_ch3_ctl_ssr_int;
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc_adc_100ms_csr_ch3_sta_val_lwb <= '1';
              fmc_adc_100ms_csr_ch3_sta_val_lwb_delay <= '1';
              fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "01100010" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch3_gain_val_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch3_gain_val_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100011" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch3_offset_val_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch3_offset_val_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100100" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch3_sat_val_int <= wrdata_reg(14 downto 0);
            end if;
            rddata_reg(14 downto 0) <= fmc_adc_100ms_csr_ch3_sat_val_int;
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100101" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch3_trig_thres_val_int <= wrdata_reg(15 downto 0);
              fmc_adc_100ms_csr_ch3_trig_thres_val_swb <= '1';
              fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay <= '1';
              fmc_adc_100ms_csr_ch3_trig_thres_hyst_int <= wrdata_reg(31 downto 16);
              fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb <= '1';
              fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay <= '1';
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch3_trig_thres_val_int;
            rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "01100110" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch3_trig_dly_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ch3_trig_dly_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000000" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch4_ctl_ssr_int <= wrdata_reg(6 downto 0);
            end if;
            rddata_reg(6 downto 0) <= fmc_adc_100ms_csr_ch4_ctl_ssr_int;
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc_adc_100ms_csr_ch4_sta_val_lwb <= '1';
              fmc_adc_100ms_csr_ch4_sta_val_lwb_delay <= '1';
              fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "10000010" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch4_gain_val_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch4_gain_val_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000011" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch4_offset_val_int <= wrdata_reg(15 downto 0);
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch4_offset_val_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000100" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch4_sat_val_int <= wrdata_reg(14 downto 0);
            end if;
            rddata_reg(14 downto 0) <= fmc_adc_100ms_csr_ch4_sat_val_int;
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000101" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch4_trig_thres_val_int <= wrdata_reg(15 downto 0);
              fmc_adc_100ms_csr_ch4_trig_thres_val_swb <= '1';
              fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay <= '1';
              fmc_adc_100ms_csr_ch4_trig_thres_hyst_int <= wrdata_reg(31 downto 16);
              fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb <= '1';
              fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay <= '1';
            end if;
            rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch4_trig_thres_val_int;
            rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "10000110" => 
            if (wb_we_i = '1') then
              fmc_adc_100ms_csr_ch4_trig_dly_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ch4_trig_dly_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- State machine commands (ignore on read)
-- pass-through field: State machine commands (ignore on read) in register: Control register
  regs_o.ctl_fsm_cmd_o <= wrdata_reg(1 downto 0);
-- FMC Si750 output enable
  regs_o.ctl_fmc_clk_oe_o <= fmc_adc_100ms_csr_ctl_fmc_clk_oe_int;
-- Offset DACs clear (active low)
  regs_o.ctl_offset_dac_clr_n_o <= fmc_adc_100ms_csr_ctl_offset_dac_clr_n_int;
-- Manual serdes bitslip (ignore on read)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ctl_man_bitslip_o <= '0';
      fmc_adc_100ms_csr_ctl_man_bitslip_sync0 <= '0';
      fmc_adc_100ms_csr_ctl_man_bitslip_sync1 <= '0';
      fmc_adc_100ms_csr_ctl_man_bitslip_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ctl_man_bitslip_sync0 <= fmc_adc_100ms_csr_ctl_man_bitslip_int;
      fmc_adc_100ms_csr_ctl_man_bitslip_sync1 <= fmc_adc_100ms_csr_ctl_man_bitslip_sync0;
      fmc_adc_100ms_csr_ctl_man_bitslip_sync2 <= fmc_adc_100ms_csr_ctl_man_bitslip_sync1;
      regs_o.ctl_man_bitslip_o <= fmc_adc_100ms_csr_ctl_man_bitslip_sync2 and (not fmc_adc_100ms_csr_ctl_man_bitslip_sync1);
    end if;
  end process;
  
  
-- Enable test data
  regs_o.ctl_test_data_en_o <= fmc_adc_100ms_csr_ctl_test_data_en_int;
-- Manual TRIG LED
  regs_o.ctl_trig_led_o <= fmc_adc_100ms_csr_ctl_trig_led_int;
-- Manual ACQ LED
  regs_o.ctl_acq_led_o <= fmc_adc_100ms_csr_ctl_acq_led_int;
-- Clear trigger status
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ctl_clear_trig_stat_dly0 <= '0';
      regs_o.ctl_clear_trig_stat_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc_adc_100ms_csr_ctl_clear_trig_stat_dly0 <= fmc_adc_100ms_csr_ctl_clear_trig_stat_int;
      regs_o.ctl_clear_trig_stat_o <= fmc_adc_100ms_csr_ctl_clear_trig_stat_int and (not fmc_adc_100ms_csr_ctl_clear_trig_stat_dly0);
    end if;
  end process;
  
  
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
-- Acquisition configuration status
-- External trigger input
-- Software trigger
-- Timetag trigger
-- Channel 1 internal threshold trigger
-- Channel 2 internal threshold trigger
-- Channel 3 internal threshold trigger
-- Channel 4 internal threshold trigger
-- External trigger input
-- synchronizer chain for field : External trigger input (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_en_ext_o <= '0';
      fmc_adc_100ms_csr_trig_en_ext_sync0 <= '0';
      fmc_adc_100ms_csr_trig_en_ext_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_en_ext_sync0 <= fmc_adc_100ms_csr_trig_en_ext_int;
      fmc_adc_100ms_csr_trig_en_ext_sync1 <= fmc_adc_100ms_csr_trig_en_ext_sync0;
      regs_o.trig_en_ext_o <= fmc_adc_100ms_csr_trig_en_ext_sync1;
    end if;
  end process;
  
  
-- Software trigger
-- synchronizer chain for field : Software trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_en_sw_o <= '0';
      fmc_adc_100ms_csr_trig_en_sw_sync0 <= '0';
      fmc_adc_100ms_csr_trig_en_sw_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_en_sw_sync0 <= fmc_adc_100ms_csr_trig_en_sw_int;
      fmc_adc_100ms_csr_trig_en_sw_sync1 <= fmc_adc_100ms_csr_trig_en_sw_sync0;
      regs_o.trig_en_sw_o <= fmc_adc_100ms_csr_trig_en_sw_sync1;
    end if;
  end process;
  
  
-- Timetag trigger
-- synchronizer chain for field : Timetag trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_en_time_o <= '0';
      fmc_adc_100ms_csr_trig_en_time_sync0 <= '0';
      fmc_adc_100ms_csr_trig_en_time_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_en_time_sync0 <= fmc_adc_100ms_csr_trig_en_time_int;
      fmc_adc_100ms_csr_trig_en_time_sync1 <= fmc_adc_100ms_csr_trig_en_time_sync0;
      regs_o.trig_en_time_o <= fmc_adc_100ms_csr_trig_en_time_sync1;
    end if;
  end process;
  
  
-- Alternate timetag trigger
-- synchronizer chain for field : Alternate timetag trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_en_alt_time_o <= '0';
      fmc_adc_100ms_csr_trig_en_alt_time_sync0 <= '0';
      fmc_adc_100ms_csr_trig_en_alt_time_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_en_alt_time_sync0 <= fmc_adc_100ms_csr_trig_en_alt_time_int;
      fmc_adc_100ms_csr_trig_en_alt_time_sync1 <= fmc_adc_100ms_csr_trig_en_alt_time_sync0;
      regs_o.trig_en_alt_time_o <= fmc_adc_100ms_csr_trig_en_alt_time_sync1;
    end if;
  end process;
  
  
-- Channel 1 internal threshold trigger
-- synchronizer chain for field : Channel 1 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_en_ch1_o <= '0';
      fmc_adc_100ms_csr_trig_en_ch1_sync0 <= '0';
      fmc_adc_100ms_csr_trig_en_ch1_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_en_ch1_sync0 <= fmc_adc_100ms_csr_trig_en_ch1_int;
      fmc_adc_100ms_csr_trig_en_ch1_sync1 <= fmc_adc_100ms_csr_trig_en_ch1_sync0;
      regs_o.trig_en_ch1_o <= fmc_adc_100ms_csr_trig_en_ch1_sync1;
    end if;
  end process;
  
  
-- Channel 2 internal threshold trigger
-- synchronizer chain for field : Channel 2 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_en_ch2_o <= '0';
      fmc_adc_100ms_csr_trig_en_ch2_sync0 <= '0';
      fmc_adc_100ms_csr_trig_en_ch2_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_en_ch2_sync0 <= fmc_adc_100ms_csr_trig_en_ch2_int;
      fmc_adc_100ms_csr_trig_en_ch2_sync1 <= fmc_adc_100ms_csr_trig_en_ch2_sync0;
      regs_o.trig_en_ch2_o <= fmc_adc_100ms_csr_trig_en_ch2_sync1;
    end if;
  end process;
  
  
-- Channel 3 internal threshold trigger
-- synchronizer chain for field : Channel 3 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_en_ch3_o <= '0';
      fmc_adc_100ms_csr_trig_en_ch3_sync0 <= '0';
      fmc_adc_100ms_csr_trig_en_ch3_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_en_ch3_sync0 <= fmc_adc_100ms_csr_trig_en_ch3_int;
      fmc_adc_100ms_csr_trig_en_ch3_sync1 <= fmc_adc_100ms_csr_trig_en_ch3_sync0;
      regs_o.trig_en_ch3_o <= fmc_adc_100ms_csr_trig_en_ch3_sync1;
    end if;
  end process;
  
  
-- Channel 4 internal threshold trigger
-- synchronizer chain for field : Channel 4 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_en_ch4_o <= '0';
      fmc_adc_100ms_csr_trig_en_ch4_sync0 <= '0';
      fmc_adc_100ms_csr_trig_en_ch4_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_en_ch4_sync0 <= fmc_adc_100ms_csr_trig_en_ch4_int;
      fmc_adc_100ms_csr_trig_en_ch4_sync1 <= fmc_adc_100ms_csr_trig_en_ch4_sync0;
      regs_o.trig_en_ch4_o <= fmc_adc_100ms_csr_trig_en_ch4_sync1;
    end if;
  end process;
  
  
-- Forward external trigger to trigger out
  regs_o.trig_en_fwd_ext_o <= fmc_adc_100ms_csr_trig_en_fwd_ext_int;
-- Forward channel 1 internal threshold trigger to trigger out
  regs_o.trig_en_fwd_ch1_o <= fmc_adc_100ms_csr_trig_en_fwd_ch1_int;
-- Forward channel 2 internal threshold trigger to trigger out
  regs_o.trig_en_fwd_ch2_o <= fmc_adc_100ms_csr_trig_en_fwd_ch2_int;
-- Forward channel 3 internal threshold trigger to trigger out
  regs_o.trig_en_fwd_ch3_o <= fmc_adc_100ms_csr_trig_en_fwd_ch3_int;
-- Forward channel 4 internal threshold trigger to trigger out
  regs_o.trig_en_fwd_ch4_o <= fmc_adc_100ms_csr_trig_en_fwd_ch4_int;
-- External trigger input
-- synchronizer chain for field : External trigger input (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_pol_ext_o <= '0';
      fmc_adc_100ms_csr_trig_pol_ext_sync0 <= '0';
      fmc_adc_100ms_csr_trig_pol_ext_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_pol_ext_sync0 <= fmc_adc_100ms_csr_trig_pol_ext_int;
      fmc_adc_100ms_csr_trig_pol_ext_sync1 <= fmc_adc_100ms_csr_trig_pol_ext_sync0;
      regs_o.trig_pol_ext_o <= fmc_adc_100ms_csr_trig_pol_ext_sync1;
    end if;
  end process;
  
  
-- Channel 1 internal threshold trigger
-- synchronizer chain for field : Channel 1 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_pol_ch1_o <= '0';
      fmc_adc_100ms_csr_trig_pol_ch1_sync0 <= '0';
      fmc_adc_100ms_csr_trig_pol_ch1_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_pol_ch1_sync0 <= fmc_adc_100ms_csr_trig_pol_ch1_int;
      fmc_adc_100ms_csr_trig_pol_ch1_sync1 <= fmc_adc_100ms_csr_trig_pol_ch1_sync0;
      regs_o.trig_pol_ch1_o <= fmc_adc_100ms_csr_trig_pol_ch1_sync1;
    end if;
  end process;
  
  
-- Channel 2 internal threshold trigger
-- synchronizer chain for field : Channel 2 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_pol_ch2_o <= '0';
      fmc_adc_100ms_csr_trig_pol_ch2_sync0 <= '0';
      fmc_adc_100ms_csr_trig_pol_ch2_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_pol_ch2_sync0 <= fmc_adc_100ms_csr_trig_pol_ch2_int;
      fmc_adc_100ms_csr_trig_pol_ch2_sync1 <= fmc_adc_100ms_csr_trig_pol_ch2_sync0;
      regs_o.trig_pol_ch2_o <= fmc_adc_100ms_csr_trig_pol_ch2_sync1;
    end if;
  end process;
  
  
-- Channel 3 internal threshold trigger
-- synchronizer chain for field : Channel 3 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_pol_ch3_o <= '0';
      fmc_adc_100ms_csr_trig_pol_ch3_sync0 <= '0';
      fmc_adc_100ms_csr_trig_pol_ch3_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_pol_ch3_sync0 <= fmc_adc_100ms_csr_trig_pol_ch3_int;
      fmc_adc_100ms_csr_trig_pol_ch3_sync1 <= fmc_adc_100ms_csr_trig_pol_ch3_sync0;
      regs_o.trig_pol_ch3_o <= fmc_adc_100ms_csr_trig_pol_ch3_sync1;
    end if;
  end process;
  
  
-- Channel 4 internal threshold trigger
-- synchronizer chain for field : Channel 4 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_pol_ch4_o <= '0';
      fmc_adc_100ms_csr_trig_pol_ch4_sync0 <= '0';
      fmc_adc_100ms_csr_trig_pol_ch4_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_trig_pol_ch4_sync0 <= fmc_adc_100ms_csr_trig_pol_ch4_int;
      fmc_adc_100ms_csr_trig_pol_ch4_sync1 <= fmc_adc_100ms_csr_trig_pol_ch4_sync0;
      regs_o.trig_pol_ch4_o <= fmc_adc_100ms_csr_trig_pol_ch4_sync1;
    end if;
  end process;
  
  
-- External trigger delay value
  regs_o.ext_trig_dly_o <= fmc_adc_100ms_csr_ext_trig_dly_int;
-- Software trigger (ignore on read)
-- pass-through field: Software trigger (ignore on read) in register: Software trigger
  regs_o.sw_trig_o <= wrdata_reg(31 downto 0);
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_sw_trig_wr_sync0 <= '0';
      fmc_adc_100ms_csr_sw_trig_wr_sync1 <= '0';
      fmc_adc_100ms_csr_sw_trig_wr_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_sw_trig_wr_sync0 <= fmc_adc_100ms_csr_sw_trig_wr_int;
      fmc_adc_100ms_csr_sw_trig_wr_sync1 <= fmc_adc_100ms_csr_sw_trig_wr_sync0;
      fmc_adc_100ms_csr_sw_trig_wr_sync2 <= fmc_adc_100ms_csr_sw_trig_wr_sync1;
      regs_o.sw_trig_wr_o <= fmc_adc_100ms_csr_sw_trig_wr_sync1 and (not fmc_adc_100ms_csr_sw_trig_wr_sync2);
    end if;
  end process;
  
  
-- Number of shots
  regs_o.shots_nb_o <= fmc_adc_100ms_csr_shots_nb_int;
-- Multi-shot sample depth
-- Remaining shots counter
-- Trigger address
-- Sampling clock frequency
-- asynchronous std_logic_vector register : Sampling clock frequency (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_fs_freq_lwb_s0 <= '0';
      fmc_adc_100ms_csr_fs_freq_lwb_s1 <= '0';
      fmc_adc_100ms_csr_fs_freq_lwb_s2 <= '0';
      fmc_adc_100ms_csr_fs_freq_int <= "00000000000000000000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_fs_freq_lwb_s0 <= fmc_adc_100ms_csr_fs_freq_lwb;
      fmc_adc_100ms_csr_fs_freq_lwb_s1 <= fmc_adc_100ms_csr_fs_freq_lwb_s0;
      fmc_adc_100ms_csr_fs_freq_lwb_s2 <= fmc_adc_100ms_csr_fs_freq_lwb_s1;
      if ((fmc_adc_100ms_csr_fs_freq_lwb_s1 = '1') and (fmc_adc_100ms_csr_fs_freq_lwb_s2 = '0')) then
        fmc_adc_100ms_csr_fs_freq_int <= regs_i.fs_freq_i;
      end if;
    end if;
  end process;
  
  
-- Undersampling ratio
-- asynchronous std_logic_vector register : Undersampling ratio (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_sr_undersample_swb_s0 <= '0';
      fmc_adc_100ms_csr_sr_undersample_swb_s1 <= '0';
      fmc_adc_100ms_csr_sr_undersample_swb_s2 <= '0';
      regs_o.sr_undersample_o <= "00000000000000000000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_sr_undersample_swb_s0 <= fmc_adc_100ms_csr_sr_undersample_swb;
      fmc_adc_100ms_csr_sr_undersample_swb_s1 <= fmc_adc_100ms_csr_sr_undersample_swb_s0;
      fmc_adc_100ms_csr_sr_undersample_swb_s2 <= fmc_adc_100ms_csr_sr_undersample_swb_s1;
      if ((fmc_adc_100ms_csr_sr_undersample_swb_s2 = '0') and (fmc_adc_100ms_csr_sr_undersample_swb_s1 = '1')) then
        regs_o.sr_undersample_o <= fmc_adc_100ms_csr_sr_undersample_int;
      end if;
    end if;
  end process;
  
  
-- Pre-trigger samples
  regs_o.pre_samples_o <= fmc_adc_100ms_csr_pre_samples_int;
-- Post-trigger samples
  regs_o.post_samples_o <= fmc_adc_100ms_csr_post_samples_int;
-- Samples counter
-- Solid state relays control for channel 1
  regs_o.ch1_ctl_ssr_o <= fmc_adc_100ms_csr_ch1_ctl_ssr_int;
-- Channel 1 current ADC value
-- asynchronous std_logic_vector register : Channel 1 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch1_sta_val_lwb_s0 <= '0';
      fmc_adc_100ms_csr_ch1_sta_val_lwb_s1 <= '0';
      fmc_adc_100ms_csr_ch1_sta_val_lwb_s2 <= '0';
      fmc_adc_100ms_csr_ch1_sta_val_int <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch1_sta_val_lwb_s0 <= fmc_adc_100ms_csr_ch1_sta_val_lwb;
      fmc_adc_100ms_csr_ch1_sta_val_lwb_s1 <= fmc_adc_100ms_csr_ch1_sta_val_lwb_s0;
      fmc_adc_100ms_csr_ch1_sta_val_lwb_s2 <= fmc_adc_100ms_csr_ch1_sta_val_lwb_s1;
      if ((fmc_adc_100ms_csr_ch1_sta_val_lwb_s1 = '1') and (fmc_adc_100ms_csr_ch1_sta_val_lwb_s2 = '0')) then
        fmc_adc_100ms_csr_ch1_sta_val_int <= regs_i.ch1_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Gain calibration for channel 1
  regs_o.ch1_gain_val_o <= fmc_adc_100ms_csr_ch1_gain_val_int;
-- Offset calibration for channel 1
  regs_o.ch1_offset_val_o <= fmc_adc_100ms_csr_ch1_offset_val_int;
-- Saturation value for channel 1
  regs_o.ch1_sat_val_o <= fmc_adc_100ms_csr_ch1_sat_val_int;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s0 <= '0';
      fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1 <= '0';
      fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s2 <= '0';
      regs_o.ch1_trig_thres_val_o <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s0 <= fmc_adc_100ms_csr_ch1_trig_thres_val_swb;
      fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1 <= fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s0;
      fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s2 <= fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1;
      if ((fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s2 = '0') and (fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1 = '1')) then
        regs_o.ch1_trig_thres_val_o <= fmc_adc_100ms_csr_ch1_trig_thres_val_int;
      end if;
    end if;
  end process;
  
  
-- Internal trigger threshold hysteresis
-- asynchronous std_logic_vector register : Internal trigger threshold hysteresis (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0 <= '0';
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 <= '0';
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 <= '0';
      regs_o.ch1_trig_thres_hyst_o <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0 <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb;
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0;
      fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1;
      if ((fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 = '0') and (fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 = '1')) then
        regs_o.ch1_trig_thres_hyst_o <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_int;
      end if;
    end if;
  end process;
  
  
-- Channel 1 trigger delay value
  regs_o.ch1_trig_dly_o <= fmc_adc_100ms_csr_ch1_trig_dly_int;
-- Solid state relays control for channel 2
  regs_o.ch2_ctl_ssr_o <= fmc_adc_100ms_csr_ch2_ctl_ssr_int;
-- Channel 2 current ACD value
-- asynchronous std_logic_vector register : Channel 2 current ACD value (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch2_sta_val_lwb_s0 <= '0';
      fmc_adc_100ms_csr_ch2_sta_val_lwb_s1 <= '0';
      fmc_adc_100ms_csr_ch2_sta_val_lwb_s2 <= '0';
      fmc_adc_100ms_csr_ch2_sta_val_int <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch2_sta_val_lwb_s0 <= fmc_adc_100ms_csr_ch2_sta_val_lwb;
      fmc_adc_100ms_csr_ch2_sta_val_lwb_s1 <= fmc_adc_100ms_csr_ch2_sta_val_lwb_s0;
      fmc_adc_100ms_csr_ch2_sta_val_lwb_s2 <= fmc_adc_100ms_csr_ch2_sta_val_lwb_s1;
      if ((fmc_adc_100ms_csr_ch2_sta_val_lwb_s1 = '1') and (fmc_adc_100ms_csr_ch2_sta_val_lwb_s2 = '0')) then
        fmc_adc_100ms_csr_ch2_sta_val_int <= regs_i.ch2_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Gain calibration for channel 2
  regs_o.ch2_gain_val_o <= fmc_adc_100ms_csr_ch2_gain_val_int;
-- Offset calibration for channel 2
  regs_o.ch2_offset_val_o <= fmc_adc_100ms_csr_ch2_offset_val_int;
-- Saturation value for channel 2
  regs_o.ch2_sat_val_o <= fmc_adc_100ms_csr_ch2_sat_val_int;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s0 <= '0';
      fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1 <= '0';
      fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s2 <= '0';
      regs_o.ch2_trig_thres_val_o <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s0 <= fmc_adc_100ms_csr_ch2_trig_thres_val_swb;
      fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1 <= fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s0;
      fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s2 <= fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1;
      if ((fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s2 = '0') and (fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1 = '1')) then
        regs_o.ch2_trig_thres_val_o <= fmc_adc_100ms_csr_ch2_trig_thres_val_int;
      end if;
    end if;
  end process;
  
  
-- Internal trigger threshold hysteresis
-- asynchronous std_logic_vector register : Internal trigger threshold hysteresis (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0 <= '0';
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 <= '0';
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 <= '0';
      regs_o.ch2_trig_thres_hyst_o <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0 <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb;
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0;
      fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1;
      if ((fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 = '0') and (fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 = '1')) then
        regs_o.ch2_trig_thres_hyst_o <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_int;
      end if;
    end if;
  end process;
  
  
-- Channel 2 trigger delay value
  regs_o.ch2_trig_dly_o <= fmc_adc_100ms_csr_ch2_trig_dly_int;
-- Solid state relays control for channel 3
  regs_o.ch3_ctl_ssr_o <= fmc_adc_100ms_csr_ch3_ctl_ssr_int;
-- Channel 3 current ADC value
-- asynchronous std_logic_vector register : Channel 3 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch3_sta_val_lwb_s0 <= '0';
      fmc_adc_100ms_csr_ch3_sta_val_lwb_s1 <= '0';
      fmc_adc_100ms_csr_ch3_sta_val_lwb_s2 <= '0';
      fmc_adc_100ms_csr_ch3_sta_val_int <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch3_sta_val_lwb_s0 <= fmc_adc_100ms_csr_ch3_sta_val_lwb;
      fmc_adc_100ms_csr_ch3_sta_val_lwb_s1 <= fmc_adc_100ms_csr_ch3_sta_val_lwb_s0;
      fmc_adc_100ms_csr_ch3_sta_val_lwb_s2 <= fmc_adc_100ms_csr_ch3_sta_val_lwb_s1;
      if ((fmc_adc_100ms_csr_ch3_sta_val_lwb_s1 = '1') and (fmc_adc_100ms_csr_ch3_sta_val_lwb_s2 = '0')) then
        fmc_adc_100ms_csr_ch3_sta_val_int <= regs_i.ch3_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Gain calibration for channel 3
  regs_o.ch3_gain_val_o <= fmc_adc_100ms_csr_ch3_gain_val_int;
-- Offset calibration for channel 3
  regs_o.ch3_offset_val_o <= fmc_adc_100ms_csr_ch3_offset_val_int;
-- Saturation value for channel 3
  regs_o.ch3_sat_val_o <= fmc_adc_100ms_csr_ch3_sat_val_int;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s0 <= '0';
      fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1 <= '0';
      fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s2 <= '0';
      regs_o.ch3_trig_thres_val_o <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s0 <= fmc_adc_100ms_csr_ch3_trig_thres_val_swb;
      fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1 <= fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s0;
      fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s2 <= fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1;
      if ((fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s2 = '0') and (fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1 = '1')) then
        regs_o.ch3_trig_thres_val_o <= fmc_adc_100ms_csr_ch3_trig_thres_val_int;
      end if;
    end if;
  end process;
  
  
-- Internal trigger threshold hysteresis
-- asynchronous std_logic_vector register : Internal trigger threshold hysteresis (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0 <= '0';
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 <= '0';
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 <= '0';
      regs_o.ch3_trig_thres_hyst_o <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0 <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb;
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0;
      fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1;
      if ((fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 = '0') and (fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 = '1')) then
        regs_o.ch3_trig_thres_hyst_o <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_int;
      end if;
    end if;
  end process;
  
  
-- Channel 3 trigger delay value
  regs_o.ch3_trig_dly_o <= fmc_adc_100ms_csr_ch3_trig_dly_int;
-- Solid state relays control for channel 4
  regs_o.ch4_ctl_ssr_o <= fmc_adc_100ms_csr_ch4_ctl_ssr_int;
-- Channel 4 current ADC value
-- asynchronous std_logic_vector register : Channel 4 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch4_sta_val_lwb_s0 <= '0';
      fmc_adc_100ms_csr_ch4_sta_val_lwb_s1 <= '0';
      fmc_adc_100ms_csr_ch4_sta_val_lwb_s2 <= '0';
      fmc_adc_100ms_csr_ch4_sta_val_int <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch4_sta_val_lwb_s0 <= fmc_adc_100ms_csr_ch4_sta_val_lwb;
      fmc_adc_100ms_csr_ch4_sta_val_lwb_s1 <= fmc_adc_100ms_csr_ch4_sta_val_lwb_s0;
      fmc_adc_100ms_csr_ch4_sta_val_lwb_s2 <= fmc_adc_100ms_csr_ch4_sta_val_lwb_s1;
      if ((fmc_adc_100ms_csr_ch4_sta_val_lwb_s1 = '1') and (fmc_adc_100ms_csr_ch4_sta_val_lwb_s2 = '0')) then
        fmc_adc_100ms_csr_ch4_sta_val_int <= regs_i.ch4_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Gain calibration for channel 4
  regs_o.ch4_gain_val_o <= fmc_adc_100ms_csr_ch4_gain_val_int;
-- Offset calibration for channel 4
  regs_o.ch4_offset_val_o <= fmc_adc_100ms_csr_ch4_offset_val_int;
-- Saturation value for channel 4
  regs_o.ch4_sat_val_o <= fmc_adc_100ms_csr_ch4_sat_val_int;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s0 <= '0';
      fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1 <= '0';
      fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s2 <= '0';
      regs_o.ch4_trig_thres_val_o <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s0 <= fmc_adc_100ms_csr_ch4_trig_thres_val_swb;
      fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1 <= fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s0;
      fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s2 <= fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1;
      if ((fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s2 = '0') and (fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1 = '1')) then
        regs_o.ch4_trig_thres_val_o <= fmc_adc_100ms_csr_ch4_trig_thres_val_int;
      end if;
    end if;
  end process;
  
  
-- Internal trigger threshold hysteresis
-- asynchronous std_logic_vector register : Internal trigger threshold hysteresis (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0 <= '0';
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 <= '0';
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 <= '0';
      regs_o.ch4_trig_thres_hyst_o <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0 <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb;
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0;
      fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1;
      if ((fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 = '0') and (fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 = '1')) then
        regs_o.ch4_trig_thres_hyst_o <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_int;
      end if;
    end if;
  end process;
  
  
-- Channel 4 trigger delay value
  regs_o.ch4_trig_dly_o <= fmc_adc_100ms_csr_ch4_trig_dly_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
  wb_err_o <= '0';
  wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
