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-- Title          : Wishbone slave core for SVEC carrier control and status registers
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-- File           : ../rtl/carrier_csr_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from carrier_csr.wb
-- Created        : Thu Jun 16 17:11:57 2016
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package carrier_csr_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_carrier_csr_in_registers is record
    carrier_pcb_rev_i                        : std_logic_vector(4 downto 0);
    carrier_reserved_i                       : std_logic_vector(10 downto 0);
    carrier_type_i                           : std_logic_vector(15 downto 0);
    stat_fmc0_pres_i                         : std_logic;
    stat_fmc1_pres_i                         : std_logic;
    stat_sys_pll_lck_i                       : std_logic;
    stat_ddr0_cal_done_i                     : std_logic;
    stat_ddr1_cal_done_i                     : std_logic;
    end record;
  
  constant c_carrier_csr_in_registers_init_value: t_carrier_csr_in_registers := (
    carrier_pcb_rev_i => (others => '0'),
    carrier_reserved_i => (others => '0'),
    carrier_type_i => (others => '0'),
    stat_fmc0_pres_i => '0',
    stat_fmc1_pres_i => '0',
    stat_sys_pll_lck_i => '0',
    stat_ddr0_cal_done_i => '0',
    stat_ddr1_cal_done_i => '0'
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_carrier_csr_out_registers is record
      ctrl_fp_leds_man_o                       : std_logic_vector(15 downto 0);
      ctrl_wrabbit_en_o                        : std_logic;
      rst_fmc0_o                               : std_logic;
      rst_fmc1_o                               : std_logic;
      end record;
    
    constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
      ctrl_fp_leds_man_o => (others => '0'),
      ctrl_wrabbit_en_o => '0',
      rst_fmc0_o => '0',
      rst_fmc1_o => '0'
      );
    function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body carrier_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers is
variable tmp: t_carrier_csr_in_registers;
begin
tmp.carrier_pcb_rev_i := f_x_to_zero(left.carrier_pcb_rev_i) or f_x_to_zero(right.carrier_pcb_rev_i);
tmp.carrier_reserved_i := f_x_to_zero(left.carrier_reserved_i) or f_x_to_zero(right.carrier_reserved_i);
tmp.carrier_type_i := f_x_to_zero(left.carrier_type_i) or f_x_to_zero(right.carrier_type_i);
tmp.stat_fmc0_pres_i := f_x_to_zero(left.stat_fmc0_pres_i) or f_x_to_zero(right.stat_fmc0_pres_i);
tmp.stat_fmc1_pres_i := f_x_to_zero(left.stat_fmc1_pres_i) or f_x_to_zero(right.stat_fmc1_pres_i);
tmp.stat_sys_pll_lck_i := f_x_to_zero(left.stat_sys_pll_lck_i) or f_x_to_zero(right.stat_sys_pll_lck_i);
tmp.stat_ddr0_cal_done_i := f_x_to_zero(left.stat_ddr0_cal_done_i) or f_x_to_zero(right.stat_ddr0_cal_done_i);
tmp.stat_ddr1_cal_done_i := f_x_to_zero(left.stat_ddr1_cal_done_i) or f_x_to_zero(right.stat_ddr1_cal_done_i);
return tmp;
end function;
end package body;
