# fmc_adc_100Ms_csr

### FMC ADC 100MS/s core registers

Wishbone slave for FMC ADC 100MS/s core

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control register
3.2. Status register
3.3. Trigger configuration
3.4. Trigger delay
3.5. Software trigger
3.6. Number of shots
3.7. Remaining shots counter
3.8. Trigger address register
3.9. Sampling clock frequency
3.10. Sample rate
3.11. Pre-trigger samples
3.12. Post-trigger samples
3.13. Samples counter
3.14. Channel 1 control register
3.15. Channel 1 status register
3.16. Channel 1 gain calibration register
3.17. Channel 1 offset calibration register
3.18. Channel 1 saturation register
3.19. Channel 2 control register
3.20. Channel 2 status register
3.21. Channel 2 gain calibration register
3.22. Channel 2 offset calibration register
3.23. Channel 2 saturation register
3.24. Channel 3 control register
3.25. Channel 3 status register
3.26. Channel 3 gain calibration register
3.27. Channel 3 offset calibration register
3.28. Channel 3 saturation register
3.29. Channel 4 control register
3.30. Channel 4 status register
3.31. Channel 4 gain calibration register
3.32. Channel 4 offset calibration register
3.33. Channel 4 saturation register
3.34. Multi-shot sample depth register

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Control register | fmc_adc_core_ctl | CTL
0x1 | REG | Status register | fmc_adc_core_sta | STA
0x2 | REG | Trigger configuration | fmc_adc_core_trig_cfg | TRIG_CFG
0x3 | REG | Trigger delay | fmc_adc_core_trig_dly | TRIG_DLY
0x4 | REG | Software trigger | fmc_adc_core_sw_trig | SW_TRIG
0x5 | REG | Number of shots | fmc_adc_core_shots | SHOTS
0x6 | REG | Remaining shots counter | fmc_adc_core_shots_cnt | SHOTS_CNT
0x7 | REG | Trigger address register | fmc_adc_core_trig_pos | TRIG_POS
0x8 | REG | Sampling clock frequency | fmc_adc_core_fs_freq | FS_FREQ
0x9 | REG | Sample rate | fmc_adc_core_sr | SR
0xa | REG | Pre-trigger samples | fmc_adc_core_pre_samples | PRE_SAMPLES
0xb | REG | Post-trigger samples | fmc_adc_core_post_samples | POST_SAMPLES
0xc | REG | Samples counter | fmc_adc_core_samples_cnt | SAMPLES_CNT
0xd | REG | Channel 1 control register | fmc_adc_core_ch1_ctl | CH1_CTL
0xe | REG | Channel 1 status register | fmc_adc_core_ch1_sta | CH1_STA
0xf | REG | Channel 1 gain calibration register | fmc_adc_core_ch1_gain | CH1_GAIN
0x10 | REG | Channel 1 offset calibration register | fmc_adc_core_ch1_offset | CH1_OFFSET
0x11 | REG | Channel 1 saturation register | fmc_adc_core_ch1_sat | CH1_SAT
0x12 | REG | Channel 2 control register | fmc_adc_core_ch2_ctl | CH2_CTL
0x13 | REG | Channel 2 status register | fmc_adc_core_ch2_sta | CH2_STA
0x14 | REG | Channel 2 gain calibration register | fmc_adc_core_ch2_gain | CH2_GAIN
0x15 | REG | Channel 2 offset calibration register | fmc_adc_core_ch2_offset | CH2_OFFSET
0x16 | REG | Channel 2 saturation register | fmc_adc_core_ch2_sat | CH2_SAT
0x17 | REG | Channel 3 control register | fmc_adc_core_ch3_ctl | CH3_CTL
0x18 | REG | Channel 3 status register | fmc_adc_core_ch3_sta | CH3_STA
0x19 | REG | Channel 3 gain calibration register | fmc_adc_core_ch3_gain | CH3_GAIN
0x1a | REG | Channel 3 offset calibration register | fmc_adc_core_ch3_offset | CH3_OFFSET
0x1b | REG | Channel 3 saturation register | fmc_adc_core_ch3_sat | CH3_SAT
0x1c | REG | Channel 4 control register | fmc_adc_core_ch4_ctl | CH4_CTL
0x1d | REG | Channel 4 status register | fmc_adc_core_ch4_sta | CH4_STA
0x1e | REG | Channel 4 gain calibration register | fmc_adc_core_ch4_gain | CH4_GAIN
0x1f | REG | Channel 4 offset calibration register | fmc_adc_core_ch4_offset | CH4_OFFSET
0x20 | REG | Channel 4 saturation register | fmc_adc_core_ch4_sat | CH4_SAT
0x21 | REG | Multi-shot sample depth register | fmc_adc_core_multi_depth | MULTI_DEPTH

### 2. HDL symbol

→ | rst_n_i |  | Control register: |
→ | clk_sys_i |  | fmc_adc_core_ctl_fsm_cmd_o[1:0] | ⇒
⇒ | wb_adr_i[5:0] |  | fmc_adc_core_ctl_fsm_cmd_wr_o | →
⇒ | wb_dat_i[31:0] |  | fmc_adc_core_ctl_fmc_clk_oe_o | →
⇐ | wb_dat_o[31:0] |  | fmc_adc_core_ctl_offset_dac_clr_n_o | →
→ | wb_cyc_i |  | fmc_adc_core_ctl_man_bitslip_o | →
⇒ | wb_sel_i[3:0] |  | fmc_adc_core_ctl_test_data_en_o | →
→ | wb_stb_i |  | fmc_adc_core_ctl_trig_led_o | →
→ | wb_we_i |  | fmc_adc_core_ctl_acq_led_o | →
← | wb_ack_o |  |  |
← | wb_stall_o |  | Status register: |
|  |  | fmc_adc_core_sta_fsm_i[2:0] | ⇐
|  |  | fmc_adc_core_sta_serdes_pll_i | ←
|  |  | fmc_adc_core_sta_serdes_synced_i | ←
|  |  | fmc_adc_core_sta_acq_cfg_i | ←
|  |  | Trigger configuration: |
|  |  | fmc_adc_core_trig_cfg_hw_trig_sel_o | →
|  |  | fmc_adc_core_trig_cfg_hw_trig_pol_o | →
|  |  | fmc_adc_core_trig_cfg_hw_trig_en_o | →
|  |  | fmc_adc_core_trig_cfg_sw_trig_en_o | →
|  |  | fmc_adc_core_trig_cfg_int_trig_sel_o[1:0] | ⇒
|  |  | fmc_adc_core_trig_cfg_int_trig_test_en_o | →
|  |  | fmc_adc_core_trig_cfg_reserved_o | →
|  |  | fmc_adc_core_trig_cfg_int_trig_thres_filt_o[7:0] | ⇒
|  |  | fmc_adc_core_trig_cfg_int_trig_thres_o[15:0] | ⇒
|  |  | Trigger delay: |
|  |  | fmc_adc_core_trig_dly_o[31:0] | ⇒
|  |  | Software trigger: |
|  |  | fmc_adc_core_sw_trig_o[31:0] | ⇒
|  |  | fmc_adc_core_sw_trig_wr_o | →
|  |  | Number of shots: |
|  |  | fmc_adc_core_shots_nb_o[15:0] | ⇒
|  |  | Remaining shots counter: |
|  |  | fmc_adc_core_shots_cnt_val_i[15:0] | ⇐
|  |  | Trigger address register: |
|  |  | fmc_adc_core_trig_pos_i[31:0] | ⇐
|  |  | Sampling clock frequency: |
|  |  | fmc_adc_core_fs_freq_i[31:0] | ⇐
|  |  | Sample rate: |
|  |  | fmc_adc_core_sr_undersample_o[31:0] | ⇒
|  |  | Pre-trigger samples: |
|  |  | fmc_adc_core_pre_samples_o[31:0] | ⇒
|  |  | Post-trigger samples: |
|  |  | fmc_adc_core_post_samples_o[31:0] | ⇒
|  |  | Samples counter: |
|  |  | fmc_adc_core_samples_cnt_i[31:0] | ⇐
|  |  | Channel 1 control register: |
|  |  | fmc_adc_core_ch1_ctl_ssr_o[6:0] | ⇒
|  |  | Channel 1 status register: |
|  |  | fmc_adc_core_ch1_sta_val_i[15:0] | ⇐
|  |  | Channel 1 gain calibration register: |
|  |  | fmc_adc_core_ch1_gain_val_o[15:0] | ⇒
|  |  | Channel 1 offset calibration register: |
|  |  | fmc_adc_core_ch1_offset_val_o[15:0] | ⇒
|  |  | Channel 1 saturation register: |
|  |  | fmc_adc_core_ch1_sat_val_o[14:0] | ⇒
|  |  | Channel 2 control register: |
|  |  | fmc_adc_core_ch2_ctl_ssr_o[6:0] | ⇒
|  |  | Channel 2 status register: |
|  |  | fmc_adc_core_ch2_sta_val_i[15:0] | ⇐
|  |  | Channel 2 gain calibration register: |
|  |  | fmc_adc_core_ch2_gain_val_o[15:0] | ⇒
|  |  | Channel 2 offset calibration register: |
|  |  | fmc_adc_core_ch2_offset_val_o[15:0] | ⇒
|  |  | Channel 2 saturation register: |
|  |  | fmc_adc_core_ch2_sat_val_o[14:0] | ⇒
|  |  | Channel 3 control register: |
|  |  | fmc_adc_core_ch3_ctl_ssr_o[6:0] | ⇒
|  |  | Channel 3 status register: |
|  |  | fmc_adc_core_ch3_sta_val_i[15:0] | ⇐
|  |  | Channel 3 gain calibration register: |
|  |  | fmc_adc_core_ch3_gain_val_o[15:0] | ⇒
|  |  | Channel 3 offset calibration register: |
|  |  | fmc_adc_core_ch3_offset_val_o[15:0] | ⇒
|  |  | Channel 3 saturation register: |
|  |  | fmc_adc_core_ch3_sat_val_o[14:0] | ⇒
|  |  | Channel 4 control register: |
|  |  | fmc_adc_core_ch4_ctl_ssr_o[6:0] | ⇒
|  |  | Channel 4 status register: |
|  |  | fmc_adc_core_ch4_sta_val_i[15:0] | ⇐
|  |  | Channel 4 gain calibration register: |
|  |  | fmc_adc_core_ch4_gain_val_o[15:0] | ⇒
|  |  | Channel 4 offset calibration register: |
|  |  | fmc_adc_core_ch4_offset_val_o[15:0] | ⇒
|  |  | Channel 4 saturation register: |
|  |  | fmc_adc_core_ch4_sat_val_o[14:0] | ⇒
|  |  | Multi-shot sample depth register: |
|  |  | fmc_adc_core_multi_depth_i[31:0] | ⇐

### 3. Register description

### 3.1. Control register

HW prefix: | fmc_adc_core_ctl
HW address: | 0x0
C prefix: | CTL
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ACQ_LED | TRIG_LED | TEST_DATA_EN | MAN_BITSLIP | OFFSET_DAC_CLR_N | FMC_CLK_OE | FSM_CMD[1:0] |

- FSM_CMD [read/write]: State machine commands (ignore on read)
  1: ACQ_START (start acquisition, only when FSM is idle)
  2: ACQ_STOP (stop acquisition, anytime)
- FMC_CLK_OE [read/write]: FMC Si750 output enable
- OFFSET_DAC_CLR_N [read/write]: Offset DACs clear (active low)
- MAN_BITSLIP [write-only]: Manual serdes bitslip (ignore on read)
- TEST_DATA_EN [read/write]: Enable test data
  Write the address counter value instead of ADC data to DDR
- TRIG_LED [read/write]: Manual TRIG LED
  Manual control of the front panel TRIG LED
- ACQ_LED [read/write]: Manual ACQ LED
  Manual control of the front panel ACQ LED

### 3.2. Status register

HW prefix: | fmc_adc_core_sta
HW address: | 0x1
C prefix: | STA
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | ACQ_CFG | SERDES_SYNCED | SERDES_PLL | FSM[2:0] |  |

- FSM [read-only]: State machine status
  States:
  0: illegal
  1: IDLE
  2: PRE_TRIG
  3: WAIT_TRIG
  4: POST_TRIG
  5: TRIG_TAG
  6: DECR_SHOT
  7: illegal
- SERDES_PLL [read-only]: SerDes PLL status
  Sampling clock recovery PLL.
  0: not locked
  1: locked
- SERDES_SYNCED [read-only]: SerDes synchronization status
  0: bitslip in progress
  1: serdes synchronized
- ACQ_CFG [read-only]: Acquisition configuration status
  0: Unauthorised acquisition configuration (will prevent acquisition to start)
  1: Valid acquisition configuration
  - Shot number > 0
  - Post-trigger sample > 0

### 3.3. Trigger configuration

HW prefix: | fmc_adc_core_trig_cfg
HW address: | 0x2
C prefix: | TRIG_CFG
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
INT_TRIG_THRES[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
INT_TRIG_THRES[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_TRIG_THRES_FILT[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED | INT_TRIG_TEST_EN | INT_TRIG_SEL[1:0] | SW_TRIG_EN | HW_TRIG_EN | HW_TRIG_POL | HW_TRIG_SEL |

- HW_TRIG_SEL [read/write]: Hardware trigger selection
  0: internal (data threshold)
  1: external (front panel trigger input)
- HW_TRIG_POL [read/write]: Hardware trigger polarity
  0: positive edge/slope
  1: negative edge/slope
- HW_TRIG_EN [read/write]: Hardware trigger enable
  0: disable
  1: enable
- SW_TRIG_EN [read/write]: Software trigger enable
  0: disable
  1: enable
- INT_TRIG_SEL [read/write]: Channel selection for internal trigger
  00: channel 1
  01: channel 2
  10: channel 3
  11: channel 4
- INT_TRIG_TEST_EN [read/write]: Enable internal trigger test mode
  Test mode:
  ch1 = Channel 1 input(analogue)
  ch2 = Channel input over threshold (digital)
  ch3 = Channel input over threshold filtered (digital)
  ch4 = Trigger (digital)
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's
- INT_TRIG_THRES_FILT [read/write]: Internal trigger threshold glitch filter
  Configures the internal trigger threshold glitch filter length.
- INT_TRIG_THRES [read/write]: Threshold for internal trigger
  Treated as binary two's complement and compared to raw ADC data.

### 3.4. Trigger delay

HW prefix: | fmc_adc_core_trig_dly
HW address: | 0x3
C prefix: | TRIG_DLY
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRIG_DLY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TRIG_DLY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRIG_DLY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIG_DLY[7:0] |  |  |  |  |  |  |

- TRIG_DLY [read/write]: Trigger delay value
  Delay to apply on the trigger in sampling clock period.
  The default clock frequency is 100MHz (period = 10ns).

### 3.5. Software trigger

HW prefix: | fmc_adc_core_sw_trig
HW address: | 0x4
C prefix: | SW_TRIG
C offset: | 0x10

Writing (anything) to this register generates a software trigger.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SW_TRIG[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SW_TRIG[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SW_TRIG[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SW_TRIG[7:0] |  |  |  |  |  |  |

- SW_TRIG [write-only]: Software trigger (ignore on read)

### 3.6. Number of shots

HW prefix: | fmc_adc_core_shots
HW address: | 0x5
C prefix: | SHOTS
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NB[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NB[7:0] |  |  |  |  |  |  |

- NB [read/write]: Number of shots
  Number of shots required in multi-shot mode, set to one for single-shot mode.

### 3.7. Remaining shots counter

HW prefix: | fmc_adc_core_shots_cnt
HW address: | 0x6
C prefix: | SHOTS_CNT
C offset: | 0x18

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Remaining shots counter
  Counts the number of remaining shots to acquire.

### 3.8. Trigger address register

HW prefix: | fmc_adc_core_trig_pos
HW address: | 0x7
C prefix: | TRIG_POS
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRIG_POS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TRIG_POS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRIG_POS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIG_POS[7:0] |  |  |  |  |  |  |

- TRIG_POS [read-only]: Trigger address
  Trigger address in DDR memory.
  Only used in single-shot mode.

### 3.9. Sampling clock frequency

HW prefix: | fmc_adc_core_fs_freq
HW address: | 0x8
C prefix: | FS_FREQ
C offset: | 0x20

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
FS_FREQ[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
FS_FREQ[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
FS_FREQ[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FS_FREQ[7:0] |  |  |  |  |  |  |

- FS_FREQ [read-only]: Sampling clock frequency
  ADC sampling clock frequency in Hz

### 3.10. Sample rate

HW prefix: | fmc_adc_core_sr
HW address: | 0x9
C prefix: | SR
C offset: | 0x24

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
UNDERSAMPLE[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
UNDERSAMPLE[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
UNDERSAMPLE[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
UNDERSAMPLE[7:0] |  |  |  |  |  |  |

- UNDERSAMPLE [read/write]: Undersampling ratio
  Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio).

### 3.11. Pre-trigger samples

HW prefix: | fmc_adc_core_pre_samples
HW address: | 0xa
C prefix: | PRE_SAMPLES
C offset: | 0x28

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
PRE_SAMPLES[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PRE_SAMPLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PRE_SAMPLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PRE_SAMPLES[7:0] |  |  |  |  |  |  |

- PRE_SAMPLES [read/write]: Pre-trigger samples
  Number of requested pre-trigger samples (>1).

### 3.12. Post-trigger samples

HW prefix: | fmc_adc_core_post_samples
HW address: | 0xb
C prefix: | POST_SAMPLES
C offset: | 0x2c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
POST_SAMPLES[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
POST_SAMPLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
POST_SAMPLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
POST_SAMPLES[7:0] |  |  |  |  |  |  |

- POST_SAMPLES [read/write]: Post-trigger samples
  Number of requested post-trigger samples (>1).

### 3.13. Samples counter

HW prefix: | fmc_adc_core_samples_cnt
HW address: | 0xc
C prefix: | SAMPLES_CNT
C offset: | 0x30

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SAMPLES_CNT[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SAMPLES_CNT[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SAMPLES_CNT[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SAMPLES_CNT[7:0] |  |  |  |  |  |  |

- SAMPLES_CNT [read-only]: Samples counter
  Counts the number of samples.
  It is reset on START and then counts the number of pre-trigger + post-trigger samples

### 3.14. Channel 1 control register

HW prefix: | fmc_adc_core_ch1_ctl
HW address: | 0xd
C prefix: | CH1_CTL
C offset: | 0x34

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | SSR[6:0] |  |  |  |  |  |

- SSR [read/write]: Solid state relays control for channel 1
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

### 3.15. Channel 1 status register

HW prefix: | fmc_adc_core_ch1_sta
HW address: | 0xe
C prefix: | CH1_STA
C offset: | 0x38

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 1 current ADC value
  Current ADC raw value. The format is binary two's complement.

### 3.16. Channel 1 gain calibration register

HW prefix: | fmc_adc_core_ch1_gain
HW address: | 0xf
C prefix: | CH1_GAIN
C offset: | 0x3c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Gain calibration for channel 1
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)

### 3.17. Channel 1 offset calibration register

HW prefix: | fmc_adc_core_ch1_offset
HW address: | 0x10
C prefix: | CH1_OFFSET
C offset: | 0x40

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Offset calibration for channel 1
  Offset applied to all data coming from the ADC. The format is binary two's complement.

### 3.18. Channel 1 saturation register

HW prefix: | fmc_adc_core_ch1_sat
HW address: | 0x11
C prefix: | CH1_SAT
C offset: | 0x44

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | VAL[14:8] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Saturation value for channel 1
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

### 3.19. Channel 2 control register

HW prefix: | fmc_adc_core_ch2_ctl
HW address: | 0x12
C prefix: | CH2_CTL
C offset: | 0x48

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | SSR[6:0] |  |  |  |  |  |

- SSR [read/write]: Solid state relays control for channel 2
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

### 3.20. Channel 2 status register

HW prefix: | fmc_adc_core_ch2_sta
HW address: | 0x13
C prefix: | CH2_STA
C offset: | 0x4c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 2 current ACD value
  Current ADC raw value. The format is binary two's complement.

### 3.21. Channel 2 gain calibration register

HW prefix: | fmc_adc_core_ch2_gain
HW address: | 0x14
C prefix: | CH2_GAIN
C offset: | 0x50

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Gain calibration for channel 2
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)

### 3.22. Channel 2 offset calibration register

HW prefix: | fmc_adc_core_ch2_offset
HW address: | 0x15
C prefix: | CH2_OFFSET
C offset: | 0x54

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Offset calibration for channel 2
  Offset applied to all data coming from the ADC. The format is binary two's complement.

### 3.23. Channel 2 saturation register

HW prefix: | fmc_adc_core_ch2_sat
HW address: | 0x16
C prefix: | CH2_SAT
C offset: | 0x58

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | VAL[14:8] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Saturation value for channel 2
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

### 3.24. Channel 3 control register

HW prefix: | fmc_adc_core_ch3_ctl
HW address: | 0x17
C prefix: | CH3_CTL
C offset: | 0x5c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | SSR[6:0] |  |  |  |  |  |

- SSR [read/write]: Solid state relays control for channel 3
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

### 3.25. Channel 3 status register

HW prefix: | fmc_adc_core_ch3_sta
HW address: | 0x18
C prefix: | CH3_STA
C offset: | 0x60

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 3 current ADC value
  Current ADC raw value. The format is binary two's complement.

### 3.26. Channel 3 gain calibration register

HW prefix: | fmc_adc_core_ch3_gain
HW address: | 0x19
C prefix: | CH3_GAIN
C offset: | 0x64

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Gain calibration for channel 3
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)

### 3.27. Channel 3 offset calibration register

HW prefix: | fmc_adc_core_ch3_offset
HW address: | 0x1a
C prefix: | CH3_OFFSET
C offset: | 0x68

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Offset calibration for channel 3
  Offset applied to all data coming from the ADC. The format is binary two's complement.

### 3.28. Channel 3 saturation register

HW prefix: | fmc_adc_core_ch3_sat
HW address: | 0x1b
C prefix: | CH3_SAT
C offset: | 0x6c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | VAL[14:8] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Saturation value for channel 3
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

### 3.29. Channel 4 control register

HW prefix: | fmc_adc_core_ch4_ctl
HW address: | 0x1c
C prefix: | CH4_CTL
C offset: | 0x70

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | SSR[6:0] |  |  |  |  |  |

- SSR [read/write]: Solid state relays control for channel 4
  Controls input voltage range, termination and DC offset error calibration
  0x23: 100mV range
  0x11: 1V range
  0x45: 10V range
  0x00: Open input
  0x42: 100mV range calibration
  0x40: 1V range calibration
  0x44: 10V range calibration
  Bit3 is indepandant of the others and enables the 50ohms termination.

### 3.30. Channel 4 status register

HW prefix: | fmc_adc_core_ch4_sta
HW address: | 0x1d
C prefix: | CH4_STA
C offset: | 0x74

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 4 current ADC value
  Current ADC raw value. The format is binary two's complement.

### 3.31. Channel 4 gain calibration register

HW prefix: | fmc_adc_core_ch4_gain
HW address: | 0x1e
C prefix: | CH4_GAIN
C offset: | 0x78

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Gain calibration for channel 4
  Gain applied to all data coming from the ADC.
  Fixed point format:
  Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)

### 3.32. Channel 4 offset calibration register

HW prefix: | fmc_adc_core_ch4_offset
HW address: | 0x1f
C prefix: | CH4_OFFSET
C offset: | 0x7c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Offset calibration for channel 4
  Offset applied to all data coming from the ADC. The format is binary two's complement.

### 3.33. Channel 4 saturation register

HW prefix: | fmc_adc_core_ch4_sat
HW address: | 0x20
C prefix: | CH4_SAT
C offset: | 0x80

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | VAL[14:8] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read/write]: Saturation value for channel 4
  Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.

### 3.34. Multi-shot sample depth register

HW prefix: | fmc_adc_core_multi_depth
HW address: | 0x21
C prefix: | MULTI_DEPTH
C offset: | 0x84

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
MULTI_DEPTH[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
MULTI_DEPTH[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
MULTI_DEPTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
MULTI_DEPTH[7:0] |  |  |  |  |  |  |

- MULTI_DEPTH [read-only]: Multi-shot sample depth
  Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag