fmc_adc_100ms_csr

FMC ADC 100MS/s core registers

Wishbone slave for FMC ADC 100MS/s core

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control register
3.2. Status register
3.3. Trigger status
3.4. Trigger enable
3.5. Trigger polarity
3.6. External trigger delay
3.7. Software trigger
3.8. Number of shots
3.9. Multi-shot sample depth register
3.10. Remaining shots counter
3.11. Trigger address register
3.12. Sampling clock frequency
3.13. Sample rate
3.14. Pre-trigger samples
3.15. Post-trigger samples
3.16. Samples counter
3.17. Channel 1 control register
3.18. Channel 1 status register
3.19. Channel 1 gain calibration register
3.20. Channel 1 offset calibration register
3.21. Channel 1 saturation register
3.22. Channel 1 trigger threshold configuration register
3.23. Channel 1 trigger delay
3.24. Channel 2 control register
3.25. Channel 2 status register
3.26. Channel 2 gain calibration register
3.27. Channel 2 offset calibration register
3.28. Channel 2 saturation register
3.29. Channel 2 trigger threshold configuration register
3.30. Channel 2 trigger delay
3.31. Channel 3 control register
3.32. Channel 3 status register
3.33. Channel 3 gain calibration register
3.34. Channel 3 offset calibration register
3.35. Channel 3 saturation register
3.36. Channel 3 trigger threshold configuration register
3.37. Channel 3 trigger delay
3.38. Channel 4 control register
3.39. Channel 4 status register
3.40. Channel 4 gain calibration register
3.41. Channel 4 offset calibration register
3.42. Channel 4 saturation register
3.43. Channel 4 trigger threshold configuration register
3.44. Channel 4 trigger delay

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Control register fmc_adc_100ms_csr_ctl CTL
0x1 REG Status register fmc_adc_100ms_csr_sta STA
0x2 REG Trigger status fmc_adc_100ms_csr_trig_stat TRIG_STAT
0x3 REG Trigger enable fmc_adc_100ms_csr_trig_en TRIG_EN
0x4 REG Trigger polarity fmc_adc_100ms_csr_trig_pol TRIG_POL
0x5 REG External trigger delay fmc_adc_100ms_csr_ext_trig_dly EXT_TRIG_DLY
0x6 REG Software trigger fmc_adc_100ms_csr_sw_trig SW_TRIG
0x7 REG Number of shots fmc_adc_100ms_csr_shots SHOTS
0x8 REG Multi-shot sample depth register fmc_adc_100ms_csr_multi_depth MULTI_DEPTH
0x9 REG Remaining shots counter fmc_adc_100ms_csr_shots_cnt SHOTS_CNT
0xa REG Trigger address register fmc_adc_100ms_csr_trig_pos TRIG_POS
0xb REG Sampling clock frequency fmc_adc_100ms_csr_fs_freq FS_FREQ
0xc REG Sample rate fmc_adc_100ms_csr_sr SR
0xd REG Pre-trigger samples fmc_adc_100ms_csr_pre_samples PRE_SAMPLES
0xe REG Post-trigger samples fmc_adc_100ms_csr_post_samples POST_SAMPLES
0xf REG Samples counter fmc_adc_100ms_csr_samples_cnt SAMPLES_CNT
0x20 REG Channel 1 control register fmc_adc_100ms_csr_ch1_ctl CH1_CTL
0x21 REG Channel 1 status register fmc_adc_100ms_csr_ch1_sta CH1_STA
0x22 REG Channel 1 gain calibration register fmc_adc_100ms_csr_ch1_gain CH1_GAIN
0x23 REG Channel 1 offset calibration register fmc_adc_100ms_csr_ch1_offset CH1_OFFSET
0x24 REG Channel 1 saturation register fmc_adc_100ms_csr_ch1_sat CH1_SAT
0x25 REG Channel 1 trigger threshold configuration register fmc_adc_100ms_csr_ch1_trig_thres CH1_TRIG_THRES
0x26 REG Channel 1 trigger delay fmc_adc_100ms_csr_ch1_trig_dly CH1_TRIG_DLY
0x40 REG Channel 2 control register fmc_adc_100ms_csr_ch2_ctl CH2_CTL
0x41 REG Channel 2 status register fmc_adc_100ms_csr_ch2_sta CH2_STA
0x42 REG Channel 2 gain calibration register fmc_adc_100ms_csr_ch2_gain CH2_GAIN
0x43 REG Channel 2 offset calibration register fmc_adc_100ms_csr_ch2_offset CH2_OFFSET
0x44 REG Channel 2 saturation register fmc_adc_100ms_csr_ch2_sat CH2_SAT
0x45 REG Channel 2 trigger threshold configuration register fmc_adc_100ms_csr_ch2_trig_thres CH2_TRIG_THRES
0x46 REG Channel 2 trigger delay fmc_adc_100ms_csr_ch2_trig_dly CH2_TRIG_DLY
0x60 REG Channel 3 control register fmc_adc_100ms_csr_ch3_ctl CH3_CTL
0x61 REG Channel 3 status register fmc_adc_100ms_csr_ch3_sta CH3_STA
0x62 REG Channel 3 gain calibration register fmc_adc_100ms_csr_ch3_gain CH3_GAIN
0x63 REG Channel 3 offset calibration register fmc_adc_100ms_csr_ch3_offset CH3_OFFSET
0x64 REG Channel 3 saturation register fmc_adc_100ms_csr_ch3_sat CH3_SAT
0x65 REG Channel 3 trigger threshold configuration register fmc_adc_100ms_csr_ch3_trig_thres CH3_TRIG_THRES
0x66 REG Channel 3 trigger delay fmc_adc_100ms_csr_ch3_trig_dly CH3_TRIG_DLY
0x80 REG Channel 4 control register fmc_adc_100ms_csr_ch4_ctl CH4_CTL
0x81 REG Channel 4 status register fmc_adc_100ms_csr_ch4_sta CH4_STA
0x82 REG Channel 4 gain calibration register fmc_adc_100ms_csr_ch4_gain CH4_GAIN
0x83 REG Channel 4 offset calibration register fmc_adc_100ms_csr_ch4_offset CH4_OFFSET
0x84 REG Channel 4 saturation register fmc_adc_100ms_csr_ch4_sat CH4_SAT
0x85 REG Channel 4 trigger threshold configuration register fmc_adc_100ms_csr_ch4_trig_thres CH4_TRIG_THRES
0x86 REG Channel 4 trigger delay fmc_adc_100ms_csr_ch4_trig_dly CH4_TRIG_DLY

2. HDL symbol

wb_adr_i[7:0] Control register:
wb_dat_i[31:0] fmc_adc_100ms_csr_ctl_fsm_cmd_o[1:0]
wb_dat_o[31:0] fmc_adc_100ms_csr_ctl_fsm_cmd_wr_o
wb_cyc_i fmc_adc_100ms_csr_ctl_fmc_clk_oe_o
wb_sel_i[3:0] fmc_adc_100ms_csr_ctl_offset_dac_clr_n_o
wb_stb_i fmc_adc_100ms_csr_ctl_man_bitslip_o
wb_we_i fmc_adc_100ms_csr_ctl_test_data_en_o
wb_ack_o fmc_adc_100ms_csr_ctl_trig_led_o
wb_err_o fmc_adc_100ms_csr_ctl_acq_led_o
wb_rty_o fmc_adc_100ms_csr_ctl_clear_trig_stat_o
wb_stall_o  
Status register:
fmc_adc_100ms_csr_sta_fsm_i[2:0]
fmc_adc_100ms_csr_sta_serdes_pll_i
fmc_adc_100ms_csr_sta_serdes_synced_i
fmc_adc_100ms_csr_sta_acq_cfg_i
 
Trigger status:
fmc_adc_100ms_csr_trig_stat_ext_i
fmc_adc_100ms_csr_trig_stat_sw_i
fmc_adc_100ms_csr_trig_stat_time_i
fmc_adc_100ms_csr_trig_stat_ch1_i
fmc_adc_100ms_csr_trig_stat_ch2_i
fmc_adc_100ms_csr_trig_stat_ch3_i
fmc_adc_100ms_csr_trig_stat_ch4_i
 
Trigger enable:
fmc_adc_100ms_csr_trig_en_ext_o
fmc_adc_100ms_csr_trig_en_sw_o
fmc_adc_100ms_csr_trig_en_time_o
fmc_adc_100ms_csr_trig_en_alt_time_o
fmc_adc_100ms_csr_trig_en_ch1_o
fmc_adc_100ms_csr_trig_en_ch2_o
fmc_adc_100ms_csr_trig_en_ch3_o
fmc_adc_100ms_csr_trig_en_ch4_o
 
Trigger polarity:
fmc_adc_100ms_csr_trig_pol_ext_o
fmc_adc_100ms_csr_trig_pol_ch1_o
fmc_adc_100ms_csr_trig_pol_ch2_o
fmc_adc_100ms_csr_trig_pol_ch3_o
fmc_adc_100ms_csr_trig_pol_ch4_o
 
External trigger delay:
fmc_adc_100ms_csr_ext_trig_dly_o[31:0]
 
Software trigger:
fmc_adc_100ms_csr_sw_trig_o[31:0]
fmc_adc_100ms_csr_sw_trig_wr_o
 
Number of shots:
fmc_adc_100ms_csr_shots_nb_o[15:0]
 
Multi-shot sample depth register:
fmc_adc_100ms_csr_multi_depth_i[31:0]
 
Remaining shots counter:
fmc_adc_100ms_csr_shots_cnt_val_i[15:0]
 
Trigger address register:
fmc_adc_100ms_csr_trig_pos_i[31:0]
 
Sampling clock frequency:
fmc_adc_100ms_csr_fs_freq_i[31:0]
 
Sample rate:
fmc_adc_100ms_csr_sr_undersample_o[31:0]
 
Pre-trigger samples:
fmc_adc_100ms_csr_pre_samples_o[31:0]
 
Post-trigger samples:
fmc_adc_100ms_csr_post_samples_o[31:0]
 
Samples counter:
fmc_adc_100ms_csr_samples_cnt_i[31:0]
 
Channel 1 control register:
fmc_adc_100ms_csr_ch1_ctl_ssr_o[6:0]
 
Channel 1 status register:
fmc_adc_100ms_csr_ch1_sta_val_i[15:0]
 
Channel 1 gain calibration register:
fmc_adc_100ms_csr_ch1_gain_val_o[15:0]
 
Channel 1 offset calibration register:
fmc_adc_100ms_csr_ch1_offset_val_o[15:0]
 
Channel 1 saturation register:
fmc_adc_100ms_csr_ch1_sat_val_o[14:0]
 
Channel 1 trigger threshold configuration register:
fmc_adc_100ms_csr_ch1_trig_thres_val_o[15:0]
fmc_adc_100ms_csr_ch1_trig_thres_hyst_o[15:0]
 
Channel 1 trigger delay:
fmc_adc_100ms_csr_ch1_trig_dly_o[31:0]
 
Channel 2 control register:
fmc_adc_100ms_csr_ch2_ctl_ssr_o[6:0]
 
Channel 2 status register:
fmc_adc_100ms_csr_ch2_sta_val_i[15:0]
 
Channel 2 gain calibration register:
fmc_adc_100ms_csr_ch2_gain_val_o[15:0]
 
Channel 2 offset calibration register:
fmc_adc_100ms_csr_ch2_offset_val_o[15:0]
 
Channel 2 saturation register:
fmc_adc_100ms_csr_ch2_sat_val_o[14:0]
 
Channel 2 trigger threshold configuration register:
fmc_adc_100ms_csr_ch2_trig_thres_val_o[15:0]
fmc_adc_100ms_csr_ch2_trig_thres_hyst_o[15:0]
 
Channel 2 trigger delay:
fmc_adc_100ms_csr_ch2_trig_dly_o[31:0]
 
Channel 3 control register:
fmc_adc_100ms_csr_ch3_ctl_ssr_o[6:0]
 
Channel 3 status register:
fmc_adc_100ms_csr_ch3_sta_val_i[15:0]
 
Channel 3 gain calibration register:
fmc_adc_100ms_csr_ch3_gain_val_o[15:0]
 
Channel 3 offset calibration register:
fmc_adc_100ms_csr_ch3_offset_val_o[15:0]
 
Channel 3 saturation register:
fmc_adc_100ms_csr_ch3_sat_val_o[14:0]
 
Channel 3 trigger threshold configuration register:
fmc_adc_100ms_csr_ch3_trig_thres_val_o[15:0]
fmc_adc_100ms_csr_ch3_trig_thres_hyst_o[15:0]
 
Channel 3 trigger delay:
fmc_adc_100ms_csr_ch3_trig_dly_o[31:0]
 
Channel 4 control register:
fmc_adc_100ms_csr_ch4_ctl_ssr_o[6:0]
 
Channel 4 status register:
fmc_adc_100ms_csr_ch4_sta_val_i[15:0]
 
Channel 4 gain calibration register:
fmc_adc_100ms_csr_ch4_gain_val_o[15:0]
 
Channel 4 offset calibration register:
fmc_adc_100ms_csr_ch4_offset_val_o[15:0]
 
Channel 4 saturation register:
fmc_adc_100ms_csr_ch4_sat_val_o[14:0]
 
Channel 4 trigger threshold configuration register:
fmc_adc_100ms_csr_ch4_trig_thres_val_o[15:0]
fmc_adc_100ms_csr_ch4_trig_thres_hyst_o[15:0]
 
Channel 4 trigger delay:
fmc_adc_100ms_csr_ch4_trig_dly_o[31:0]

3. Register description

3.1. Control register

HW prefix: fmc_adc_100ms_csr_ctl
HW address: 0x0
C prefix: CTL
C offset: 0x0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - CLEAR_TRIG_STAT
7 6 5 4 3 2 1 0
ACQ_LED TRIG_LED TEST_DATA_EN MAN_BITSLIP OFFSET_DAC_CLR_N FMC_CLK_OE FSM_CMD[1:0]

3.2. Status register

HW prefix: fmc_adc_100ms_csr_sta
HW address: 0x1
C prefix: STA
C offset: 0x4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - ACQ_CFG SERDES_SYNCED SERDES_PLL FSM[2:0]

3.3. Trigger status

HW prefix: fmc_adc_100ms_csr_trig_stat
HW address: 0x2
C prefix: TRIG_STAT
C offset: 0x8

Shows the source(s) of the last received trigger.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - CH4 CH3 CH2 CH1
7 6 5 4 3 2 1 0
- - - TIME - - SW EXT

3.4. Trigger enable

HW prefix: fmc_adc_100ms_csr_trig_en
HW address: 0x3
C prefix: TRIG_EN
C offset: 0xc
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - CH4 CH3 CH2 CH1
7 6 5 4 3 2 1 0
- - ALT_TIME TIME - - SW EXT

3.5. Trigger polarity

HW prefix: fmc_adc_100ms_csr_trig_pol
HW address: 0x4
C prefix: TRIG_POL
C offset: 0x10
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - CH4 CH3 CH2 CH1
7 6 5 4 3 2 1 0
- - - - - - - EXT

3.6. External trigger delay

HW prefix: fmc_adc_100ms_csr_ext_trig_dly
HW address: 0x5
C prefix: EXT_TRIG_DLY
C offset: 0x14
31 30 29 28 27 26 25 24
EXT_TRIG_DLY[31:24]
23 22 21 20 19 18 17 16
EXT_TRIG_DLY[23:16]
15 14 13 12 11 10 9 8
EXT_TRIG_DLY[15:8]
7 6 5 4 3 2 1 0
EXT_TRIG_DLY[7:0]

3.7. Software trigger

HW prefix: fmc_adc_100ms_csr_sw_trig
HW address: 0x6
C prefix: SW_TRIG
C offset: 0x18

Writing (anything) to this register generates a software trigger.

31 30 29 28 27 26 25 24
SW_TRIG[31:24]
23 22 21 20 19 18 17 16
SW_TRIG[23:16]
15 14 13 12 11 10 9 8
SW_TRIG[15:8]
7 6 5 4 3 2 1 0
SW_TRIG[7:0]

3.8. Number of shots

HW prefix: fmc_adc_100ms_csr_shots
HW address: 0x7
C prefix: SHOTS
C offset: 0x1c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NB[15:8]
7 6 5 4 3 2 1 0
NB[7:0]

3.9. Multi-shot sample depth register

HW prefix: fmc_adc_100ms_csr_multi_depth
HW address: 0x8
C prefix: MULTI_DEPTH
C offset: 0x20
31 30 29 28 27 26 25 24
MULTI_DEPTH[31:24]
23 22 21 20 19 18 17 16
MULTI_DEPTH[23:16]
15 14 13 12 11 10 9 8
MULTI_DEPTH[15:8]
7 6 5 4 3 2 1 0
MULTI_DEPTH[7:0]

3.10. Remaining shots counter

HW prefix: fmc_adc_100ms_csr_shots_cnt
HW address: 0x9
C prefix: SHOTS_CNT
C offset: 0x24
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.11. Trigger address register

HW prefix: fmc_adc_100ms_csr_trig_pos
HW address: 0xa
C prefix: TRIG_POS
C offset: 0x28
31 30 29 28 27 26 25 24
TRIG_POS[31:24]
23 22 21 20 19 18 17 16
TRIG_POS[23:16]
15 14 13 12 11 10 9 8
TRIG_POS[15:8]
7 6 5 4 3 2 1 0
TRIG_POS[7:0]

3.12. Sampling clock frequency

HW prefix: fmc_adc_100ms_csr_fs_freq
HW address: 0xb
C prefix: FS_FREQ
C offset: 0x2c
31 30 29 28 27 26 25 24
FS_FREQ[31:24]
23 22 21 20 19 18 17 16
FS_FREQ[23:16]
15 14 13 12 11 10 9 8
FS_FREQ[15:8]
7 6 5 4 3 2 1 0
FS_FREQ[7:0]

3.13. Sample rate

HW prefix: fmc_adc_100ms_csr_sr
HW address: 0xc
C prefix: SR
C offset: 0x30
31 30 29 28 27 26 25 24
UNDERSAMPLE[31:24]
23 22 21 20 19 18 17 16
UNDERSAMPLE[23:16]
15 14 13 12 11 10 9 8
UNDERSAMPLE[15:8]
7 6 5 4 3 2 1 0
UNDERSAMPLE[7:0]

3.14. Pre-trigger samples

HW prefix: fmc_adc_100ms_csr_pre_samples
HW address: 0xd
C prefix: PRE_SAMPLES
C offset: 0x34
31 30 29 28 27 26 25 24
PRE_SAMPLES[31:24]
23 22 21 20 19 18 17 16
PRE_SAMPLES[23:16]
15 14 13 12 11 10 9 8
PRE_SAMPLES[15:8]
7 6 5 4 3 2 1 0
PRE_SAMPLES[7:0]

3.15. Post-trigger samples

HW prefix: fmc_adc_100ms_csr_post_samples
HW address: 0xe
C prefix: POST_SAMPLES
C offset: 0x38
31 30 29 28 27 26 25 24
POST_SAMPLES[31:24]
23 22 21 20 19 18 17 16
POST_SAMPLES[23:16]
15 14 13 12 11 10 9 8
POST_SAMPLES[15:8]
7 6 5 4 3 2 1 0
POST_SAMPLES[7:0]

3.16. Samples counter

HW prefix: fmc_adc_100ms_csr_samples_cnt
HW address: 0xf
C prefix: SAMPLES_CNT
C offset: 0x3c
31 30 29 28 27 26 25 24
SAMPLES_CNT[31:24]
23 22 21 20 19 18 17 16
SAMPLES_CNT[23:16]
15 14 13 12 11 10 9 8
SAMPLES_CNT[15:8]
7 6 5 4 3 2 1 0
SAMPLES_CNT[7:0]

3.17. Channel 1 control register

HW prefix: fmc_adc_100ms_csr_ch1_ctl
HW address: 0x20
C prefix: CH1_CTL
C offset: 0x80
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- SSR[6:0]

3.18. Channel 1 status register

HW prefix: fmc_adc_100ms_csr_ch1_sta
HW address: 0x21
C prefix: CH1_STA
C offset: 0x84
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.19. Channel 1 gain calibration register

HW prefix: fmc_adc_100ms_csr_ch1_gain
HW address: 0x22
C prefix: CH1_GAIN
C offset: 0x88
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.20. Channel 1 offset calibration register

HW prefix: fmc_adc_100ms_csr_ch1_offset
HW address: 0x23
C prefix: CH1_OFFSET
C offset: 0x8c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.21. Channel 1 saturation register

HW prefix: fmc_adc_100ms_csr_ch1_sat
HW address: 0x24
C prefix: CH1_SAT
C offset: 0x90
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- VAL[14:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.22. Channel 1 trigger threshold configuration register

HW prefix: fmc_adc_100ms_csr_ch1_trig_thres
HW address: 0x25
C prefix: CH1_TRIG_THRES
C offset: 0x94
31 30 29 28 27 26 25 24
HYST[15:8]
23 22 21 20 19 18 17 16
HYST[7:0]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.23. Channel 1 trigger delay

HW prefix: fmc_adc_100ms_csr_ch1_trig_dly
HW address: 0x26
C prefix: CH1_TRIG_DLY
C offset: 0x98
31 30 29 28 27 26 25 24
CH1_TRIG_DLY[31:24]
23 22 21 20 19 18 17 16
CH1_TRIG_DLY[23:16]
15 14 13 12 11 10 9 8
CH1_TRIG_DLY[15:8]
7 6 5 4 3 2 1 0
CH1_TRIG_DLY[7:0]

3.24. Channel 2 control register

HW prefix: fmc_adc_100ms_csr_ch2_ctl
HW address: 0x40
C prefix: CH2_CTL
C offset: 0x100
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- SSR[6:0]

3.25. Channel 2 status register

HW prefix: fmc_adc_100ms_csr_ch2_sta
HW address: 0x41
C prefix: CH2_STA
C offset: 0x104
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.26. Channel 2 gain calibration register

HW prefix: fmc_adc_100ms_csr_ch2_gain
HW address: 0x42
C prefix: CH2_GAIN
C offset: 0x108
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.27. Channel 2 offset calibration register

HW prefix: fmc_adc_100ms_csr_ch2_offset
HW address: 0x43
C prefix: CH2_OFFSET
C offset: 0x10c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.28. Channel 2 saturation register

HW prefix: fmc_adc_100ms_csr_ch2_sat
HW address: 0x44
C prefix: CH2_SAT
C offset: 0x110
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- VAL[14:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.29. Channel 2 trigger threshold configuration register

HW prefix: fmc_adc_100ms_csr_ch2_trig_thres
HW address: 0x45
C prefix: CH2_TRIG_THRES
C offset: 0x114
31 30 29 28 27 26 25 24
HYST[15:8]
23 22 21 20 19 18 17 16
HYST[7:0]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.30. Channel 2 trigger delay

HW prefix: fmc_adc_100ms_csr_ch2_trig_dly
HW address: 0x46
C prefix: CH2_TRIG_DLY
C offset: 0x118
31 30 29 28 27 26 25 24
CH2_TRIG_DLY[31:24]
23 22 21 20 19 18 17 16
CH2_TRIG_DLY[23:16]
15 14 13 12 11 10 9 8
CH2_TRIG_DLY[15:8]
7 6 5 4 3 2 1 0
CH2_TRIG_DLY[7:0]

3.31. Channel 3 control register

HW prefix: fmc_adc_100ms_csr_ch3_ctl
HW address: 0x60
C prefix: CH3_CTL
C offset: 0x180
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- SSR[6:0]

3.32. Channel 3 status register

HW prefix: fmc_adc_100ms_csr_ch3_sta
HW address: 0x61
C prefix: CH3_STA
C offset: 0x184
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.33. Channel 3 gain calibration register

HW prefix: fmc_adc_100ms_csr_ch3_gain
HW address: 0x62
C prefix: CH3_GAIN
C offset: 0x188
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.34. Channel 3 offset calibration register

HW prefix: fmc_adc_100ms_csr_ch3_offset
HW address: 0x63
C prefix: CH3_OFFSET
C offset: 0x18c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.35. Channel 3 saturation register

HW prefix: fmc_adc_100ms_csr_ch3_sat
HW address: 0x64
C prefix: CH3_SAT
C offset: 0x190
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- VAL[14:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.36. Channel 3 trigger threshold configuration register

HW prefix: fmc_adc_100ms_csr_ch3_trig_thres
HW address: 0x65
C prefix: CH3_TRIG_THRES
C offset: 0x194
31 30 29 28 27 26 25 24
HYST[15:8]
23 22 21 20 19 18 17 16
HYST[7:0]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.37. Channel 3 trigger delay

HW prefix: fmc_adc_100ms_csr_ch3_trig_dly
HW address: 0x66
C prefix: CH3_TRIG_DLY
C offset: 0x198
31 30 29 28 27 26 25 24
CH3_TRIG_DLY[31:24]
23 22 21 20 19 18 17 16
CH3_TRIG_DLY[23:16]
15 14 13 12 11 10 9 8
CH3_TRIG_DLY[15:8]
7 6 5 4 3 2 1 0
CH3_TRIG_DLY[7:0]

3.38. Channel 4 control register

HW prefix: fmc_adc_100ms_csr_ch4_ctl
HW address: 0x80
C prefix: CH4_CTL
C offset: 0x200
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- SSR[6:0]

3.39. Channel 4 status register

HW prefix: fmc_adc_100ms_csr_ch4_sta
HW address: 0x81
C prefix: CH4_STA
C offset: 0x204
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.40. Channel 4 gain calibration register

HW prefix: fmc_adc_100ms_csr_ch4_gain
HW address: 0x82
C prefix: CH4_GAIN
C offset: 0x208
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.41. Channel 4 offset calibration register

HW prefix: fmc_adc_100ms_csr_ch4_offset
HW address: 0x83
C prefix: CH4_OFFSET
C offset: 0x20c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.42. Channel 4 saturation register

HW prefix: fmc_adc_100ms_csr_ch4_sat
HW address: 0x84
C prefix: CH4_SAT
C offset: 0x210
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- VAL[14:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.43. Channel 4 trigger threshold configuration register

HW prefix: fmc_adc_100ms_csr_ch4_trig_thres
HW address: 0x85
C prefix: CH4_TRIG_THRES
C offset: 0x214
31 30 29 28 27 26 25 24
HYST[15:8]
23 22 21 20 19 18 17 16
HYST[7:0]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.44. Channel 4 trigger delay

HW prefix: fmc_adc_100ms_csr_ch4_trig_dly
HW address: 0x86
C prefix: CH4_TRIG_DLY
C offset: 0x218
31 30 29 28 27 26 25 24
CH4_TRIG_DLY[31:24]
23 22 21 20 19 18 17 16
CH4_TRIG_DLY[23:16]
15 14 13 12 11 10 9 8
CH4_TRIG_DLY[15:8]
7 6 5 4 3 2 1 0
CH4_TRIG_DLY[7:0]