dma_eic

GN4124 DMA enhanced interrupt controller

Enhanced interrrupt controller for GN4124 DMA.

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Interrupt disable register
3.2. Interrupt enable register
3.3. Interrupt mask register
3.4. Interrupt status register
5. Interrupts
5.1. DMA done interrupt
5.2. DMA error interrupt

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Interrupt disable register dma_eic_eic_idr EIC_IDR
0x1 REG Interrupt enable register dma_eic_eic_ier EIC_IER
0x2 REG Interrupt mask register dma_eic_eic_imr EIC_IMR
0x3 REG Interrupt status register dma_eic_eic_isr EIC_ISR

2. HDL symbol

rst_n_i DMA done interrupt:
clk_sys_i irq_dma_done_i
wb_adr_i[1:0]  
wb_dat_i[31:0] DMA error interrupt:
wb_dat_o[31:0] irq_dma_error_i
wb_cyc_i
wb_sel_i[3:0]
wb_stb_i
wb_we_i
wb_ack_o
wb_stall_o
wb_int_o

3. Register description

3.1. Interrupt disable register

HW prefix: dma_eic_eic_idr
HW address: 0x0
C prefix: EIC_IDR
C offset: 0x0

Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DMA_ERROR DMA_DONE

3.2. Interrupt enable register

HW prefix: dma_eic_eic_ier
HW address: 0x1
C prefix: EIC_IER
C offset: 0x4

Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DMA_ERROR DMA_DONE

3.3. Interrupt mask register

HW prefix: dma_eic_eic_imr
HW address: 0x2
C prefix: EIC_IMR
C offset: 0x8

Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DMA_ERROR DMA_DONE

3.4. Interrupt status register

HW prefix: dma_eic_eic_isr
HW address: 0x3
C prefix: EIC_ISR
C offset: 0xc

Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DMA_ERROR DMA_DONE

5. Interrupts

5.1. DMA done interrupt

HW prefix: dma_eic_dma_done
C prefix: DMA_DONE
Trigger: rising edge

DMA done interrupt line (rising edge sensitive).

5.2. DMA error interrupt

HW prefix: dma_eic_dma_error
C prefix: DMA_ERROR
Trigger: rising edge

DMA error interrupt line (rising edge sensitive).