Wishbone slave for control and status registers related to the SVEC FMC carrier
H/W Address | Type | Name | VHDL/Verilog prefix | C prefix |
---|---|---|---|---|
0x0 | REG | Carrier type and PCB version | carrier_csr_carrier | CARRIER |
0x1 | REG | Status | carrier_csr_stat | STAT |
0x2 | REG | Control | carrier_csr_ctrl | CTRL |
0x3 | REG | Reset Register | carrier_csr_rst | RST |
→ | rst_n_i | Carrier type and PCB version: | ||
→ | clk_sys_i | carrier_csr_carrier_pcb_rev_i[4:0] | ⇐ | |
⇒ | wb_adr_i[1:0] | carrier_csr_carrier_reserved_i[10:0] | ⇐ | |
⇒ | wb_dat_i[31:0] | carrier_csr_carrier_type_i[15:0] | ⇐ | |
⇐ | wb_dat_o[31:0] | |||
→ | wb_cyc_i | Status: | ||
⇒ | wb_sel_i[3:0] | carrier_csr_stat_fmc0_pres_i | ← | |
→ | wb_stb_i | carrier_csr_stat_fmc1_pres_i | ← | |
→ | wb_we_i | carrier_csr_stat_sys_pll_lck_i | ← | |
← | wb_ack_o | carrier_csr_stat_ddr0_cal_done_i | ← | |
← | wb_stall_o | carrier_csr_stat_ddr1_cal_done_i | ← | |
Control: | ||||
carrier_csr_ctrl_fp_leds_man_o[15:0] | ⇒ | |||
Reset Register: | ||||
carrier_csr_rst_fmc0_o | → | |||
carrier_csr_rst_fmc1_o | → |
HW prefix: | carrier_csr_carrier |
HW address: | 0x0 |
C prefix: | CARRIER |
C offset: | 0x0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
TYPE[15:8] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
TYPE[7:0] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
RESERVED[10:3] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED[2:0] | PCB_REV[4:0] |
HW prefix: | carrier_csr_stat |
HW address: | 0x1 |
C prefix: | STAT |
C offset: | 0x4 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | DDR1_CAL_DONE | DDR0_CAL_DONE | SYS_PLL_LCK | FMC1_PRES | FMC0_PRES |
HW prefix: | carrier_csr_ctrl |
HW address: | 0x2 |
C prefix: | CTRL |
C offset: | 0x8 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
FP_LEDS_MAN[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
FP_LEDS_MAN[7:0] |
HW prefix: | carrier_csr_rst |
HW address: | 0x3 |
C prefix: | RST |
C offset: | 0xc |
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | FMC1 | FMC0 |