# irq_controller

### Interrupt controller

Fmc-adc interrrupt controller for SVEC.

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Interrupt disable register
3.2. Interrupt enable register
3.3. Interrupt mask register
3.4. Interrupt status register
5. Interrupts
5.1. FMC slot 1 trigger interrupt
5.2. FMC slot 1 end of acquisition interrupt
5.3. FMC slot 2 trigger interrupt
5.4. FMC slot 2 end of acquisition interrupt

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Interrupt disable register | irq_ctrl_eic_idr | EIC_IDR
0x1 | REG | Interrupt enable register | irq_ctrl_eic_ier | EIC_IER
0x2 | REG | Interrupt mask register | irq_ctrl_eic_imr | EIC_IMR
0x3 | REG | Interrupt status register | irq_ctrl_eic_isr | EIC_ISR

### 2. HDL symbol

→ | rst_n_i |  | FMC slot 1 trigger interrupt: |
→ | clk_sys_i |  | irq_fmc0_trig_i | ←
⇒ | wb_adr_i[1:0] |  |  |
⇒ | wb_dat_i[31:0] |  | FMC slot 1 end of acquisition interrupt: |
⇐ | wb_dat_o[31:0] |  | irq_fmc0_acq_end_i | ←
→ | wb_cyc_i |  |  |
⇒ | wb_sel_i[3:0] |  | FMC slot 2 trigger interrupt: |
→ | wb_stb_i |  | irq_fmc1_trig_i | ←
→ | wb_we_i |  |  |
← | wb_ack_o |  | FMC slot 2 end of acquisition interrupt: |
← | wb_stall_o |  | irq_fmc1_acq_end_i | ←
← | wb_int_o |  |  |

### 3. Register description

### 3.1. Interrupt disable register

HW prefix: | irq_ctrl_eic_idr
HW address: | 0x0
C prefix: | EIC_IDR
C offset: | 0x0

Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | FMC1_ACQ_END | FMC1_TRIG | FMC0_ACQ_END | FMC0_TRIG

- FMC0_TRIG [write-only]: FMC slot 1 trigger interrupt
  write 1: disable interrupt 'FMC slot 1 trigger interrupt'
  write 0: no effect
- FMC0_ACQ_END [write-only]: FMC slot 1 end of acquisition interrupt
  write 1: disable interrupt 'FMC slot 1 end of acquisition interrupt'
  write 0: no effect
- FMC1_TRIG [write-only]: FMC slot 2 trigger interrupt
  write 1: disable interrupt 'FMC slot 2 trigger interrupt'
  write 0: no effect
- FMC1_ACQ_END [write-only]: FMC slot 2 end of acquisition interrupt
  write 1: disable interrupt 'FMC slot 2 end of acquisition interrupt'
  write 0: no effect

### 3.2. Interrupt enable register

HW prefix: | irq_ctrl_eic_ier
HW address: | 0x1
C prefix: | EIC_IER
C offset: | 0x4

Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | FMC1_ACQ_END | FMC1_TRIG | FMC0_ACQ_END | FMC0_TRIG

- FMC0_TRIG [write-only]: FMC slot 1 trigger interrupt
  write 1: enable interrupt 'FMC slot 1 trigger interrupt'
  write 0: no effect
- FMC0_ACQ_END [write-only]: FMC slot 1 end of acquisition interrupt
  write 1: enable interrupt 'FMC slot 1 end of acquisition interrupt'
  write 0: no effect
- FMC1_TRIG [write-only]: FMC slot 2 trigger interrupt
  write 1: enable interrupt 'FMC slot 2 trigger interrupt'
  write 0: no effect
- FMC1_ACQ_END [write-only]: FMC slot 2 end of acquisition interrupt
  write 1: enable interrupt 'FMC slot 2 end of acquisition interrupt'
  write 0: no effect

### 3.3. Interrupt mask register

HW prefix: | irq_ctrl_eic_imr
HW address: | 0x2
C prefix: | EIC_IMR
C offset: | 0x8

Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | FMC1_ACQ_END | FMC1_TRIG | FMC0_ACQ_END | FMC0_TRIG

- FMC0_TRIG [read-only]: FMC slot 1 trigger interrupt
  read 1: interrupt 'FMC slot 1 trigger interrupt' is enabled
  read 0: interrupt 'FMC slot 1 trigger interrupt' is disabled
- FMC0_ACQ_END [read-only]: FMC slot 1 end of acquisition interrupt
  read 1: interrupt 'FMC slot 1 end of acquisition interrupt' is enabled
  read 0: interrupt 'FMC slot 1 end of acquisition interrupt' is disabled
- FMC1_TRIG [read-only]: FMC slot 2 trigger interrupt
  read 1: interrupt 'FMC slot 2 trigger interrupt' is enabled
  read 0: interrupt 'FMC slot 2 trigger interrupt' is disabled
- FMC1_ACQ_END [read-only]: FMC slot 2 end of acquisition interrupt
  read 1: interrupt 'FMC slot 2 end of acquisition interrupt' is enabled
  read 0: interrupt 'FMC slot 2 end of acquisition interrupt' is disabled

### 3.4. Interrupt status register

HW prefix: | irq_ctrl_eic_isr
HW address: | 0x3
C prefix: | EIC_ISR
C offset: | 0xc

Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | FMC1_ACQ_END | FMC1_TRIG | FMC0_ACQ_END | FMC0_TRIG

- FMC0_TRIG [read/write]: FMC slot 1 trigger interrupt
  read 1: interrupt 'FMC slot 1 trigger interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'FMC slot 1 trigger interrupt'
  write 0: no effect
- FMC0_ACQ_END [read/write]: FMC slot 1 end of acquisition interrupt
  read 1: interrupt 'FMC slot 1 end of acquisition interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'FMC slot 1 end of acquisition interrupt'
  write 0: no effect
- FMC1_TRIG [read/write]: FMC slot 2 trigger interrupt
  read 1: interrupt 'FMC slot 2 trigger interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'FMC slot 2 trigger interrupt'
  write 0: no effect
- FMC1_ACQ_END [read/write]: FMC slot 2 end of acquisition interrupt
  read 1: interrupt 'FMC slot 2 end of acquisition interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'FMC slot 2 end of acquisition interrupt'
  write 0: no effect

### 5. Interrupts

### 5.1. FMC slot 1 trigger interrupt

HW prefix: | irq_ctrl_fmc0_trig
C prefix: | FMC0_TRIG
Trigger: | rising edge

FMC slot 1 trigger interrupt line (rising edge sensitive).

### 5.2. FMC slot 1 end of acquisition interrupt

HW prefix: | irq_ctrl_fmc0_acq_end
C prefix: | FMC0_ACQ_END
Trigger: | rising edge

FMC slot 1 end of acquisition interrupt line (rising edge sensitive).

### 5.3. FMC slot 2 trigger interrupt

HW prefix: | irq_ctrl_fmc1_trig
C prefix: | FMC1_TRIG
Trigger: | rising edge

FMC slot 2 trigger interrupt line (rising edge sensitive).

### 5.4. FMC slot 2 end of acquisition interrupt

HW prefix: | irq_ctrl_fmc1_acq_end
C prefix: | FMC1_ACQ_END
Trigger: | rising edge

FMC slot 2 end of acquisition interrupt line (rising edge sensitive).