alt_trigin
FMC ADC alt trigger out registers
| HW address |
Type |
Name |
HDL prefix |
C prefix |
| 0x00 |
REG |
version |
version |
version |
| 0x04 |
REG |
ctrl |
ctrl |
ctrl |
| 0x08 |
REG |
seconds |
seconds |
seconds |
| 0x10 |
REG |
cycles |
cycles |
cycles |
| HW prefix: | version |
| HW address: | 0x0 |
| C prefix: | version |
| C block offset: | 0x0 |
Core version
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| version[31:24] |
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| version[23:16] |
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| version[15:8] |
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| version[7:0] |
-
version
[ro]: Core version
| HW prefix: | ctrl |
| HW address: | 0x4 |
| C prefix: | ctrl |
| C block offset: | 0x4 |
Control register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| - |
- |
- |
- |
- |
- |
- |
- |
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| - |
- |
- |
- |
- |
- |
- |
- |
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| - |
- |
- |
- |
- |
- |
- |
- |
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| - |
- |
- |
- |
- |
- |
- |
enable |
-
enable
[rw]: Enable trigger, cleared when triggered
| HW prefix: | seconds |
| HW address: | 0x8 |
| C prefix: | seconds |
| C block offset: | 0x8 |
Time (seconds) to trigger
| 63 |
62 |
61 |
60 |
59 |
58 |
57 |
56 |
| seconds[63:56] |
| 55 |
54 |
53 |
52 |
51 |
50 |
49 |
48 |
| seconds[55:48] |
| 47 |
46 |
45 |
44 |
43 |
42 |
41 |
40 |
| seconds[47:40] |
| 39 |
38 |
37 |
36 |
35 |
34 |
33 |
32 |
| seconds[39:32] |
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| seconds[31:24] |
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| seconds[23:16] |
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| seconds[15:8] |
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| seconds[7:0] |
-
seconds
[rw]: Time (seconds) to trigger
| HW prefix: | cycles |
| HW address: | 0x10 |
| C prefix: | cycles |
| C block offset: | 0x10 |
Time (cycles) to trigger
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| cycles[31:24] |
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| cycles[23:16] |
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| cycles[15:8] |
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| cycles[7:0] |
-
cycles
[rw]: Time (cycles) to trigger