wb_slave_vic
Vectored Interrupt Controller (VIC)
Module implementing a 2 to 32-input prioritized interrupt controller with internal interrupt vector storage support.
Contents:
1. Memory map summary
2. HDL symbol
3. Register description
3.1. VIC Control Register
3.2. Raw Interrupt Status Register
3.3. Interrupt Enable Register
3.4. Interrupt Disable Register
3.5. Interrupt Mask Register
3.6. Vector Address Register
3.7. Software Interrupt Register
3.8. End Of Interrupt Acknowledge Register
4. Memory blocks
4.1. Interrupt Vector Table
|
→
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rst_n_i
|
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VIC Control Register:
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|
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→
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clk_sys_i
|
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vic_ctl_enable_o
|
→
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⇒
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wb_adr_i[5:0]
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vic_ctl_pol_o
|
→
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⇒
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wb_dat_i[31:0]
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vic_ctl_emu_edge_o
|
→
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⇐
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wb_dat_o[31:0]
|
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vic_ctl_emu_len_o[15:0]
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⇒
|
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→
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wb_cyc_i
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|
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|
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⇒
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wb_sel_i[3:0]
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Raw Interrupt Status Register:
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|
|
→
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wb_stb_i
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vic_risr_i[31:0]
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⇐
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→
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wb_we_i
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|
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←
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wb_ack_o
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|
Interrupt Enable Register:
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|
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←
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wb_stall_o
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vic_ier_o[31:0]
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⇒
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|
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vic_ier_wr_o
|
→
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|
|
|
|
|
|
|
|
|
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Interrupt Disable Register:
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vic_idr_o[31:0]
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⇒
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vic_idr_wr_o
|
→
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|
|
|
|
|
|
|
|
|
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Interrupt Mask Register:
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vic_imr_i[31:0]
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⇐
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|
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|
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Vector Address Register:
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vic_var_i[31:0]
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⇐
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|
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Software Interrupt Register:
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vic_swir_o[31:0]
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⇒
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vic_swir_wr_o
|
→
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|
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End Of Interrupt Acknowledge Register:
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vic_eoir_o[31:0]
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⇒
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vic_eoir_wr_o
|
→
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|
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Interrupt Vector Table:
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vic_ivt_ram_addr_i[4:0]
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⇐
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vic_ivt_ram_data_o[31:0]
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⇒
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vic_ivt_ram_rd_i
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←
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HW prefix:
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vic_ctl
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HW address:
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0x0
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C prefix:
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CTL
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C offset:
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0x0
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31
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30
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29
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28
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27
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26
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25
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24
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-
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-
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-
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-
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-
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-
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-
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-
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23
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22
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21
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20
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19
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18
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17
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16
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-
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-
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-
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-
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-
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EMU_LEN[15:13]
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15
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14
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13
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12
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11
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10
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9
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8
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EMU_LEN[12:5]
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7
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6
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5
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4
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3
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2
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1
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0
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EMU_LEN[4:0]
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EMU_EDGE
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POL
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ENABLE
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-
ENABLE
[read/write]: VIC Enable
- 1: enables VIC operation
- 0: disables VIC operation
-
POL
[read/write]: VIC output polarity
- 1: IRQ output is active high
- 0: IRQ output is active low
-
EMU_EDGE
[read/write]: Emulate Edge sensitive output
- 1: Forces a low pulse of EMU_LEN clock cycles at each write to EOIR. Useful for edge-only IRQ controllers such as Gennum.
- 0: Normal IRQ master line behavior
-
EMU_LEN
[read/write]: Emulated Edge pulse timer
Length of the delay (in clk_sys_i cycles) between write to EOIR and re-assertion of irq_master_o.
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HW prefix:
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vic_risr
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HW address:
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0x1
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C prefix:
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RISR
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C offset:
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0x4
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31
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30
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29
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28
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27
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26
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25
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24
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RISR[31:24]
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23
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22
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21
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20
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19
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18
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17
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16
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RISR[23:16]
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15
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14
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13
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12
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11
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10
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9
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8
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RISR[15:8]
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7
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6
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5
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4
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3
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2
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1
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0
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RISR[7:0]
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|
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-
RISR
[read-only]: Raw interrupt status
Each bit reflects the current state of corresponding IRQ input line.
- read 1: interrupt line is currently active
- read 0: interrupt line is inactive
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HW prefix:
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vic_ier
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HW address:
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0x2
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C prefix:
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IER
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C offset:
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0x8
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31
|
30
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29
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28
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27
|
26
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25
|
24
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IER[31:24]
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23
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22
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21
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20
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19
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18
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17
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16
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IER[23:16]
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15
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14
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13
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12
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11
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10
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9
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8
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IER[15:8]
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-
IER
[write-only]: Enable IRQ
- write 1: enables interrupt associated with written bit
- write 0: no effect
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HW prefix:
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vic_idr
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HW address:
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0x3
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C prefix:
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IDR
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C offset:
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0xc
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31
|
30
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29
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28
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27
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26
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25
|
24
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IDR[31:24]
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23
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22
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21
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20
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19
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18
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17
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16
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IDR[23:16]
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15
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14
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13
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12
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11
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10
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9
|
8
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IDR[15:8]
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|
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|
-
IDR
[write-only]: Disable IRQ
- write 1: enables interrupt associated with written bit
- write 0: no effect
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HW prefix:
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vic_imr
|
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HW address:
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0x4
|
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C prefix:
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IMR
|
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C offset:
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0x10
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31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
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IMR[31:24]
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|
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23
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22
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21
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20
|
19
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18
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17
|
16
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IMR[23:16]
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15
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14
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13
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12
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11
|
10
|
9
|
8
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IMR[15:8]
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|
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-
IMR
[read-only]: IRQ disabled/enabled
- read 1: interrupt associated with read bit is enabled
- read 0: interrupt is disabled
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HW prefix:
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vic_var
|
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HW address:
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0x5
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C prefix:
|
VAR
|
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C offset:
|
0x14
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
|
VAR[31:24]
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23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
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VAR[23:16]
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15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
|
VAR[15:8]
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|
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|
-
VAR
[read-only]: Vector Address
Address of pending interrupt vector, read from Interrupt Vector Table
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HW prefix:
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vic_swir
|
|
HW address:
|
0x6
|
|
C prefix:
|
SWIR
|
|
C offset:
|
0x18
|
Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
|
SWIR[31:24]
|
|
|
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|
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|
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23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
|
SWIR[23:16]
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|
|
|
|
|
|
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15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
|
SWIR[15:8]
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|
|
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|
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7
|
6
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5
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4
|
3
|
2
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1
|
0
|
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SWIR[7:0]
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|
|
|
|
|
|
|
-
SWIR
[write-only]: SWI interrupt mask
|
HW prefix:
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vic_eoir
|
|
HW address:
|
0x7
|
|
C prefix:
|
EOIR
|
|
C offset:
|
0x1c
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
|
EOIR[31:24]
|
|
|
|
|
|
|
|
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23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
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EOIR[23:16]
|
|
|
|
|
|
|
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15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
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EOIR[15:8]
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|
|
|
|
|
|
|
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7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
|
EOIR[7:0]
|
|
|
|
|
|
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|
-
EOIR
[write-only]: End of Interrupt
Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.
|
HW prefix:
|
vic_ivt_ram
|
|
HW address:
|
0x20
|
|
C prefix:
|
IVT_RAM
|
|
C offset:
|
0x80
|
|
Size:
|
32 32-bit words
|
|
Data width:
|
32
|
|
Access (bus):
|
read/write
|
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Access (device):
|
read-only
|
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Mirrored:
|
no
|
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Byte-addressable:
|
no
|
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Peripheral port:
|
bus-synchronous
|
|
⇒
|
vic_ivt_ram_addr_i[4:0]
|
|
|
|
|
⇐
|
vic_ivt_ram_data_o[31:0]
|
|
|
|
|
→
|
vic_ivt_ram_rd_i
|
|
|
|
Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register. The contents of this table can be pre-initialized during synthesis through g_init_vectors generic parameter. This is used to auto-enumerate interrupts in SDB-based designs.