--------------------------------------------------------------------------------
Release 13.3 Trace  (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

/opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 3 -n 3
-fastpaths -xml svec_top_fmc_adc_100Ms.twx svec_top_fmc_adc_100Ms.ncd -o
svec_top_fmc_adc_100Ms.twr svec_top_fmc_adc_100Ms.pcf

Design file:              svec_top_fmc_adc_100Ms.ncd
Physical constraint file: svec_top_fmc_adc_100Ms.pcf
Device,package,speed:     xc6slx150t,fgg900,C,-3 (PRODUCTION 1.20 2011-10-03)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns 
HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is  20.000ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.630ns (max period limit - period)
  Period: 50.000ns
  Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKIN)
  Physical resource: cmp_sys_clk_pll/PLL_ADV/CLKIN1
  Logical resource: cmp_sys_clk_pll/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y1.CLKIN1
  Clock network: cmp_sys_clk_pll/PLL_ADV_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 2.630ns (max period limit - period)
  Period: 50.000ns
  Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKFB)
  Physical resource: cmp_sys_clk_pll/PLL_ADV/CLKFBOUT
  Logical resource: cmp_sys_clk_pll/PLL_ADV/CLKFBOUT
  Location pin: PLL_ADV_X0Y1.CLKFBOUT
  Clock network: sys_clk_fb
--------------------------------------------------------------------------------
Slack: 7.075ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_sys_clk_pll/PLL_ADV/CLKOUT0
  Logical resource: cmp_sys_clk_pll/PLL_ADV/CLKOUT0
  Location pin: PLL_ADV_X0Y1.CLKOUT0
  Clock network: sys_clk_125_buf
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_adc0_dco_n_i = PERIOD TIMEGRP "adc0_dco_n_i" 2 ns HIGH 
50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   0.925ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_adc0_dco_n_i = PERIOD TIMEGRP "adc0_dco_n_i" 2 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.075ns (period - min period limit)
  Period: 2.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_dco_bufio/I
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_dco_bufio/I
  Location pin: BUFIO2_X2Y28.I
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dco_clk_buf
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_adc1_dco_n_i = PERIOD TIMEGRP "adc1_dco_n_i" 2 ns HIGH 
50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   0.925ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_adc1_dco_n_i = PERIOD TIMEGRP "adc1_dco_n_i" 2 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.075ns (period - min period limit)
  Period: 2.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_dco_bufio/I
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_dco_bufio/I
  Location pin: BUFIO2_X1Y6.I
  Clock network: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/dco_clk_buf
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_sys_clk_62_5_buf = PERIOD TIMEGRP "sys_clk_62_5_buf" 
TS_clk_20m_vcxo_i /         3.125 HIGH 50%;

 1756234 paths analyzed, 10504 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  15.723ns.
--------------------------------------------------------------------------------

Paths for end point cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0 (SLICE_X31Y41.A5), 121 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.277ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0 (FF)
  Requirement:          16.000ns
  Data Path Delay:      15.587ns (Levels of Logic = 5)
  Clock Path Skew:      -0.022ns (0.786 - 0.808)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y57.BQ      Tcko                  0.447   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<3>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1
    SLICE_X68Y7.D3       net (fanout=137)      8.482   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<1>
    SLICE_X68Y7.D        Tilo                  0.203   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
    SLICE_X56Y9.C2       net (fanout=1)        1.265   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
    SLICE_X56Y9.C        Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_112
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X35Y16.A3      net (fanout=2)        1.733   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X35Y16.A       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_14
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o12
    SLICE_X31Y41.B1      net (fanout=1)        2.226   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o11
    SLICE_X31Y41.B       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
    SLICE_X31Y41.A5      net (fanout=1)        0.187   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o13
    SLICE_X31Y41.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o18
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    -------------------------------------------------  ---------------------------
    Total                                     15.587ns (1.694ns logic, 13.893ns route)
                                                       (10.9% logic, 89.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.973ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_0 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0 (FF)
  Requirement:          16.000ns
  Data Path Delay:      14.891ns (Levels of Logic = 5)
  Clock Path Skew:      -0.022ns (0.786 - 0.808)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_0 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y57.AQ      Tcko                  0.447   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<3>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_0
    SLICE_X68Y7.D4       net (fanout=137)      7.786   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<0>
    SLICE_X68Y7.D        Tilo                  0.203   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
    SLICE_X56Y9.C2       net (fanout=1)        1.265   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
    SLICE_X56Y9.C        Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_112
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X35Y16.A3      net (fanout=2)        1.733   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X35Y16.A       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_14
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o12
    SLICE_X31Y41.B1      net (fanout=1)        2.226   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o11
    SLICE_X31Y41.B       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
    SLICE_X31Y41.A5      net (fanout=1)        0.187   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o13
    SLICE_X31Y41.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o18
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    -------------------------------------------------  ---------------------------
    Total                                     14.891ns (1.694ns logic, 13.197ns route)
                                                       (11.4% logic, 88.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.891ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0 (FF)
  Requirement:          16.000ns
  Data Path Delay:      13.973ns (Levels of Logic = 5)
  Clock Path Skew:      -0.022ns (0.786 - 0.808)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y57.BQ      Tcko                  0.447   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<3>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1
    SLICE_X63Y9.A4       net (fanout=137)      7.514   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<1>
    SLICE_X63Y9.A        Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_13
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_13
    SLICE_X56Y9.C6       net (fanout=1)        0.563   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_13
    SLICE_X56Y9.C        Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_112
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X35Y16.A3      net (fanout=2)        1.733   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X35Y16.A       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_14
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o12
    SLICE_X31Y41.B1      net (fanout=1)        2.226   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o11
    SLICE_X31Y41.B       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
    SLICE_X31Y41.A5      net (fanout=1)        0.187   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o13
    SLICE_X31Y41.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o18
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    -------------------------------------------------  ---------------------------
    Total                                     13.973ns (1.750ns logic, 12.223ns route)
                                                       (12.5% logic, 87.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22 (SLICE_X15Y58.A3), 6998 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.426ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_25 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22 (FF)
  Requirement:          16.000ns
  Data Path Delay:      15.293ns (Levels of Logic = 8)
  Clock Path Skew:      -0.167ns (0.786 - 0.953)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_25 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y81.BQ      Tcko                  0.391   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_25
    SLICE_X1Y50.A4       net (fanout=8)        4.053   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<25>
    SLICE_X1Y50.A        Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[2][31]_and_139_OUT<17>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[2][31]_and_139_OUT<17>1
    SLICE_X2Y53.B6       net (fanout=2)        0.568   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[2][31]_and_139_OUT<17>
    SLICE_X2Y53.DMUX     Topbd                 0.574   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[2][31]_s_locAddr[31]_equal_141_o
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[2][31]_s_locAddr[31]_equal_141_o_lut<5>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[2][31]_s_locAddr[31]_equal_141_o_cy<7>
    SLICE_X29Y56.C3      net (fanout=7)        2.642   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[2][31]_s_locAddr[31]_equal_141_o
    SLICE_X29Y56.C       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2412
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[2][31]_s_isprev_func64[2]_AND_259_o1101
    SLICE_X32Y56.A1      net (fanout=4)        0.701   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[2][31]_s_isprev_func64[2]_AND_259_o110
    SLICE_X32Y56.A       Tilo                  0.205   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[2].cmp_offset_gain_calibr/product<7>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124_SW0
    SLICE_X22Y60.C1      net (fanout=1)        1.239   N182
    SLICE_X22Y60.C       Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1215
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124
    SLICE_X32Y57.B4      net (fanout=10)       1.031   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124
    SLICE_X32Y57.B       Tilo                  0.205   N1128
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2461
    SLICE_X28Y62.C3      net (fanout=8)        1.092   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT246
    SLICE_X28Y62.C       Tilo                  0.205   N1120
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT455_SW0
    SLICE_X15Y58.A3      net (fanout=1)        1.343   N1116
    SLICE_X15Y58.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<23>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT455
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
    -------------------------------------------------  ---------------------------
    Total                                     15.293ns (2.624ns logic, 12.669ns route)
                                                       (17.2% logic, 82.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.522ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_25 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22 (FF)
  Requirement:          16.000ns
  Data Path Delay:      15.197ns (Levels of Logic = 8)
  Clock Path Skew:      -0.167ns (0.786 - 0.953)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_25 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y81.BQ      Tcko                  0.391   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_25
    SLICE_X6Y50.A1       net (fanout=8)        3.616   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<25>
    SLICE_X6Y50.A        Tilo                  0.203   cmp_vme_core/U_Wrapped_VME/Inst_VME_CR_CSR_Space/s_CSRarray_234<4>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[3][31]_and_113_OUT<17>1
    SLICE_X4Y47.B4       net (fanout=2)        1.057   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[3][31]_and_113_OUT<17>
    SLICE_X4Y47.DMUX     Topbd                 0.534   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_lut<5>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_cy<7>
    SLICE_X9Y51.C5       net (fanout=5)        0.891   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o
    SLICE_X9Y51.C        Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[2][0]_s_FUNC_ADEM_64[2][63]_AND_258_o641
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[3][31]_s_isprev_func64[3]_AND_254_o1101
    SLICE_X32Y56.A2      net (fanout=5)        2.400   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[3][31]_s_isprev_func64[3]_AND_254_o110
    SLICE_X32Y56.A       Tilo                  0.205   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[2].cmp_offset_gain_calibr/product<7>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124_SW0
    SLICE_X22Y60.C1      net (fanout=1)        1.239   N182
    SLICE_X22Y60.C       Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1215
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124
    SLICE_X32Y57.B4      net (fanout=10)       1.031   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124
    SLICE_X32Y57.B       Tilo                  0.205   N1128
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2461
    SLICE_X28Y62.C3      net (fanout=8)        1.092   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT246
    SLICE_X28Y62.C       Tilo                  0.205   N1120
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT455_SW0
    SLICE_X15Y58.A3      net (fanout=1)        1.343   N1116
    SLICE_X15Y58.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<23>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT455
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
    -------------------------------------------------  ---------------------------
    Total                                     15.197ns (2.528ns logic, 12.669ns route)
                                                       (16.6% logic, 83.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.639ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_24 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22 (FF)
  Requirement:          16.000ns
  Data Path Delay:      15.080ns (Levels of Logic = 8)
  Clock Path Skew:      -0.167ns (0.786 - 0.953)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_24 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y81.AQ      Tcko                  0.391   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<27>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr_24
    SLICE_X7Y52.A5       net (fanout=8)        3.613   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_locAddr<24>
    SLICE_X7Y52.A        Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[23]_s_FUNC_ADEM[2][23]_and_145_OUT<8>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[3][31]_and_113_OUT<16>1
    SLICE_X4Y47.B2       net (fanout=2)        0.887   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_locAddr[31]_s_FUNC_ADEM[3][31]_and_113_OUT<16>
    SLICE_X4Y47.DMUX     Topbd                 0.534   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_lut<5>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mcompar_s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o_cy<7>
    SLICE_X9Y51.C5       net (fanout=5)        0.891   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADER[3][31]_s_locAddr[31]_equal_115_o
    SLICE_X9Y51.C        Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[2][0]_s_FUNC_ADEM_64[2][63]_AND_258_o641
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[3][31]_s_isprev_func64[3]_AND_254_o1101
    SLICE_X32Y56.A2      net (fanout=5)        2.400   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/s_FUNC_ADEM[3][31]_s_isprev_func64[3]_AND_254_o110
    SLICE_X32Y56.A       Tilo                  0.205   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[2].cmp_offset_gain_calibr/product<7>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124_SW0
    SLICE_X22Y60.C1      net (fanout=1)        1.239   N182
    SLICE_X22Y60.C       Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT1215
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124
    SLICE_X32Y57.B4      net (fanout=10)       1.031   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT124
    SLICE_X32Y57.B       Tilo                  0.205   N1128
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT2461
    SLICE_X28Y62.C3      net (fanout=8)        1.092   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT246
    SLICE_X28Y62.C       Tilo                  0.205   N1120
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT455_SW0
    SLICE_X15Y58.A3      net (fanout=1)        1.343   N1116
    SLICE_X15Y58.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr<23>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Mmux_Nx_Base_Addr[63]_AddrWidth[1]_mux_211_OUT455
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Funct_Match/Nx_Base_Addr_22
    -------------------------------------------------  ---------------------------
    Total                                     15.080ns (2.584ns logic, 12.496ns route)
                                                       (17.1% logic, 82.9% route)

--------------------------------------------------------------------------------

Paths for end point cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0 (SLICE_X31Y41.A1), 106 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.428ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0 (FF)
  Requirement:          16.000ns
  Data Path Delay:      15.436ns (Levels of Logic = 4)
  Clock Path Skew:      -0.022ns (0.786 - 0.808)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y57.BQ      Tcko                  0.447   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<3>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1
    SLICE_X68Y7.D3       net (fanout=137)      8.482   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<1>
    SLICE_X68Y7.D        Tilo                  0.203   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
    SLICE_X56Y9.C2       net (fanout=1)        1.265   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
    SLICE_X56Y9.C        Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_112
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X31Y16.B1      net (fanout=2)        2.324   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X31Y16.B       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o15
    SLICE_X31Y41.A1      net (fanout=1)        1.930   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
    SLICE_X31Y41.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o18
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    -------------------------------------------------  ---------------------------
    Total                                     15.436ns (1.435ns logic, 14.001ns route)
                                                       (9.3% logic, 90.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.124ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_0 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0 (FF)
  Requirement:          16.000ns
  Data Path Delay:      14.740ns (Levels of Logic = 4)
  Clock Path Skew:      -0.022ns (0.786 - 0.808)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_0 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y57.AQ      Tcko                  0.447   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<3>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_0
    SLICE_X68Y7.D4       net (fanout=137)      7.786   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<0>
    SLICE_X68Y7.D        Tilo                  0.203   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
    SLICE_X56Y9.C2       net (fanout=1)        1.265   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_121
    SLICE_X56Y9.C        Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_112
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X31Y16.B1      net (fanout=2)        2.324   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X31Y16.B       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o15
    SLICE_X31Y41.A1      net (fanout=1)        1.930   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
    SLICE_X31Y41.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o18
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    -------------------------------------------------  ---------------------------
    Total                                     14.740ns (1.435ns logic, 13.305ns route)
                                                       (9.7% logic, 90.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     2.042ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1 (FF)
  Destination:          cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0 (FF)
  Requirement:          16.000ns
  Data Path Delay:      13.822ns (Levels of Logic = 4)
  Clock Path Skew:      -0.022ns (0.786 - 0.808)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.114ns

  Clock Uncertainty:          0.114ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1 to cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y57.BQ      Tcko                  0.447   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<3>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched_1
    SLICE_X63Y9.A4       net (fanout=137)      7.514   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/s_AMlatched<1>
    SLICE_X63Y9.A        Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_13
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_13
    SLICE_X56Y9.C6       net (fanout=1)        0.563   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_13
    SLICE_X56Y9.C        Tilo                  0.204   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_112
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X31Y16.B1      net (fanout=2)        2.324   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match<0>_7
    SLICE_X31Y16.B       Tilo                  0.259   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o15
    SLICE_X31Y41.A1      net (fanout=1)        1.930   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o14
    SLICE_X31Y41.CLK     Tas                   0.322   cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch<1>
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/Mmux_s_amcap_match[0]_GND_27_o_MUX_1285_o18
                                                       cmp_vme_core/U_Wrapped_VME/Inst_VME_bus/Inst_Access_Decode/Inst_Am_Match/AmMatch_0
    -------------------------------------------------  ---------------------------
    Total                                     13.822ns (1.491ns logic, 12.331ns route)
                                                       (10.8% logic, 89.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_sys_clk_62_5_buf = PERIOD TIMEGRP "sys_clk_62_5_buf" TS_clk_20m_vcxo_i /
        3.125 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm_4 (SLICE_X47Y118.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.057ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_4 (FF)
  Destination:          cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.465ns (Levels of Logic = 0)
  Clock Path Skew:      0.174ns (1.113 - 0.939)
  Source Clock:         sys_clk_125 rising at 16.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.234ns

  Clock Uncertainty:          0.234ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_4 to cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y118.BQ     Tcko                  0.200   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray<4>
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_4
    SLICE_X47Y118.AX     net (fanout=5)        0.206   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray<4>
    SLICE_X47Y118.CLK    Tckdi       (-Th)    -0.059   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm<4>
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm_4
    -------------------------------------------------  ---------------------------
    Total                                      0.465ns (0.259ns logic, 0.206ns route)
                                                       (55.7% logic, 44.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray_xm_0 (SLICE_X59Y103.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.085ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray_0 (FF)
  Destination:          cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray_xm_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.491ns (Levels of Logic = 0)
  Clock Path Skew:      0.172ns (1.164 - 0.992)
  Source Clock:         sys_clk_125 rising at 16.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.234ns

  Clock Uncertainty:          0.234ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray_0 to cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray_xm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X58Y105.AQ     Tcko                  0.200   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray<4>
                                                       cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray_0
    SLICE_X59Y103.AX     net (fanout=2)        0.232   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray<0>
    SLICE_X59Y103.CLK    Tckdi       (-Th)    -0.059   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray_xm<3>
                                                       cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/rcb_gray_xm_0
    -------------------------------------------------  ---------------------------
    Total                                      0.491ns (0.259ns logic, 0.232ns route)
                                                       (52.7% logic, 47.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm_1 (SLICE_X49Y118.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.117ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_1 (FF)
  Destination:          cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.528ns (Levels of Logic = 0)
  Clock Path Skew:      0.177ns (1.114 - 0.937)
  Source Clock:         sys_clk_125 rising at 16.000ns
  Destination Clock:    sys_clk_62_5 rising at 16.000ns
  Clock Uncertainty:    0.234ns

  Clock Uncertainty:          0.234ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_1 to cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y119.DMUX   Tshcko                0.238   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Madd_wcb_bin_next_cy<2>
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_1
    SLICE_X49Y118.BX     net (fanout=1)        0.231   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray<1>
    SLICE_X49Y118.CLK    Tckdi       (-Th)    -0.059   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm<3>
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/wcb_gray_xm_1
    -------------------------------------------------  ---------------------------
    Total                                      0.528ns (0.297ns logic, 0.231ns route)
                                                       (56.2% logic, 43.8% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_sys_clk_62_5_buf = PERIOD TIMEGRP "sys_clk_62_5_buf" TS_clk_20m_vcxo_i /
        3.125 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 12.876ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_vme_core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
  Logical resource: cmp_vme_core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT1/CLKA
  Location pin: RAMB16_X2Y30.CLKA
  Clock network: sys_clk_62_5
--------------------------------------------------------------------------------
Slack: 12.876ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_vme_core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT2/CLKA
  Logical resource: cmp_vme_core/U_Wrapped_VME_Inst_VME_CR_CSR_Space/Mram_CR_addr[11]_s_CR_Space[4095][7]_wide_mux_4097_OUT2/CLKA
  Location pin: RAMB16_X2Y32.CLKA
  Clock network: sys_clk_62_5
--------------------------------------------------------------------------------
Slack: 12.876ns (period - min period limit)
  Period: 16.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Logical resource: cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Location pin: RAMB8_X2Y55.CLKAWRCLK
  Clock network: sys_clk_62_5
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_clk_125_buf" 
TS_clk_20m_vcxo_i / 6.25         HIGH 50%;

 755348 paths analyzed, 30081 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.767ns.
--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104 (SLICE_X19Y129.C6), 1647 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.233ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.556ns (Levels of Logic = 6)
  Clock Path Skew:      -0.106ns (0.793 - 0.899)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11 to cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y127.BQ     Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_10
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11
    SLICE_X19Y128.A1     net (fanout=20)       0.871   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11
    SLICE_X19Y128.A      Tilo                  0.259   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_B<4>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_A4
    SLICE_X22Y127.D6     net (fanout=2)        0.520   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_A<3>
    SLICE_X22Y127.DMUX   Topdd                 0.393   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_lut<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
    SLICE_X24Y125.A6     net (fanout=44)       0.748   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos<3>
    SLICE_X24Y125.A      Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_142
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_9
    SLICE_X24Y129.C6     net (fanout=1)        1.023   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_9
    SLICE_X24Y129.CMUX   Tilo                  0.343   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_81
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_2_f7
    SLICE_X28Y129.B5     net (fanout=1)        0.798   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos[6]_data[127]_Mux_20_o
    SLICE_X28Y129.B      Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_34
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk1
    SLICE_X19Y129.C6     net (fanout=128)      1.461   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk_mmx_out
    SLICE_X19Y129.CLK    Tas                   0.322   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104_rstpot
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
    -------------------------------------------------  ---------------------------
    Total                                      7.556ns (2.135ns logic, 5.421ns route)
                                                       (28.3% logic, 71.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.251ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.538ns (Levels of Logic = 6)
  Clock Path Skew:      -0.106ns (0.793 - 0.899)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11 to cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y127.BQ     Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_10
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11
    SLICE_X20Y128.B3     net (fanout=20)       0.912   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11
    SLICE_X20Y128.B      Tilo                  0.205   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_addr_d<25>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_A31
    SLICE_X22Y127.CX     net (fanout=1)        0.620   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_A<2>
    SLICE_X22Y127.DMUX   Tcxd                  0.288   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
    SLICE_X24Y125.A6     net (fanout=44)       0.748   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos<3>
    SLICE_X24Y125.A      Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_142
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_9
    SLICE_X24Y129.C6     net (fanout=1)        1.023   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_9
    SLICE_X24Y129.CMUX   Tilo                  0.343   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_81
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_2_f7
    SLICE_X28Y129.B5     net (fanout=1)        0.798   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos[6]_data[127]_Mux_20_o
    SLICE_X28Y129.B      Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_34
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk1
    SLICE_X19Y129.C6     net (fanout=128)      1.461   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk_mmx_out
    SLICE_X19Y129.CLK    Tas                   0.322   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104_rstpot
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
    -------------------------------------------------  ---------------------------
    Total                                      7.538ns (1.976ns logic, 5.562ns route)
                                                       (26.2% logic, 73.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.260ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_3 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.627ns (Levels of Logic = 6)
  Clock Path Skew:      -0.008ns (0.155 - 0.163)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_3 to cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y130.CQ     Tcko                  0.447   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/cnt<4>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/cnt_3
    SLICE_X19Y128.A3     net (fanout=9)        0.903   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/cnt<3>
    SLICE_X19Y128.A      Tilo                  0.259   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_B<4>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_A4
    SLICE_X22Y127.D6     net (fanout=2)        0.520   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_A<3>
    SLICE_X22Y127.DMUX   Topdd                 0.393   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_lut<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
    SLICE_X24Y125.A6     net (fanout=44)       0.748   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos<3>
    SLICE_X24Y125.A      Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_142
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_9
    SLICE_X24Y129.C6     net (fanout=1)        1.023   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_9
    SLICE_X24Y129.CMUX   Tilo                  0.343   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_81
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_2_f7
    SLICE_X28Y129.B5     net (fanout=1)        0.798   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos[6]_data[127]_Mux_20_o
    SLICE_X28Y129.B      Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_34
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk1
    SLICE_X19Y129.C6     net (fanout=128)      1.461   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk_mmx_out
    SLICE_X19Y129.CLK    Tas                   0.322   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104_rstpot
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_104
    -------------------------------------------------  ---------------------------
    Total                                      7.627ns (2.174ns logic, 5.453ns route)
                                                       (28.5% logic, 71.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem (RAMB8_X2Y59.DIBDI11), 20 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.238ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem1 (RAM)
  Destination:          cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem (RAM)
  Requirement:          8.000ns
  Data Path Delay:      7.570ns (Levels of Logic = 1)
  Clock Path Skew:      -0.087ns (0.860 - 0.947)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem1 to cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB8_X2Y55.DOADO9   Trcko_DOA             1.850   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem1
                                                       cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem1
    SLICE_X71Y123.A5     net (fanout=41)       3.449   vme_sync_master_out_adr<7>
    SLICE_X71Y123.A      Tilo                  0.259   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>
                                                       cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>4
    RAMB8_X2Y59.DIBDI11  net (fanout=1)        1.712   cnx_slave_out[0]_dat<24>
    RAMB8_X2Y59.CLKAWRCLKTrdck_DIB             0.300   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
    -------------------------------------------------  ---------------------------
    Total                                      7.570ns (2.409ns logic, 5.161ns route)
                                                       (31.8% logic, 68.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.207ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_xwb_reg/r_slave_dat_24 (FF)
  Destination:          cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem (RAM)
  Requirement:          8.000ns
  Data Path Delay:      6.599ns (Levels of Logic = 3)
  Clock Path Skew:      -0.089ns (0.860 - 0.949)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_1/cmp_xwb_reg/r_slave_dat_24 to cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X66Y98.AQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_1/cmp_xwb_reg/r_slave_dat<24>
                                                       cmp_fmc_adc_mezzanine_1/cmp_xwb_reg/r_slave_dat_24
    SLICE_X69Y124.D1     net (fanout=1)        2.435   cmp_fmc_adc_mezzanine_1/cmp_xwb_reg/r_slave_dat<24>
    SLICE_X69Y124.D      Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_1/wb_data_o<9>
                                                       cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>2
    SLICE_X71Y123.B3     net (fanout=1)        0.509   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>1
    SLICE_X71Y123.B      Tilo                  0.259   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>
                                                       cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>3
    SLICE_X71Y123.A3     net (fanout=1)        0.458   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>2
    SLICE_X71Y123.A      Tilo                  0.259   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>
                                                       cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>4
    RAMB8_X2Y59.DIBDI11  net (fanout=1)        1.712   cnx_slave_out[0]_dat<24>
    RAMB8_X2Y59.CLKAWRCLKTrdck_DIB             0.300   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
    -------------------------------------------------  ---------------------------
    Total                                      6.599ns (1.485ns logic, 5.114ns route)
                                                       (22.5% logic, 77.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.476ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_sdb_crossbar/crossbar/matrix_old_0_5 (FF)
  Destination:          cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem (RAM)
  Requirement:          8.000ns
  Data Path Delay:      6.394ns (Levels of Logic = 3)
  Clock Path Skew:      -0.025ns (0.233 - 0.258)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_sdb_crossbar/crossbar/matrix_old_0_5 to cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X57Y115.CQ     Tcko                  0.391   cmp_sdb_crossbar/crossbar/matrix_old_0<6>
                                                       cmp_sdb_crossbar/crossbar/matrix_old_0_5
    SLICE_X69Y124.D5     net (fanout=70)       2.247   cmp_sdb_crossbar/crossbar/matrix_old_0<5>
    SLICE_X69Y124.D      Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_1/wb_data_o<9>
                                                       cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>2
    SLICE_X71Y123.B3     net (fanout=1)        0.509   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>1
    SLICE_X71Y123.B      Tilo                  0.259   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>
                                                       cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>3
    SLICE_X71Y123.A3     net (fanout=1)        0.458   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>2
    SLICE_X71Y123.A      Tilo                  0.259   cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>
                                                       cmp_sdb_crossbar/crossbar/slave_o[0]_dat<24>4
    RAMB8_X2Y59.DIBDI11  net (fanout=1)        1.712   cnx_slave_out[0]_dat<24>
    RAMB8_X2Y59.CLKAWRCLKTrdck_DIB             0.300   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/Mram_mem
    -------------------------------------------------  ---------------------------
    Total                                      6.394ns (1.468ns logic, 4.926ns route)
                                                       (23.0% logic, 77.0% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_data_7 (SLICE_X15Y140.D2), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.254ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_data_7 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.491ns (Levels of Logic = 1)
  Clock Path Skew:      -0.150ns (0.790 - 0.940)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem2 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB8_X2Y53.DOADO5   Trcko_DOA             1.850   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem2
                                                       cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/Mram_mem2
    SLICE_X15Y140.D2     net (fanout=12)       5.414   vme_sync_master_out_dat<7>
    SLICE_X15Y140.CLK    Tas                   0.227   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_data<6>
                                                       cmp_sdb_crossbar/crossbar/master_oe[6]_dat<7>1
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_data_7
    -------------------------------------------------  ---------------------------
    Total                                      7.491ns (2.077ns logic, 5.414ns route)
                                                       (27.7% logic, 72.3% route)

--------------------------------------------------------------------------------

Hold Paths: TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_clk_125_buf" TS_clk_20m_vcxo_i / 6.25
        HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm_0 (SLICE_X59Y104.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.170ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_0 (FF)
  Destination:          cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.580ns (Levels of Logic = 0)
  Clock Path Skew:      0.176ns (1.165 - 0.989)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.234ns

  Clock Uncertainty:          0.234ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_0 to cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X57Y103.BQ     Tcko                  0.198   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray<4>
                                                       cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_0
    SLICE_X59Y104.AX     net (fanout=1)        0.323   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray<0>
    SLICE_X59Y104.CLK    Tckdi       (-Th)    -0.059   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm<3>
                                                       cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm_0
    -------------------------------------------------  ---------------------------
    Total                                      0.580ns (0.257ns logic, 0.323ns route)
                                                       (44.3% logic, 55.7% route)

--------------------------------------------------------------------------------

Paths for end point cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray_xm_4 (SLICE_X49Y116.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.200ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray_4 (FF)
  Destination:          cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray_xm_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.606ns (Levels of Logic = 0)
  Clock Path Skew:      0.172ns (1.119 - 0.947)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.234ns

  Clock Uncertainty:          0.234ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray_4 to cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray_xm_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y114.BQ     Tcko                  0.200   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray<4>
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray_4
    SLICE_X49Y116.AX     net (fanout=5)        0.347   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray<4>
    SLICE_X49Y116.CLK    Tckdi       (-Th)    -0.059   cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray_xm<4>
                                                       cmp_xwb_clock_crossing/sfifo/U_Inferred_FIFO/rcb_gray_xm_4
    -------------------------------------------------  ---------------------------
    Total                                      0.606ns (0.259ns logic, 0.347ns route)
                                                       (42.7% logic, 57.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm_3 (SLICE_X59Y104.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.212ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_3 (FF)
  Destination:          cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.622ns (Levels of Logic = 0)
  Clock Path Skew:      0.176ns (1.165 - 0.989)
  Source Clock:         sys_clk_62_5 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.234ns

  Clock Uncertainty:          0.234ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.217ns
    Phase Error (PE):           0.120ns

  Minimum Data Path at Fast Process Corner: cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_3 to cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X57Y103.CMUX   Tshcko                0.244   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray<4>
                                                       cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_3
    SLICE_X59Y104.DX     net (fanout=1)        0.319   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray<3>
    SLICE_X59Y104.CLK    Tckdi       (-Th)    -0.059   cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm<3>
                                                       cmp_xwb_clock_crossing/mfifo/U_Inferred_FIFO/wcb_gray_xm_3
    -------------------------------------------------  ---------------------------
    Total                                      0.622ns (0.303ns logic, 0.319ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_clk_125_buf" TS_clk_20m_vcxo_i / 6.25
        HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
  Location pin: RAMB16_X3Y30.CLKA
  Clock network: sys_clk_125
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKB
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKB
  Location pin: RAMB16_X3Y30.CLKB
  Clock network: sys_clk_125
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
  Location pin: RAMB16_X4Y88.CLKA
  Clock network: sys_clk_125
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_buf" 
TS_clk_20m_vcxo_i / 16.6666667         HIGH 50%;

 6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   2.572ns.
--------------------------------------------------------------------------------

Paths for end point cmp_sync_ddr_rst/sync1 (SLICE_X50Y142.BX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     1.546ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_sync_ddr_rst/sync0 (FF)
  Destination:          cmp_sync_ddr_rst/sync1 (FF)
  Requirement:          3.000ns
  Data Path Delay:      1.362ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 3.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_sync_ddr_rst/sync0 to cmp_sync_ddr_rst/sync1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y142.AQ     Tcko                  0.408   cmp_sync_ddr_rst/sync2
                                                       cmp_sync_ddr_rst/sync0
    SLICE_X50Y142.BX     net (fanout=1)        0.818   cmp_sync_ddr_rst/sync0
    SLICE_X50Y142.CLK    Tdick                 0.136   cmp_sync_ddr_rst/sync2
                                                       cmp_sync_ddr_rst/sync1
    -------------------------------------------------  ---------------------------
    Total                                      1.362ns (0.544ns logic, 0.818ns route)
                                                       (39.9% logic, 60.1% route)

--------------------------------------------------------------------------------

Paths for end point cmp_sync_fmc0_rst/sync2 (SLICE_X49Y140.CX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     1.638ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_sync_fmc0_rst/sync1 (FF)
  Destination:          cmp_sync_fmc0_rst/sync2 (FF)
  Requirement:          3.000ns
  Data Path Delay:      1.270ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 3.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_sync_fmc0_rst/sync1 to cmp_sync_fmc0_rst/sync2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X49Y140.BQ     Tcko                  0.391   cmp_sync_fmc0_rst/sync2
                                                       cmp_sync_fmc0_rst/sync1
    SLICE_X49Y140.CX     net (fanout=1)        0.816   cmp_sync_fmc0_rst/sync1
    SLICE_X49Y140.CLK    Tdick                 0.063   cmp_sync_fmc0_rst/sync2
                                                       cmp_sync_fmc0_rst/sync2
    -------------------------------------------------  ---------------------------
    Total                                      1.270ns (0.454ns logic, 0.816ns route)
                                                       (35.7% logic, 64.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_sync_fmc1_rst/sync2 (SLICE_X89Y140.CX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     1.638ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_sync_fmc1_rst/sync1 (FF)
  Destination:          cmp_sync_fmc1_rst/sync2 (FF)
  Requirement:          3.000ns
  Data Path Delay:      1.270ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 3.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_sync_fmc1_rst/sync1 to cmp_sync_fmc1_rst/sync2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X89Y140.BQ     Tcko                  0.391   cmp_sync_fmc1_rst/sync2
                                                       cmp_sync_fmc1_rst/sync1
    SLICE_X89Y140.CX     net (fanout=1)        0.816   cmp_sync_fmc1_rst/sync1
    SLICE_X89Y140.CLK    Tdick                 0.063   cmp_sync_fmc1_rst/sync2
                                                       cmp_sync_fmc1_rst/sync2
    -------------------------------------------------  ---------------------------
    Total                                      1.270ns (0.454ns logic, 0.816ns route)
                                                       (35.7% logic, 64.3% route)

--------------------------------------------------------------------------------

Hold Paths: TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_buf" TS_clk_20m_vcxo_i / 16.6666667
        HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_sync_ddr_rst/sync2 (SLICE_X50Y142.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.562ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_sync_ddr_rst/sync1 (FF)
  Destination:          cmp_sync_ddr_rst/sync2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.562ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 3.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_sync_ddr_rst/sync1 to cmp_sync_ddr_rst/sync2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y142.BQ     Tcko                  0.200   cmp_sync_ddr_rst/sync2
                                                       cmp_sync_ddr_rst/sync1
    SLICE_X50Y142.CX     net (fanout=1)        0.314   cmp_sync_ddr_rst/sync1
    SLICE_X50Y142.CLK    Tckdi       (-Th)    -0.048   cmp_sync_ddr_rst/sync2
                                                       cmp_sync_ddr_rst/sync2
    -------------------------------------------------  ---------------------------
    Total                                      0.562ns (0.248ns logic, 0.314ns route)
                                                       (44.1% logic, 55.9% route)

--------------------------------------------------------------------------------

Paths for end point cmp_sync_fmc0_rst/sync1 (SLICE_X49Y140.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.687ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_sync_fmc0_rst/sync0 (FF)
  Destination:          cmp_sync_fmc0_rst/sync1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.687ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 3.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_sync_fmc0_rst/sync0 to cmp_sync_fmc0_rst/sync1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X49Y140.AQ     Tcko                  0.198   cmp_sync_fmc0_rst/sync2
                                                       cmp_sync_fmc0_rst/sync0
    SLICE_X49Y140.BX     net (fanout=1)        0.430   cmp_sync_fmc0_rst/sync0
    SLICE_X49Y140.CLK    Tckdi       (-Th)    -0.059   cmp_sync_fmc0_rst/sync2
                                                       cmp_sync_fmc0_rst/sync1
    -------------------------------------------------  ---------------------------
    Total                                      0.687ns (0.257ns logic, 0.430ns route)
                                                       (37.4% logic, 62.6% route)

--------------------------------------------------------------------------------

Paths for end point cmp_sync_fmc1_rst/sync1 (SLICE_X89Y140.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.687ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_sync_fmc1_rst/sync0 (FF)
  Destination:          cmp_sync_fmc1_rst/sync1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.687ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg rising at 3.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_sync_fmc1_rst/sync0 to cmp_sync_fmc1_rst/sync1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X89Y140.AQ     Tcko                  0.198   cmp_sync_fmc1_rst/sync2
                                                       cmp_sync_fmc1_rst/sync0
    SLICE_X89Y140.BX     net (fanout=1)        0.430   cmp_sync_fmc1_rst/sync0
    SLICE_X89Y140.CLK    Tckdi       (-Th)    -0.059   cmp_sync_fmc1_rst/sync2
                                                       cmp_sync_fmc1_rst/sync1
    -------------------------------------------------  ---------------------------
    Total                                      0.687ns (0.257ns logic, 0.430ns route)
                                                       (37.4% logic, 62.6% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_buf" TS_clk_20m_vcxo_i / 16.6666667
        HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.428ns (period - (min low pulse limit / (low pulse / period)))
  Period: 3.000ns
  Low pulse: 1.500ns
  Low pulse limit: 1.286ns (Tdcmpw_CLKIN_300_350)
  Physical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg
--------------------------------------------------------------------------------
Slack: 0.428ns (period - (min high pulse limit / (high pulse / period)))
  Period: 3.000ns
  High pulse: 1.500ns
  High pulse limit: 1.286ns (Tdcmpw_CLKIN_300_350)
  Physical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg
--------------------------------------------------------------------------------
Slack: 0.428ns (period - (min low pulse limit / (low pulse / period)))
  Period: 3.000ns
  Low pulse: 1.500ns
  Low pulse limit: 1.286ns (Tdcmpw_CLKIN_300_350)
  Physical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y5.CLKIN2
  Clock network: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/sys_clk_ibufg
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk = 
PERIOD TIMEGRP         "cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk" 
        TS_adc0_dco_n_i HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.636ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk"
        TS_adc0_dco_n_i HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.075ns (period - min period limit)
  Period: 1.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKOUT0
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKOUT0
  Location pin: PLL_ADV_X0Y3.CLKOUT0
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_clk
--------------------------------------------------------------------------------
Slack: 0.148ns (period - min period limit)
  Period: 2.000ns
  Min period limit: 1.852ns (539.957MHz) (Tpllper_CLKIN(Finmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y3.CLKIN1
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dco_clk
--------------------------------------------------------------------------------
Slack: 0.364ns (period - (min low pulse limit / (low pulse / period)))
  Period: 2.000ns
  Low pulse: 1.000ns
  Low pulse limit: 0.818ns (Tdcmpw_CLKIN_500_550)
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y3.CLKIN1
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dco_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_dco_clk = 
PERIOD TIMEGRP         "cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_dco_clk" 
        TS_adc1_dco_n_i HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.636ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_dco_clk = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_dco_clk"
        TS_adc1_dco_n_i HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.075ns (period - min period limit)
  Period: 1.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKOUT0
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKOUT0
  Location pin: PLL_ADV_X0Y2.CLKOUT0
  Clock network: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_clk
--------------------------------------------------------------------------------
Slack: 0.148ns (period - min period limit)
  Period: 2.000ns
  Min period limit: 1.852ns (539.957MHz) (Tpllper_CLKIN(Finmax))
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y2.CLKIN2
  Clock network: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/dco_clk
--------------------------------------------------------------------------------
Slack: 0.364ns (period - (min low pulse limit / (low pulse / period)))
  Period: 2.000ns
  Low pulse: 1.000ns
  Low pulse limit: 0.818ns (Tdcmpw_CLKIN_500_550)
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y2.CLKIN2
  Clock network: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/dco_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl
_memc4_infrastructure_inst_mcb_drp_clk_bufg_in         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m
emc4_infrastructure_inst_mcb_drp_clk_bufg_in"         TS_ddr_clk_buf / 0.25 
HIGH 50%;

 10471 paths analyzed, 1126 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   6.867ns.
--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (SLICE_X13Y164.CE), 251 paths
--------------------------------------------------------------------------------
Slack (setup path):     5.133ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.845ns (Levels of Logic = 6)
  Clock Path Skew:      0.070ns (0.890 - 0.820)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y155.BMUX   Tshcko                0.461   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X12Y157.A1     net (fanout=12)       0.872   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X12Y157.A      Tilo                  0.205   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o3
    SLICE_X12Y157.C1     net (fanout=1)        0.441   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o1
    SLICE_X12Y157.CMUX   Tilo                  0.251   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o11
    SLICE_X13Y158.A3     net (fanout=1)        0.480   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o11
    SLICE_X13Y158.A      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg<6>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o12
    SLICE_X10Y161.C1     net (fanout=2)        0.861   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o2
    SLICE_X10Y161.C      Tilo                  0.204   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIADDR_int<2>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In111
    SLICE_X13Y164.B1     net (fanout=3)        1.043   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In11
    SLICE_X13Y164.B      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv2
    SLICE_X13Y164.A5     net (fanout=1)        0.187   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv2
    SLICE_X13Y164.A      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3
    SLICE_X13Y164.CE     net (fanout=2)        0.723   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv
    SLICE_X13Y164.CLK    Tceck                 0.340   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      6.845ns (2.238ns logic, 4.607ns route)
                                                       (32.7% logic, 67.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.277ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.701ns (Levels of Logic = 6)
  Clock Path Skew:      0.070ns (0.890 - 0.820)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y155.BQ     Tcko                  0.391   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1
    SLICE_X12Y157.A2     net (fanout=11)       0.798   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<1>
    SLICE_X12Y157.A      Tilo                  0.205   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o3
    SLICE_X12Y157.C1     net (fanout=1)        0.441   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o1
    SLICE_X12Y157.CMUX   Tilo                  0.251   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o11
    SLICE_X13Y158.A3     net (fanout=1)        0.480   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o11
    SLICE_X13Y158.A      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg<6>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o12
    SLICE_X10Y161.C1     net (fanout=2)        0.861   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o2
    SLICE_X10Y161.C      Tilo                  0.204   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIADDR_int<2>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In111
    SLICE_X13Y164.B1     net (fanout=3)        1.043   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In11
    SLICE_X13Y164.B      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv2
    SLICE_X13Y164.A5     net (fanout=1)        0.187   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv2
    SLICE_X13Y164.A      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3
    SLICE_X13Y164.CE     net (fanout=2)        0.723   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv
    SLICE_X13Y164.CLK    Tceck                 0.340   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      6.701ns (2.168ns logic, 4.533ns route)
                                                       (32.4% logic, 67.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.327ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_1 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.647ns (Levels of Logic = 6)
  Clock Path Skew:      0.066ns (0.890 - 0.824)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_1 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y157.BQ     Tcko                  0.391   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_1
    SLICE_X10Y157.BX     net (fanout=6)        0.967   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous<1>
    SLICE_X10Y157.CMUX   Taxc                  0.310   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_cy<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_cy<3>
    SLICE_X11Y159.C3     net (fanout=1)        0.508   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Delta_Dn<2>
    SLICE_X11Y159.C      Tilo                  0.259   N684
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02501_SW0
    SLICE_X11Y159.A2     net (fanout=1)        0.437   N684
    SLICE_X11Y159.A      Tilo                  0.259   N684
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02501
    SLICE_X10Y161.C3     net (fanout=2)        0.501   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n0250
    SLICE_X10Y161.C      Tilo                  0.204   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIADDR_int<2>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In111
    SLICE_X13Y164.B1     net (fanout=3)        1.043   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In11
    SLICE_X13Y164.B      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv2
    SLICE_X13Y164.A5     net (fanout=1)        0.187   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv2
    SLICE_X13Y164.A      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3
    SLICE_X13Y164.CE     net (fanout=2)        0.723   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv
    SLICE_X13Y164.CLK    Tceck                 0.340   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      6.647ns (2.281ns logic, 4.366ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2 (SLICE_X12Y163.C1), 336 paths
--------------------------------------------------------------------------------
Slack (setup path):     5.189ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_3 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.787ns (Levels of Logic = 6)
  Clock Path Skew:      0.068ns (0.892 - 0.824)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_3 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y157.DQ     Tcko                  0.391   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_3
    SLICE_X10Y155.D4     net (fanout=5)        1.482   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous<3>
    SLICE_X10Y155.COUT   Topcyd                0.261   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_cy<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_lut<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_cy<3>
    SLICE_X10Y156.CIN    net (fanout=1)        0.003   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_cy<3>
    SLICE_X10Y156.DMUX   Tcind                 0.302   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Delta_Up<7>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_xor<7>
    SLICE_X11Y156.C2     net (fanout=1)        0.789   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Delta_Up<7>
    SLICE_X11Y156.C      Tilo                  0.259   N686
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02541
    SLICE_X11Y159.B2     net (fanout=3)        0.963   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n0254
    SLICE_X11Y159.B      Tilo                  0.259   N684
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In11
    SLICE_X12Y163.A1     net (fanout=1)        1.085   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In11
    SLICE_X12Y163.A      Tilo                  0.205   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In15
    SLICE_X12Y163.C1     net (fanout=2)        0.447   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In1
    SLICE_X12Y163.CLK    Tas                   0.341   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In3
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
    -------------------------------------------------  ---------------------------
    Total                                      6.787ns (2.018ns logic, 4.769ns route)
                                                       (29.7% logic, 70.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.400ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.580ns (Levels of Logic = 7)
  Clock Path Skew:      0.072ns (0.892 - 0.820)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y155.BMUX   Tshcko                0.461   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X15Y165.B4     net (fanout=12)       1.557   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X15Y165.B      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X15Y165.D2     net (fanout=1)        0.426   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X15Y165.DMUX   Tilo                  0.313   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X15Y166.C4     net (fanout=1)        0.455   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X15Y166.C      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X15Y166.D5     net (fanout=2)        0.215   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X15Y166.D      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In12
    SLICE_X13Y166.C3     net (fanout=1)        0.476   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In12
    SLICE_X13Y166.C      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In13
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In14
    SLICE_X12Y163.A3     net (fanout=1)        0.648   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In14
    SLICE_X12Y163.A      Tilo                  0.205   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In15
    SLICE_X12Y163.C1     net (fanout=2)        0.447   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In1
    SLICE_X12Y163.CLK    Tas                   0.341   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In3
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
    -------------------------------------------------  ---------------------------
    Total                                      6.580ns (2.356ns logic, 4.224ns route)
                                                       (35.8% logic, 64.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.529ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_3 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.447ns (Levels of Logic = 6)
  Clock Path Skew:      0.068ns (0.892 - 0.824)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_3 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y157.DQ     Tcko                  0.391   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_3
    SLICE_X10Y155.D4     net (fanout=5)        1.482   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous<3>
    SLICE_X10Y155.COUT   Topcyd                0.261   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_cy<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_lut<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_cy<3>
    SLICE_X10Y156.CIN    net (fanout=1)        0.003   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_cy<3>
    SLICE_X10Y156.CMUX   Tcinc                 0.261   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Delta_Up<7>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Up_xor<7>
    SLICE_X11Y156.C4     net (fanout=1)        0.490   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Delta_Up<6>
    SLICE_X11Y156.C      Tilo                  0.259   N686
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02541
    SLICE_X11Y159.B2     net (fanout=3)        0.963   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n0254
    SLICE_X11Y159.B      Tilo                  0.259   N684
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In11
    SLICE_X12Y163.A1     net (fanout=1)        1.085   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In11
    SLICE_X12Y163.A      Tilo                  0.205   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In15
    SLICE_X12Y163.C1     net (fanout=2)        0.447   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In1
    SLICE_X12Y163.CLK    Tas                   0.341   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2-In3
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd2
    -------------------------------------------------  ---------------------------
    Total                                      6.447ns (1.977ns logic, 4.470ns route)
                                                       (30.7% logic, 69.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0 (SLICE_X16Y165.CE), 156 paths
--------------------------------------------------------------------------------
Slack (setup path):     5.329ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.646ns (Levels of Logic = 6)
  Clock Path Skew:      0.067ns (0.887 - 0.820)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y155.BMUX   Tshcko                0.461   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X15Y165.B4     net (fanout=12)       1.557   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X15Y165.B      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X15Y165.D2     net (fanout=1)        0.426   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X15Y165.DMUX   Tilo                  0.313   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X15Y166.C4     net (fanout=1)        0.455   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X15Y166.C      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X15Y166.A2     net (fanout=2)        0.443   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X15Y166.A      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X12Y166.D4     net (fanout=2)        0.421   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X12Y166.D      Tilo                  0.205   N672
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X13Y167.C6     net (fanout=1)        0.279   N672
    SLICE_X13Y167.C      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X16Y165.CE     net (fanout=2)        0.715   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X16Y165.CLK    Tceck                 0.335   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    -------------------------------------------------  ---------------------------
    Total                                      6.646ns (2.350ns logic, 4.296ns route)
                                                       (35.4% logic, 64.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.467ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.508ns (Levels of Logic = 6)
  Clock Path Skew:      0.067ns (0.887 - 0.820)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y155.AMUX   Tshcko                0.461   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3
    SLICE_X15Y165.B5     net (fanout=11)       1.419   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<3>
    SLICE_X15Y165.B      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X15Y165.D2     net (fanout=1)        0.426   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X15Y165.DMUX   Tilo                  0.313   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X15Y166.C4     net (fanout=1)        0.455   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X15Y166.C      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X15Y166.A2     net (fanout=2)        0.443   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X15Y166.A      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X12Y166.D4     net (fanout=2)        0.421   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X12Y166.D      Tilo                  0.205   N672
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X13Y167.C6     net (fanout=1)        0.279   N672
    SLICE_X13Y167.C      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X16Y165.CE     net (fanout=2)        0.715   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X16Y165.CLK    Tceck                 0.335   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    -------------------------------------------------  ---------------------------
    Total                                      6.508ns (2.350ns logic, 4.158ns route)
                                                       (36.1% logic, 63.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.777ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.198ns (Levels of Logic = 6)
  Clock Path Skew:      0.067ns (0.887 - 0.820)
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y155.BQ     Tcko                  0.391   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1
    SLICE_X15Y165.B6     net (fanout=11)       1.179   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<1>
    SLICE_X15Y165.B      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X15Y165.D2     net (fanout=1)        0.426   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X15Y165.DMUX   Tilo                  0.313   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X15Y166.C4     net (fanout=1)        0.455   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X15Y166.C      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X15Y166.A2     net (fanout=2)        0.443   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X15Y166.A      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X12Y166.D4     net (fanout=2)        0.421   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X12Y166.D      Tilo                  0.205   N672
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X13Y167.C6     net (fanout=1)        0.279   N672
    SLICE_X13Y167.C      Tilo                  0.259   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X16Y165.CE     net (fanout=2)        0.715   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X16Y165.CLK    Tceck                 0.335   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    -------------------------------------------------  ---------------------------
    Total                                      6.198ns (2.280ns logic, 3.918ns route)
                                                       (36.8% logic, 63.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_infrastructure_inst_mcb_drp_clk_bufg_in
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_infrastructure_inst_mcb_drp_clk_bufg_in"
        TS_ddr_clk_buf / 0.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2 (SLICE_X24Y148.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.388ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R1 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.388ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R1 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y148.AQ     Tcko                  0.200   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R1
    SLICE_X24Y148.BX     net (fanout=1)        0.140   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R1
    SLICE_X24Y148.CLK    Tckdi       (-Th)    -0.048   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/PLL_LOCK_R2
    -------------------------------------------------  ---------------------------
    Total                                      0.388ns (0.248ns logic, 0.140ns route)
                                                       (63.9% logic, 36.1% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase (SLICE_X8Y173.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.412ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.412ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X8Y173.DQ      Tcko                  0.200   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
    SLICE_X8Y173.D6      net (fanout=3)        0.022   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
    SLICE_X8Y173.CLK     Tah         (-Th)    -0.190   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/Mmux_ADDR_PHASE_ST_ALMOST_READY2_ST_MUX_10777_o11
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
    -------------------------------------------------  ---------------------------
    Total                                      0.412ns (0.390ns logic, 0.022ns route)
                                                       (94.7% logic, 5.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 (SLICE_X12Y150.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.421ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 (FF)
  Destination:          cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.421ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 to cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y150.DQ     Tcko                  0.200   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    SLICE_X12Y150.D6     net (fanout=15)       0.031   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    SLICE_X12Y150.CLK    Tah         (-Th)    -0.190   cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8-In1
                                                       cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    -------------------------------------------------  ---------------------------
    Total                                      0.421ns (0.390ns logic, 0.031ns route)
                                                       (92.6% logic, 7.4% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_infrastructure_inst_mcb_drp_clk_bufg_in
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_infrastructure_inst_mcb_drp_clk_bufg_in"
        TS_ddr_clk_buf / 0.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 10.270ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 1.730ns (578.035MHz) (Tbcper_I)
  Physical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/U_BUFG_CLK1/I0
  Logical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/U_BUFG_CLK1/I0
  Location pin: BUFGMUX_X2Y3.I0
  Clock network: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_infrastructure_inst/mcb_drp_clk_bufg_in
--------------------------------------------------------------------------------
Slack: 11.000ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 1.000ns (1000.000MHz) (Tmcbcper_UICLK)
  Physical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/samc_0/UICLK
  Logical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/samc_0/UICLK
  Location pin: MCB_X0Y3.UICLK
  Clock network: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk
--------------------------------------------------------------------------------
Slack: 11.570ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 0.430ns (2325.581MHz) (Tcp)
  Physical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/counter_dec<3>/CLK
  Logical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/counter_dec_0/CK
  Location pin: SLICE_X12Y167.CLK
  Clock network: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_mcb_drp_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl
_memc4_infrastructure_inst_clk_2x_180         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m
emc4_infrastructure_inst_clk_2x_180"         TS_ddr_clk_buf / 2 PHASE 0.75 ns 
HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_infrastructure_inst_clk_2x_180
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_infrastructure_inst_clk_2x_180"
        TS_ddr_clk_buf / 2 PHASE 0.75 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Logical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Location pin: MCB_X0Y3.PLLCLK1
  Clock network: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_sysclk_2x_180
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl
_memc4_infrastructure_inst_clk_2x_0         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m
emc4_infrastructure_inst_clk_2x_0"         TS_ddr_clk_buf / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_infrastructure_inst_clk_2x_0
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_infrastructure_inst_clk_2x_0"
        TS_ddr_clk_buf / 2 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Logical resource: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Location pin: MCB_X0Y3.PLLCLK0
  Clock network: cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/c4_sysclk_2x
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl
_memc5_infrastructure_inst_mcb_drp_clk_bufg_in         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m
emc5_infrastructure_inst_mcb_drp_clk_bufg_in"         TS_ddr_clk_buf / 0.25 
HIGH 50%;

 10461 paths analyzed, 1133 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.066ns.
--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0 (SLICE_X112Y166.CE), 156 paths
--------------------------------------------------------------------------------
Slack (setup path):     4.934ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.949ns (Levels of Logic = 6)
  Clock Path Skew:      -0.025ns (0.236 - 0.261)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X111Y175.BQ    Tcko                  0.391   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1
    SLICE_X113Y166.A2    net (fanout=11)       1.455   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<1>
    SLICE_X113Y166.A     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X113Y166.C2    net (fanout=1)        0.427   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X113Y166.CMUX  Tilo                  0.313   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C3    net (fanout=1)        0.526   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X114Y167.A1    net (fanout=2)        0.457   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X114Y167.A     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D1    net (fanout=2)        0.569   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D     Tilo                  0.259   N646
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X119Y169.C6    net (fanout=1)        0.558   N646
    SLICE_X119Y169.C     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CE    net (fanout=2)        0.735   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CLK   Tceck                 0.331   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    -------------------------------------------------  ---------------------------
    Total                                      6.949ns (2.222ns logic, 4.727ns route)
                                                       (32.0% logic, 68.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.011ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.872ns (Levels of Logic = 6)
  Clock Path Skew:      -0.025ns (0.236 - 0.261)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X111Y175.AMUX  Tshcko                0.461   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3
    SLICE_X113Y166.A4    net (fanout=11)       1.308   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<3>
    SLICE_X113Y166.A     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X113Y166.C2    net (fanout=1)        0.427   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X113Y166.CMUX  Tilo                  0.313   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C3    net (fanout=1)        0.526   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X114Y167.A1    net (fanout=2)        0.457   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X114Y167.A     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D1    net (fanout=2)        0.569   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D     Tilo                  0.259   N646
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X119Y169.C6    net (fanout=1)        0.558   N646
    SLICE_X119Y169.C     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CE    net (fanout=2)        0.735   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CLK   Tceck                 0.331   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    -------------------------------------------------  ---------------------------
    Total                                      6.872ns (2.292ns logic, 4.580ns route)
                                                       (33.4% logic, 66.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.136ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.747ns (Levels of Logic = 6)
  Clock Path Skew:      -0.025ns (0.236 - 0.261)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X111Y175.BMUX  Tshcko                0.461   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X113Y166.A5    net (fanout=12)       1.183   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X113Y166.A     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X113Y166.C2    net (fanout=1)        0.427   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X113Y166.CMUX  Tilo                  0.313   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C3    net (fanout=1)        0.526   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X114Y167.A1    net (fanout=2)        0.457   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X114Y167.A     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D1    net (fanout=2)        0.569   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D     Tilo                  0.259   N646
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X119Y169.C6    net (fanout=1)        0.558   N646
    SLICE_X119Y169.C     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CE    net (fanout=2)        0.735   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CLK   Tceck                 0.331   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_0
    -------------------------------------------------  ---------------------------
    Total                                      6.747ns (2.292ns logic, 4.455ns route)
                                                       (34.0% logic, 66.0% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (SLICE_X110Y167.CE), 252 paths
--------------------------------------------------------------------------------
Slack (setup path):     4.956ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_0 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.925ns (Levels of Logic = 5)
  Clock Path Skew:      -0.027ns (0.234 - 0.261)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_0 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X111Y175.AQ    Tcko                  0.391   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_0
    SLICE_X112Y172.A1    net (fanout=10)       1.042   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<0>
    SLICE_X112Y172.CMUX  Topac                 0.537   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_cy<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_lut<0>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_cy<3>
    SLICE_X115Y173.C3    net (fanout=1)        0.528   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Delta_Dn<2>
    SLICE_X115Y173.C     Tilo                  0.259   N658
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02501_SW0
    SLICE_X115Y173.A2    net (fanout=1)        0.437   N658
    SLICE_X115Y173.A     Tilo                  0.259   N658
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02501
    SLICE_X116Y173.C2    net (fanout=2)        0.611   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n0250
    SLICE_X116Y173.C     Tilo                  0.204   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIADDR_int<2>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In111
    SLICE_X110Y167.C4    net (fanout=3)        1.204   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In11
    SLICE_X110Y167.CMUX  Tilo                  0.343   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3_G
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3
    SLICE_X110Y167.CE    net (fanout=2)        0.775   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv
    SLICE_X110Y167.CLK   Tceck                 0.335   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      6.925ns (2.328ns logic, 4.597ns route)
                                                       (33.6% logic, 66.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.155ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_0 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.730ns (Levels of Logic = 5)
  Clock Path Skew:      -0.023ns (0.234 - 0.257)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_0 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X113Y172.AQ    Tcko                  0.391   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous_0
    SLICE_X112Y172.AX    net (fanout=6)        1.036   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous<0>
    SLICE_X112Y172.CMUX  Taxc                  0.348   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_cy<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_cy<3>
    SLICE_X115Y173.C3    net (fanout=1)        0.528   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Delta_Dn<2>
    SLICE_X115Y173.C     Tilo                  0.259   N658
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02501_SW0
    SLICE_X115Y173.A2    net (fanout=1)        0.437   N658
    SLICE_X115Y173.A     Tilo                  0.259   N658
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02501
    SLICE_X116Y173.C2    net (fanout=2)        0.611   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n0250
    SLICE_X116Y173.C     Tilo                  0.204   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIADDR_int<2>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In111
    SLICE_X110Y167.C4    net (fanout=3)        1.204   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In11
    SLICE_X110Y167.CMUX  Tilo                  0.343   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3_G
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3
    SLICE_X110Y167.CE    net (fanout=2)        0.775   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv
    SLICE_X110Y167.CLK   Tceck                 0.335   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      6.730ns (2.139ns logic, 4.591ns route)
                                                       (31.8% logic, 68.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.166ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.715ns (Levels of Logic = 5)
  Clock Path Skew:      -0.027ns (0.234 - 0.261)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X111Y175.BQ    Tcko                  0.391   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1
    SLICE_X112Y172.B4    net (fanout=11)       0.843   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<1>
    SLICE_X112Y172.CMUX  Topbc                 0.526   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_cy<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_lut<1>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Msub_Max_Value_Delta_Dn_cy<3>
    SLICE_X115Y173.C3    net (fanout=1)        0.528   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Delta_Dn<2>
    SLICE_X115Y173.C     Tilo                  0.259   N658
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02501_SW0
    SLICE_X115Y173.A2    net (fanout=1)        0.437   N658
    SLICE_X115Y173.A     Tilo                  0.259   N658
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n02501
    SLICE_X116Y173.C2    net (fanout=2)        0.611   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/n0250
    SLICE_X116Y173.C     Tilo                  0.204   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIADDR_int<2>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In111
    SLICE_X110Y167.C4    net (fanout=3)        1.204   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In11
    SLICE_X110Y167.CMUX  Tilo                  0.343   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3_G
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv3
    SLICE_X110Y167.CE    net (fanout=2)        0.775   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1730_inv
    SLICE_X110Y167.CLK   Tceck                 0.335   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      6.715ns (2.317ns logic, 4.398ns route)
                                                       (34.5% logic, 65.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2 (SLICE_X112Y166.CE), 156 paths
--------------------------------------------------------------------------------
Slack (setup path):     4.970ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.913ns (Levels of Logic = 6)
  Clock Path Skew:      -0.025ns (0.236 - 0.261)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X111Y175.BQ    Tcko                  0.391   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1
    SLICE_X113Y166.A2    net (fanout=11)       1.455   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<1>
    SLICE_X113Y166.A     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X113Y166.C2    net (fanout=1)        0.427   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X113Y166.CMUX  Tilo                  0.313   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C3    net (fanout=1)        0.526   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X114Y167.A1    net (fanout=2)        0.457   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X114Y167.A     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D1    net (fanout=2)        0.569   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D     Tilo                  0.259   N646
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X119Y169.C6    net (fanout=1)        0.558   N646
    SLICE_X119Y169.C     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CE    net (fanout=2)        0.735   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CLK   Tceck                 0.295   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2
    -------------------------------------------------  ---------------------------
    Total                                      6.913ns (2.186ns logic, 4.727ns route)
                                                       (31.6% logic, 68.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.047ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.836ns (Levels of Logic = 6)
  Clock Path Skew:      -0.025ns (0.236 - 0.261)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X111Y175.AMUX  Tshcko                0.461   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3
    SLICE_X113Y166.A4    net (fanout=11)       1.308   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<3>
    SLICE_X113Y166.A     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X113Y166.C2    net (fanout=1)        0.427   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X113Y166.CMUX  Tilo                  0.313   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C3    net (fanout=1)        0.526   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X114Y167.A1    net (fanout=2)        0.457   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X114Y167.A     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D1    net (fanout=2)        0.569   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D     Tilo                  0.259   N646
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X119Y169.C6    net (fanout=1)        0.558   N646
    SLICE_X119Y169.C     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CE    net (fanout=2)        0.735   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CLK   Tceck                 0.295   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2
    -------------------------------------------------  ---------------------------
    Total                                      6.836ns (2.256ns logic, 4.580ns route)
                                                       (33.0% logic, 67.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.172ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2 (FF)
  Requirement:          12.000ns
  Data Path Delay:      6.711ns (Levels of Logic = 6)
  Clock Path Skew:      -0.025ns (0.236 - 0.261)
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X111Y175.BMUX  Tshcko                0.461   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X113Y166.A5    net (fanout=12)       1.183   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X113Y166.A     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X113Y166.C2    net (fanout=1)        0.427   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X113Y166.CMUX  Tilo                  0.313   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C3    net (fanout=1)        0.526   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X114Y167.C     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X114Y167.A1    net (fanout=2)        0.457   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X114Y167.A     Tilo                  0.205   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D1    net (fanout=2)        0.569   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_626_o_AND_4061_o
    SLICE_X115Y167.D     Tilo                  0.259   N646
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv_SW0
    SLICE_X119Y169.C6    net (fanout=1)        0.558   N646
    SLICE_X119Y169.C     Tilo                  0.259   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSDEC
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CE    net (fanout=2)        0.735   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1688_inv
    SLICE_X112Y166.CLK   Tceck                 0.295   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<3>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_2
    -------------------------------------------------  ---------------------------
    Total                                      6.711ns (2.256ns logic, 4.455ns route)
                                                       (33.6% logic, 66.4% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_infrastructure_inst_mcb_drp_clk_bufg_in
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_infrastructure_inst_mcb_drp_clk_bufg_in"
        TS_ddr_clk_buf / 0.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN (SLICE_X118Y172.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.417ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.417ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X118Y172.AQ    Tcko                  0.200   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
    SLICE_X118Y172.A6    net (fanout=2)        0.027   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
    SLICE_X118Y172.CLK   Tah         (-Th)    -0.190   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN_rstpot
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UICMDEN
    -------------------------------------------------  ---------------------------
    Total                                      0.417ns (0.390ns logic, 0.027ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase (SLICE_X118Y175.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.422ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.422ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X118Y175.AQ    Tcko                  0.200   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/shift_through_reg<7>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
    SLICE_X118Y175.A6    net (fanout=3)        0.032   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
    SLICE_X118Y175.CLK   Tah         (-Th)    -0.190   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/shift_through_reg<7>
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/Mmux_ADDR_PHASE_ST_ALMOST_READY2_ST_MUX_10777_o11
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/AddressPhase
    -------------------------------------------------  ---------------------------
    Total                                      0.422ns (0.390ns logic, 0.032ns route)
                                                       (92.4% logic, 7.6% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST (SLICE_X110Y168.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.430ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST (FF)
  Destination:          cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.430ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST to cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X110Y168.AQ    Tcko                  0.200   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST
    SLICE_X110Y168.A6    net (fanout=15)       0.040   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST
    SLICE_X110Y168.CLK   Tah         (-Th)    -0.190   cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST_rstpot
                                                       cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Pre_SYSRST
    -------------------------------------------------  ---------------------------
    Total                                      0.430ns (0.390ns logic, 0.040ns route)
                                                       (90.7% logic, 9.3% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_infrastructure_inst_mcb_drp_clk_bufg_in
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_infrastructure_inst_mcb_drp_clk_bufg_in"
        TS_ddr_clk_buf / 0.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 10.270ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 1.730ns (578.035MHz) (Tbcper_I)
  Physical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_infrastructure_inst/U_BUFG_CLK1/I0
  Logical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_infrastructure_inst/U_BUFG_CLK1/I0
  Location pin: BUFGMUX_X3Y13.I0
  Clock network: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_infrastructure_inst/mcb_drp_clk_bufg_in
--------------------------------------------------------------------------------
Slack: 11.000ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 1.000ns (1000.000MHz) (Tmcbcper_UICLK)
  Physical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/samc_0/UICLK
  Logical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/samc_0/UICLK
  Location pin: MCB_X1Y3.UICLK
  Clock network: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk
--------------------------------------------------------------------------------
Slack: 11.570ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 0.430ns (2325.581MHz) (Tcp)
  Physical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/counter_dec<3>/CLK
  Logical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/counter_dec_0/CK
  Location pin: SLICE_X118Y169.CLK
  Clock network: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_mcb_drp_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl
_memc5_infrastructure_inst_clk_2x_180         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m
emc5_infrastructure_inst_clk_2x_180"         TS_ddr_clk_buf / 2 PHASE 0.75 ns 
HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_infrastructure_inst_clk_2x_180
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_infrastructure_inst_clk_2x_180"
        TS_ddr_clk_buf / 2 PHASE 0.75 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Logical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Location pin: MCB_X1Y3.PLLCLK1
  Clock network: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_sysclk_2x_180
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl
_memc5_infrastructure_inst_clk_2x_0         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m
emc5_infrastructure_inst_clk_2x_0"         TS_ddr_clk_buf / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_infrastructure_inst_clk_2x_0
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_infrastructure_inst_clk_2x_0"
        TS_ddr_clk_buf / 2 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Logical resource: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Location pin: MCB_X1Y3.PLLCLK0
  Clock network: cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/c5_sysclk_2x
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf 
= PERIOD TIMEGRP         
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf"         
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH         
50%;

 53953 paths analyzed, 2484 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.704ns.
--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3 (SLICE_X32Y166.AX), 35 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.296ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_15 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.602ns (Levels of Logic = 1)
  Clock Path Skew:      -0.021ns (0.233 - 0.254)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_15 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y172.DQ     Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset<15>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_15
    DSP48_X1Y41.B15      net (fanout=1)        2.733   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset<15>
    DSP48_X1Y41.M18      Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X32Y166.AX     net (fanout=1)        0.961   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_t<18>
    SLICE_X32Y166.CLK    Tdick                 0.136   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3
    -------------------------------------------------  ---------------------------
    Total                                      7.602ns (3.908ns logic, 3.694ns route)
                                                       (51.4% logic, 48.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.416ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_6 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.486ns (Levels of Logic = 1)
  Clock Path Skew:      -0.017ns (0.233 - 0.250)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_6 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y170.CQ     Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset<7>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_6
    DSP48_X1Y41.B6       net (fanout=1)        2.617   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset<6>
    DSP48_X1Y41.M18      Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X32Y166.AX     net (fanout=1)        0.961   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_t<18>
    SLICE_X32Y166.CLK    Tdick                 0.136   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3
    -------------------------------------------------  ---------------------------
    Total                                      7.486ns (3.908ns logic, 3.578ns route)
                                                       (52.2% logic, 47.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.472ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_9 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.428ns (Levels of Logic = 1)
  Clock Path Skew:      -0.019ns (0.233 - 0.252)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_9 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y171.BQ     Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset<11>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_9
    DSP48_X1Y41.B9       net (fanout=1)        2.559   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset<9>
    DSP48_X1Y41.M18      Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X32Y166.AX     net (fanout=1)        0.961   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_t<18>
    SLICE_X32Y166.CLK    Tdick                 0.136   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_3
    -------------------------------------------------  ---------------------------
    Total                                      7.428ns (3.908ns logic, 3.520ns route)
                                                       (52.6% logic, 47.4% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4 (SLICE_X32Y174.AX), 35 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.307ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_13 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.598ns (Levels of Logic = 1)
  Clock Path Skew:      -0.014ns (0.243 - 0.257)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_13 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X48Y174.BQ     Tcko                  0.447   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset<15>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_13
    DSP48_X1Y43.B13      net (fanout=1)        2.690   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset<13>
    DSP48_X1Y43.M19      Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X32Y174.AX     net (fanout=1)        0.961   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_t<19>
    SLICE_X32Y174.CLK    Tdick                 0.136   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4
    -------------------------------------------------  ---------------------------
    Total                                      7.598ns (3.947ns logic, 3.651ns route)
                                                       (51.9% logic, 48.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.342ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_16 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.562ns (Levels of Logic = 1)
  Clock Path Skew:      -0.015ns (0.243 - 0.258)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_16 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X48Y175.AQ     Tcko                  0.447   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset<16>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_16
    DSP48_X1Y43.B17      net (fanout=2)        2.654   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset<16>
    DSP48_X1Y43.M19      Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X32Y174.AX     net (fanout=1)        0.961   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_t<19>
    SLICE_X32Y174.CLK    Tdick                 0.136   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4
    -------------------------------------------------  ---------------------------
    Total                                      7.562ns (3.947ns logic, 3.615ns route)
                                                       (52.2% logic, 47.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.342ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_16 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.562ns (Levels of Logic = 1)
  Clock Path Skew:      -0.015ns (0.243 - 0.258)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_16 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X48Y175.AQ     Tcko                  0.447   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset<16>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset_16
    DSP48_X1Y43.B16      net (fanout=2)        2.654   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/data_offset<16>
    DSP48_X1Y43.M19      Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X32Y174.AX     net (fanout=1)        0.961   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_t<19>
    SLICE_X32Y174.CLK    Tdick                 0.136   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/product_4
    -------------------------------------------------  ---------------------------
    Total                                      7.562ns (3.947ns logic, 3.615ns route)
                                                       (52.2% logic, 47.8% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 (RAMB8_X3Y75.DIADI4), 4 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.405ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_test_en_o (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Requirement:          8.000ns
  Data Path Delay:      7.219ns (Levels of Logic = 1)
  Clock Path Skew:      -0.295ns (0.608 - 0.903)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_test_en_o to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X65Y167.BQ     Tcko                  0.391   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_test_en_o
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_test_en_o
    SLICE_X100Y144.A4    net (fanout=64)       5.051   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_test_en_o
    SLICE_X100Y144.A     Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din<45>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_sync_fifo_din<40>11
    RAMB8_X3Y75.DIADI4   net (fanout=1)        1.274   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din<40>
    RAMB8_X3Y75.CLKAWRCLKTrdck_DIA             0.300   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
    -------------------------------------------------  ---------------------------
    Total                                      7.219ns (0.894ns logic, 6.325ns route)
                                                       (12.4% logic, 87.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.246ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Requirement:          8.000ns
  Data Path Delay:      6.371ns (Levels of Logic = 1)
  Clock Path Skew:      -0.302ns (0.608 - 0.910)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X67Y164.AQ     Tcko                  0.391   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o
    SLICE_X100Y144.A1    net (fanout=65)       4.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o
    SLICE_X100Y144.A     Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din<45>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_sync_fifo_din<40>11
    RAMB8_X3Y75.DIADI4   net (fanout=1)        1.274   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din<40>
    RAMB8_X3Y75.CLKAWRCLKTrdck_DIA             0.300   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
    -------------------------------------------------  ---------------------------
    Total                                      6.371ns (0.894ns logic, 5.477ns route)
                                                       (14.0% logic, 86.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.340ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[2].cmp_offset_gain_calibr/data_o_8 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Requirement:          8.000ns
  Data Path Delay:      3.552ns (Levels of Logic = 1)
  Clock Path Skew:      -0.027ns (0.608 - 0.635)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[2].cmp_offset_gain_calibr/data_o_8 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X94Y143.BQ     Tcko                  0.447   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[2].cmp_offset_gain_calibr/data_o<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[2].cmp_offset_gain_calibr/data_o_8
    SLICE_X100Y144.A2    net (fanout=3)        1.328   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[2].cmp_offset_gain_calibr/data_o<8>
    SLICE_X100Y144.A     Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din<45>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_sync_fifo_din<40>11
    RAMB8_X3Y75.DIADI4   net (fanout=1)        1.274   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din<40>
    RAMB8_X3Y75.CLKAWRCLKTrdck_DIA             0.300   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
    -------------------------------------------------  ---------------------------
    Total                                      3.552ns (0.950ns logic, 2.602ns route)
                                                       (26.7% logic, 73.3% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf"
        TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH
        50%;
--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse (SLICE_X69Y180.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.438ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.438ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X69Y180.AQ     Tcko                  0.198   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_pulse_sync_reg<1>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse
    SLICE_X69Y180.A6     net (fanout=2)        0.025   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse
    SLICE_X69Y180.CLK    Tah         (-Th)    -0.215   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_pulse_sync_reg<1>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse_PWR_125_o_MUX_10372_o1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse
    -------------------------------------------------  ---------------------------
    Total                                      0.438ns (0.413ns logic, 0.025ns route)
                                                       (94.3% logic, 5.7% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o (SLICE_X67Y164.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.443ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_sync1 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.445ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.038 - 0.036)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_sync1 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X66Y164.BQ     Tcko                  0.200   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_sync1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_sync1
    SLICE_X67Y164.AX     net (fanout=1)        0.186   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_sync1
    SLICE_X67Y164.CLK    Tckdi       (-Th)    -0.059   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_sel_o
    -------------------------------------------------  ---------------------------
    Total                                      0.445ns (0.259ns logic, 0.186ns route)
                                                       (58.2% logic, 41.8% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o (SLICE_X51Y153.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.447ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_sync1 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.447ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_sync1 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X51Y153.BQ     Tcko                  0.198   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_sync1
    SLICE_X51Y153.DX     net (fanout=1)        0.190   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_sync1
    SLICE_X51Y153.CLK    Tckdi       (-Th)    -0.059   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o
    -------------------------------------------------  ---------------------------
    Total                                      0.447ns (0.257ns logic, 0.190ns route)
                                                       (57.5% logic, 42.5% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf"
        TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH
        50%;
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Location pin: RAMB8_X3Y84.CLKAWRCLK
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2/CLKAWRCLK
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2/CLKAWRCLK
  Location pin: RAMB8_X3Y75.CLKAWRCLK
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------
Slack: 5.780ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 2.220ns (450.450MHz) (Tdspper_CARRYINREG_CARRYOUTREG)
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3/CLK
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3/CLK
  Location pin: DSP48_X1Y43.CLK
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_serdes_clk 
= PERIOD TIMEGRP         
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_serdes_clk"         
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk / 2 HIGH         50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_fs_clk_buf 
= PERIOD TIMEGRP         
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_fs_clk_buf"         
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH         
50%;

 53971 paths analyzed, 2484 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.546ns.
--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave (ILOGIC_X6Y2.BITSLIP), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.454ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.611ns (Levels of Logic = 1)
  Clock Path Skew:      0.146ns (0.959 - 0.813)
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y51.AQ      Tcko                  0.447   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
    SLICE_X45Y35.C1      net (fanout=1)        1.683   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
    SLICE_X45Y35.CMUX    Tilo                  0.313   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_acq_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip1
    ILOGIC_X6Y2.BITSLIP  net (fanout=18)       5.009   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip
    ILOGIC_X6Y2.CLKDIV   Tiscck_BITSLIP        0.159   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave
    -------------------------------------------------  ---------------------------
    Total                                      7.611ns (0.919ns logic, 6.692ns route)
                                                       (12.1% logic, 87.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.742ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.246ns (Levels of Logic = 1)
  Clock Path Skew:      0.069ns (0.959 - 0.890)
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X34Y23.CQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
    SLICE_X45Y35.C5      net (fanout=1)        1.357   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
    SLICE_X45Y35.CMUX    Tilo                  0.313   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_acq_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip1
    ILOGIC_X6Y2.BITSLIP  net (fanout=18)       5.009   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip
    ILOGIC_X6Y2.CLKDIV   Tiscck_BITSLIP        0.159   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave
    -------------------------------------------------  ---------------------------
    Total                                      7.246ns (0.880ns logic, 6.366ns route)
                                                       (12.1% logic, 87.9% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master (ILOGIC_X6Y3.BITSLIP), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.454ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.611ns (Levels of Logic = 1)
  Clock Path Skew:      0.146ns (0.959 - 0.813)
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y51.AQ      Tcko                  0.447   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
    SLICE_X45Y35.C1      net (fanout=1)        1.683   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
    SLICE_X45Y35.CMUX    Tilo                  0.313   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_acq_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip1
    ILOGIC_X6Y3.BITSLIP  net (fanout=18)       5.009   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip
    ILOGIC_X6Y3.CLKDIV   Tiscck_BITSLIP        0.159   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master
    -------------------------------------------------  ---------------------------
    Total                                      7.611ns (0.919ns logic, 6.692ns route)
                                                       (12.1% logic, 87.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.742ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.246ns (Levels of Logic = 1)
  Clock Path Skew:      0.069ns (0.959 - 0.890)
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X34Y23.CQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
    SLICE_X45Y35.C5      net (fanout=1)        1.357   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
    SLICE_X45Y35.CMUX    Tilo                  0.313   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_acq_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip1
    ILOGIC_X6Y3.BITSLIP  net (fanout=18)       5.009   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip
    ILOGIC_X6Y3.CLKDIV   Tiscck_BITSLIP        0.159   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_master
    -------------------------------------------------  ---------------------------
    Total                                      7.246ns (0.880ns logic, 6.366ns route)
                                                       (12.1% logic, 87.9% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master (ILOGIC_X7Y1.BITSLIP), 2 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.658ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.407ns (Levels of Logic = 1)
  Clock Path Skew:      0.146ns (0.959 - 0.813)
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y51.AQ      Tcko                  0.447   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
    SLICE_X45Y35.C1      net (fanout=1)        1.683   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_ctl_man_bitslip_o
    SLICE_X45Y35.CMUX    Tilo                  0.313   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_acq_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip1
    ILOGIC_X7Y1.BITSLIP  net (fanout=18)       4.805   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip
    ILOGIC_X7Y1.CLKDIV   Tiscck_BITSLIP        0.159   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master
    -------------------------------------------------  ---------------------------
    Total                                      7.407ns (0.919ns logic, 6.488ns route)
                                                       (12.4% logic, 87.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.946ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.042ns (Levels of Logic = 1)
  Clock Path Skew:      0.069ns (0.959 - 0.890)
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X34Y23.CQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
    SLICE_X45Y35.C5      net (fanout=1)        1.357   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
    SLICE_X45Y35.CMUX    Tilo                  0.313   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_acq_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip1
    ILOGIC_X7Y1.BITSLIP  net (fanout=18)       4.805   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/serdes_bitslip
    ILOGIC_X7Y1.CLKDIV   Tiscck_BITSLIP        0.159   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[4].iserdes2_master
    -------------------------------------------------  ---------------------------
    Total                                      7.042ns (0.880ns logic, 6.162ns route)
                                                       (12.5% logic, 87.5% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_fs_clk_buf = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_fs_clk_buf"
        TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH
        50%;
--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_1 (SLICE_X73Y34.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.399ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_0 (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.399ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_0 to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X73Y34.AQ      Tcko                  0.198   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_pulse_sync_reg<1>
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_0
    SLICE_X73Y34.BX      net (fanout=2)        0.142   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_0
    SLICE_X73Y34.CLK     Tckdi       (-Th)    -0.059   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_pulse_sync_reg<1>
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_1
    -------------------------------------------------  ---------------------------
    Total                                      0.399ns (0.257ns logic, 0.142ns route)
                                                       (64.4% logic, 35.6% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_gray_2 (SLICE_X46Y38.C5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.403ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin_3 (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_gray_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.403ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin_3 to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_gray_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y38.CQ      Tcko                  0.200   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin<3>
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin_3
    SLICE_X46Y38.C5      net (fanout=7)        0.082   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin<3>
    SLICE_X46Y38.CLK     Tah         (-Th)    -0.121   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin<3>
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mxor_wcb_gray_next<3:0>_2_xo<0>1
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_gray_2
    -------------------------------------------------  ---------------------------
    Total                                      0.403ns (0.321ns logic, 0.082ns route)
                                                       (79.7% logic, 20.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_o (SLICE_X70Y47.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.415ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_sync1 (FF)
  Destination:          cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_o (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.431ns (Levels of Logic = 0)
  Clock Path Skew:      0.016ns (0.354 - 0.338)
  Source Clock:         cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_sync1 to cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_o
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X71Y48.BQ      Tcko                  0.198   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_sync1
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_sync1
    SLICE_X70Y47.DX      net (fanout=1)        0.185   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_sync1
    SLICE_X70Y47.CLK     Tckdi       (-Th)    -0.048   cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_o
                                                       cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_o
    -------------------------------------------------  ---------------------------
    Total                                      0.431ns (0.246ns logic, 0.185ns route)
                                                       (57.1% logic, 42.9% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_fs_clk_buf = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_fs_clk_buf"
        TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH
        50%;
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Location pin: RAMB8_X3Y29.CLKAWRCLK
  Clock network: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2/CLKAWRCLK
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2/CLKAWRCLK
  Location pin: RAMB8_X3Y22.CLKAWRCLK
  Clock network: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------
Slack: 5.780ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 2.220ns (450.450MHz) (Tdspper_CARRYINREG_CARRYOUTREG)
  Physical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3/CLK
  Logical resource: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3/CLK
  Location pin: DSP48_X1Y6.CLK
  Clock network: cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_serdes_clk 
= PERIOD TIMEGRP         
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_serdes_clk"         
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_dco_clk / 2 HIGH         50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_clk_20m_vcxo_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_20m_vcxo_i              |     50.000ns|     20.000ns|     49.967ns|            0|            0|            0|      2532520|
| TS_sys_clk_62_5_buf           |     16.000ns|     15.723ns|          N/A|            0|            0|      1756234|            0|
| TS_sys_clk_125_buf            |      8.000ns|      7.767ns|          N/A|            0|            0|       755348|            0|
| TS_ddr_clk_buf                |      3.000ns|      2.572ns|      2.998ns|            0|            0|            6|        20932|
|  TS_cmp_ddr_ctrl_bank4_cmp_ddr|     12.000ns|      6.867ns|          N/A|            0|            0|        10471|            0|
|  3_ctrl_wrapper_gen_svec_bank4|             |             |             |             |             |             |             |
|  _64b_32b_cmp_ddr3_ctrl_memc4_|             |             |             |             |             |             |             |
|  infrastructure_inst_mcb_drp_c|             |             |             |             |             |             |             |
|  lk_bufg_in                   |             |             |             |             |             |             |             |
|  TS_cmp_ddr_ctrl_bank4_cmp_ddr|      1.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  3_ctrl_wrapper_gen_svec_bank4|             |             |             |             |             |             |             |
|  _64b_32b_cmp_ddr3_ctrl_memc4_|             |             |             |             |             |             |             |
|  infrastructure_inst_clk_2x_18|             |             |             |             |             |             |             |
|  0                            |             |             |             |             |             |             |             |
|  TS_cmp_ddr_ctrl_bank4_cmp_ddr|      1.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  3_ctrl_wrapper_gen_svec_bank4|             |             |             |             |             |             |             |
|  _64b_32b_cmp_ddr3_ctrl_memc4_|             |             |             |             |             |             |             |
|  infrastructure_inst_clk_2x_0 |             |             |             |             |             |             |             |
|  TS_cmp_ddr_ctrl_bank5_cmp_ddr|     12.000ns|      7.066ns|          N/A|            0|            0|        10461|            0|
|  3_ctrl_wrapper_gen_svec_bank5|             |             |             |             |             |             |             |
|  _64b_32b_cmp_ddr3_ctrl_memc5_|             |             |             |             |             |             |             |
|  infrastructure_inst_mcb_drp_c|             |             |             |             |             |             |             |
|  lk_bufg_in                   |             |             |             |             |             |             |             |
|  TS_cmp_ddr_ctrl_bank5_cmp_ddr|      1.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  3_ctrl_wrapper_gen_svec_bank5|             |             |             |             |             |             |             |
|  _64b_32b_cmp_ddr3_ctrl_memc5_|             |             |             |             |             |             |             |
|  infrastructure_inst_clk_2x_18|             |             |             |             |             |             |             |
|  0                            |             |             |             |             |             |             |             |
|  TS_cmp_ddr_ctrl_bank5_cmp_ddr|      1.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  3_ctrl_wrapper_gen_svec_bank5|             |             |             |             |             |             |             |
|  _64b_32b_cmp_ddr3_ctrl_memc5_|             |             |             |             |             |             |             |
|  infrastructure_inst_clk_2x_0 |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_adc0_dco_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc0_dco_n_i                |      2.000ns|      0.925ns|      1.926ns|            0|            0|            0|        53953|
| TS_cmp_fmc_adc_mezzanine_0_cmp|      2.000ns|      1.636ns|      1.926ns|            0|            0|            0|        53953|
| _fmc_adc_100Ms_core_dco_clk   |             |             |             |             |             |             |             |
|  TS_cmp_fmc_adc_mezzanine_0_cm|      8.000ns|      7.704ns|          N/A|            0|            0|        53953|            0|
|  p_fmc_adc_100Ms_core_fs_clk_b|             |             |             |             |             |             |             |
|  uf                           |             |             |             |             |             |             |             |
|  TS_cmp_fmc_adc_mezzanine_0_cm|      1.000ns|          N/A|          N/A|            0|            0|            0|            0|
|  p_fmc_adc_100Ms_core_serdes_c|             |             |             |             |             |             |             |
|  lk                           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_adc1_dco_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc1_dco_n_i                |      2.000ns|      0.925ns|      1.887ns|            0|            0|            0|        53971|
| TS_cmp_fmc_adc_mezzanine_1_cmp|      2.000ns|      1.636ns|      1.887ns|            0|            0|            0|        53971|
| _fmc_adc_100Ms_core_dco_clk   |             |             |             |             |             |             |             |
|  TS_cmp_fmc_adc_mezzanine_1_cm|      8.000ns|      7.546ns|          N/A|            0|            0|        53971|            0|
|  p_fmc_adc_100Ms_core_fs_clk_b|             |             |             |             |             |             |             |
|  uf                           |             |             |             |             |             |             |             |
|  TS_cmp_fmc_adc_mezzanine_1_cm|      1.000ns|          N/A|          N/A|            0|            0|            0|            0|
|  p_fmc_adc_100Ms_core_serdes_c|             |             |             |             |             |             |             |
|  lk                           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock adc0_dco_n_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
adc0_dco_n_i   |    7.704|         |         |         |
adc0_dco_p_i   |    7.704|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock adc0_dco_p_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
adc0_dco_n_i   |    7.704|         |         |         |
adc0_dco_p_i   |    7.704|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock adc1_dco_n_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
adc1_dco_n_i   |    7.546|         |         |         |
adc1_dco_p_i   |    7.546|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock adc1_dco_p_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
adc1_dco_n_i   |    7.546|         |         |         |
adc1_dco_p_i   |    7.546|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock clk_20m_vcxo_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_20m_vcxo_i |   15.723|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 2640444 paths, 0 nets, and 62719 connections

Design statistics:
   Minimum period:  20.000ns{1}   (Maximum frequency:  50.000MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Fri Apr 25 16:51:07 2014 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 420 MB



