#ChipScope Core Inserter Project File Version 3.0
#Wed Nov 16 15:47:52 CET 2011
Project.device.designInputFile=/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/syn/spec_top_fmc_adc_100Ms_cs.ngc
Project.device.designOutputFile=/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/syn/spec_top_fmc_adc_100Ms_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/syn/_ngo
Project.device.useSRL16=true
Project.filter.dimension=16
Project.filter<0>=*wb_ddr_we*
Project.filter<10>=*wb_ddr_*
Project.filter<11>=*wb_ddr_fifo*
Project.filter<12>=*ram_addr_cnt*
Project.filter<13>=*acq*
Project.filter<14>=*stop*
Project.filter<15>=*clk*
Project.filter<1>=*wb*cyc*
Project.filter<2>=*wb_ddr_cyc*
Project.filter<3>=*wb_dd_cyc*
Project.filter<4>=
Project.filter<5>=*pre*
Project.filter<6>=*post*
Project.filter<7>=*samples_wr*
Project.filter<8>=*sample_wr*
Project.filter<9>=*singl*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=sys_clk_125
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=cmp_fmc_adc_100Ms_core/acq_start
Project.unit<0>.dataChannel<100>=cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
Project.unit<0>.dataChannel<101>=cmp_fmc_adc_100Ms_core/wb_ddr_stall_t
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Project.unit<0>.dataChannel<103>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<0>
Project.unit<0>.dataChannel<104>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<1>
Project.unit<0>.dataChannel<105>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<2>
Project.unit<0>.dataChannel<106>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<3>
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