Welcome to Xilinx CORE Generator.
Help system initialized.
Opening project file
/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/coregen.cgp.
Project, 'coregen', initialised from file
'/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/coregen.cgp'.
Recustomize and Generate (Under Original Project Settings)Customizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
Initializing IP model...
Finished initialising IP model.
Cancelled Customization.
Recustomize and Generate (Under Original Project Settings)Customizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
Initializing IP model...
Finished initialising IP model.
Finished Customizing.
Generating IP...
WARNING:sim:89 - A core named <wb_ddr_fifo> already exists in the output
   directory. Output products for this core may be overwritten.
Initializing IP model...
Finished initialising IP model.
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Partition Report
XST: Design Summary
Generating Implementation files.
Generating ISE symbol file...
Generating NGC file.
Finished Generation Stage.
Generating IP instantiation template...
Generating the VHDL instantiation template.
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
Launching readme viewer...
Launched readme viewer.
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.
Recustomize and Generate (Under Original Project Settings)Customizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
Initializing IP model...
Finished initialising IP model.
Cancelled Customization.
Closed project file.
