--------------------------------------------------------------------------------
Release 13.3 Trace  (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

/opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 3 -n 3
-fastpaths -xml spec_top_fmc_adc_100Ms.twx spec_top_fmc_adc_100Ms.ncd -o
spec_top_fmc_adc_100Ms.twr spec_top_fmc_adc_100Ms.pcf

Design file:              spec_top_fmc_adc_100Ms.ncd
Physical constraint file: spec_top_fmc_adc_100Ms.pcf
Device,package,speed:     xc6slx45t,fgg484,C,-3 (PRODUCTION 1.20 2011-10-03)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_grp" 5 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   0.925ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_grp" 5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.075ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
  Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
  Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
  Location pin: BUFIO2_X4Y21.I
  Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   0.925ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.075ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
  Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
  Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
  Location pin: BUFIO2_X4Y21.I
  Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clk20_vcxo_i = PERIOD TIMEGRP "clk20_vcxo_i_grp" 50 ns 
HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is  20.000ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk20_vcxo_i = PERIOD TIMEGRP "clk20_vcxo_i_grp" 50 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 2.630ns (max period limit - period)
  Period: 50.000ns
  Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKIN)
  Physical resource: cmp_sys_clk_pll/PLL_ADV/CLKIN1
  Logical resource: cmp_sys_clk_pll/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y3.CLKIN2
  Clock network: cmp_sys_clk_pll/PLL_ADV_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 2.630ns (max period limit - period)
  Period: 50.000ns
  Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKFB)
  Physical resource: cmp_sys_clk_pll/PLL_ADV/CLKFBOUT
  Logical resource: cmp_sys_clk_pll/PLL_ADV/CLKFBOUT
  Location pin: PLL_ADV_X0Y3.CLKFBOUT
  Clock network: sys_clk_fb
--------------------------------------------------------------------------------
Slack: 7.075ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_sys_clk_pll/PLL_ADV/CLKOUT0
  Logical resource: cmp_sys_clk_pll/PLL_ADV/CLKOUT0
  Location pin: PLL_ADV_X0Y3.CLKOUT0
  Clock network: sys_clk_125_buf
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_SYS_CLK5 = PERIOD TIMEGRP "SYS_CLK5" 3 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.572ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_SYS_CLK5 = PERIOD TIMEGRP "SYS_CLK5" 3 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.428ns (period - (min low pulse limit / (low pulse / period)))
  Period: 3.000ns
  Low pulse: 1.500ns
  Low pulse limit: 1.286ns (Tdcmpw_CLKIN_300_350)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg
--------------------------------------------------------------------------------
Slack: 0.428ns (period - (min high pulse limit / (high pulse / period)))
  Period: 3.000ns
  High pulse: 1.500ns
  High pulse limit: 1.286ns (Tdcmpw_CLKIN_300_350)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg
--------------------------------------------------------------------------------
Slack: 0.575ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Location pin: PLL_ADV_X0Y0.CLKOUT0
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/clk_2x_0
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_adc_dco_n_i = PERIOD TIMEGRP "adc_dco_n_i" 2 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   0.925ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_adc_dco_n_i = PERIOD TIMEGRP "adc_dco_n_i" 2 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.075ns (period - min period limit)
  Period: 2.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_dco_bufio/I
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_dco_bufio/I
  Location pin: BUFIO2_X1Y6.I
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dco_clk_buf
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP     
    "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.800ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.575ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
  Location pin: PLL_ADV_X0Y2.CLKOUT0
  Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.000ns
  Low pulse: 2.500ns
  Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Location pin: PLL_ADV_X0Y2.CLKIN1
  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.000ns
  High pulse: 2.500ns
  High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Location pin: PLL_ADV_X0Y2.CLKIN1
  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP   
      "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.800ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.575ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
  Location pin: PLL_ADV_X0Y2.CLKOUT0
  Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.000ns
  Low pulse: 2.500ns
  Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Location pin: PLL_ADV_X0Y2.CLKIN1
  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.000ns
  High pulse: 2.500ns
  High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Location pin: PLL_ADV_X0Y2.CLKIN1
  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_clk_125_buf" 
TS_clk20_vcxo_i / 6.25         HIGH 50%;

 387949 paths analyzed, 15754 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.901ns.
--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8 (SLICE_X4Y45.CE), 5 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.099ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.785ns (Levels of Logic = 1)
  Clock Path Skew:      -0.011ns (0.242 - 0.253)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X1Y36.AQ       Tcko                  0.391   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
    SLICE_X34Y33.A4      net (fanout=35)       3.768   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
    SLICE_X34Y33.A       Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_GND_383_o_acq_trig_mux_114_OUT6111
    SLICE_X4Y45.CE       net (fanout=22)       3.088   trig_irq_p
    SLICE_X4Y45.CLK      Tceck                 0.335   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8
    -------------------------------------------------  ---------------------------
    Total                                      7.785ns (0.929ns logic, 6.856ns route)
                                                       (11.9% logic, 88.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.018ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.870ns (Levels of Logic = 1)
  Clock Path Skew:      -0.007ns (0.242 - 0.249)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB8_X1Y18.DOBDO12  Trcko_DOB             1.850   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
    SLICE_X34Y33.A6      net (fanout=28)       1.394   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout<64>
    SLICE_X34Y33.A       Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_GND_383_o_acq_trig_mux_114_OUT6111
    SLICE_X4Y45.CE       net (fanout=22)       3.088   trig_irq_p
    SLICE_X4Y45.CLK      Tceck                 0.335   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8
    -------------------------------------------------  ---------------------------
    Total                                      6.870ns (2.388ns logic, 4.482ns route)
                                                       (34.8% logic, 65.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.036ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.857ns (Levels of Logic = 1)
  Clock Path Skew:      -0.002ns (0.242 - 0.244)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y39.AQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd2
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1
    SLICE_X34Y33.A2      net (fanout=139)      2.823   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1
    SLICE_X34Y33.A       Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_GND_383_o_acq_trig_mux_114_OUT6111
    SLICE_X4Y45.CE       net (fanout=22)       3.088   trig_irq_p
    SLICE_X4Y45.CLK      Tceck                 0.335   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_8
    -------------------------------------------------  ---------------------------
    Total                                      6.857ns (0.946ns logic, 5.911ns route)
                                                       (13.8% logic, 86.2% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84 (SLICE_X22Y35.A2), 1647 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.100ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.765ns (Levels of Logic = 6)
  Clock Path Skew:      -0.030ns (0.481 - 0.511)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1 to cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y30.DQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
    SLICE_X24Y31.A4      net (fanout=3)        1.110   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
    SLICE_X24Y31.BMUX    Topab                 0.434   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_A11
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
    SLICE_X24Y36.C4      net (fanout=36)       1.316   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos<1>
    SLICE_X24Y36.C       Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_122
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_122
    SLICE_X24Y36.A1      net (fanout=1)        0.451   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_122
    SLICE_X24Y36.A       Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_122
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_8
    SLICE_X28Y32.C3      net (fanout=1)        0.738   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_8
    SLICE_X28Y32.CMUX    Tilo                  0.343   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_7
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_2_f7
    SLICE_X19Y36.D4      net (fanout=7)        1.106   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos[6]_data[127]_Mux_20_o
    SLICE_X19Y36.D       Tilo                  0.259   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk13
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk1_4
    SLICE_X22Y35.A2      net (fanout=19)       0.901   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk13
    SLICE_X22Y35.CLK     Tas                   0.289   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84_rstpot
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
    -------------------------------------------------  ---------------------------
    Total                                      7.765ns (2.143ns logic, 5.622ns route)
                                                       (27.6% logic, 72.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.102ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.763ns (Levels of Logic = 6)
  Clock Path Skew:      -0.030ns (0.481 - 0.511)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1 to cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y30.DQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
    SLICE_X24Y31.A4      net (fanout=3)        1.110   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
    SLICE_X24Y31.BMUX    Topab                 0.432   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_lut<0>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
    SLICE_X24Y36.C4      net (fanout=36)       1.316   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos<1>
    SLICE_X24Y36.C       Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_122
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_122
    SLICE_X24Y36.A1      net (fanout=1)        0.451   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_122
    SLICE_X24Y36.A       Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_122
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_8
    SLICE_X28Y32.C3      net (fanout=1)        0.738   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_8
    SLICE_X28Y32.CMUX    Tilo                  0.343   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_7
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_2_f7
    SLICE_X19Y36.D4      net (fanout=7)        1.106   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos[6]_data[127]_Mux_20_o
    SLICE_X19Y36.D       Tilo                  0.259   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk13
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk1_4
    SLICE_X22Y35.A2      net (fanout=19)       0.901   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk13
    SLICE_X22Y35.CLK     Tas                   0.289   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84_rstpot
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
    -------------------------------------------------  ---------------------------
    Total                                      7.763ns (2.141ns logic, 5.622ns route)
                                                       (27.6% logic, 72.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.106ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.759ns (Levels of Logic = 6)
  Clock Path Skew:      -0.030ns (0.481 - 0.511)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1 to cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y30.DQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
    SLICE_X24Y31.A4      net (fanout=3)        1.110   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11_1
    SLICE_X24Y31.AMUX    Topaa                 0.377   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_lut<0>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<3>
    SLICE_X32Y33.C3      net (fanout=36)       1.580   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos<0>
    SLICE_X32Y33.C       Tilo                  0.205   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_12
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_144
    SLICE_X29Y31.A6      net (fanout=1)        0.648   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_144
    SLICE_X29Y31.A       Tilo                  0.259   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_137
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_82
    SLICE_X28Y32.D6      net (fanout=1)        0.279   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_82
    SLICE_X28Y32.CMUX    Topdc                 0.338   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_7
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_4
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_2_f7
    SLICE_X19Y36.D4      net (fanout=7)        1.106   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos[6]_data[127]_Mux_20_o
    SLICE_X19Y36.D       Tilo                  0.259   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk13
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk1_4
    SLICE_X22Y35.A2      net (fanout=19)       0.901   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk13
    SLICE_X22Y35.CLK     Tas                   0.289   cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84_rstpot
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_84
    -------------------------------------------------  ---------------------------
    Total                                      7.759ns (2.135ns logic, 5.624ns route)
                                                       (27.5% logic, 72.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10 (SLICE_X4Y45.CE), 5 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.120ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10 (FF)
  Requirement:          8.000ns
  Data Path Delay:      7.764ns (Levels of Logic = 1)
  Clock Path Skew:      -0.011ns (0.242 - 0.253)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X1Y36.AQ       Tcko                  0.391   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
    SLICE_X34Y33.A4      net (fanout=35)       3.768   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
    SLICE_X34Y33.A       Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_GND_383_o_acq_trig_mux_114_OUT6111
    SLICE_X4Y45.CE       net (fanout=22)       3.088   trig_irq_p
    SLICE_X4Y45.CLK      Tceck                 0.314   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10
    -------------------------------------------------  ---------------------------
    Total                                      7.764ns (0.908ns logic, 6.856ns route)
                                                       (11.7% logic, 88.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.039ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.849ns (Levels of Logic = 1)
  Clock Path Skew:      -0.007ns (0.242 - 0.249)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB8_X1Y18.DOBDO12  Trcko_DOB             1.850   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2
    SLICE_X34Y33.A6      net (fanout=28)       1.394   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout<64>
    SLICE_X34Y33.A       Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_GND_383_o_acq_trig_mux_114_OUT6111
    SLICE_X4Y45.CE       net (fanout=22)       3.088   trig_irq_p
    SLICE_X4Y45.CLK      Tceck                 0.314   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10
    -------------------------------------------------  ---------------------------
    Total                                      6.849ns (2.367ns logic, 4.482ns route)
                                                       (34.6% logic, 65.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.057ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.836ns (Levels of Logic = 1)
  Clock Path Skew:      -0.002ns (0.242 - 0.244)
  Source Clock:         sys_clk_125 rising at 0.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.196ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y39.AQ      Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd2
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1
    SLICE_X34Y33.A2      net (fanout=139)      2.823   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1
    SLICE_X34Y33.A       Tilo                  0.203   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_led_monostable/s_trigger_d
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Mmux_GND_383_o_acq_trig_mux_114_OUT6111
    SLICE_X4Y45.CE       net (fanout=22)       3.088   trig_irq_p
    SLICE_X4Y45.CLK      Tceck                 0.314   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig<10>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram_addra_trig_10
    -------------------------------------------------  ---------------------------
    Total                                      6.836ns (0.925ns logic, 5.911ns route)
                                                       (13.5% logic, 86.5% route)

--------------------------------------------------------------------------------

Hold Paths: TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_clk_125_buf" TS_clk20_vcxo_i / 6.25
        HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2 (RAMB16_X1Y36.ADDRB9), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.287ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin_4 (FF)
  Destination:          cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.288ns (Levels of Logic = 0)
  Clock Path Skew:      0.001ns (0.067 - 0.066)
  Source Clock:         sys_clk_125 rising at 8.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin_4 to cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y74.AQ      Tcko                  0.200   cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin<7>
                                                       cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin_4
    RAMB16_X1Y36.ADDRB9  net (fanout=10)       0.154   cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin<4>
    RAMB16_X1Y36.CLKB    Trckc_ADDRB (-Th)     0.066   cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2
                                                       cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2
    -------------------------------------------------  ---------------------------
    Total                                      0.288ns (0.134ns logic, 0.154ns route)
                                                       (46.5% logic, 53.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2 (RAMB16_X1Y36.ADDRB5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.304ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin_0 (FF)
  Destination:          cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.308ns (Levels of Logic = 0)
  Clock Path Skew:      0.004ns (0.067 - 0.063)
  Source Clock:         sys_clk_125 rising at 8.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin_0 to cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y73.AQ      Tcko                  0.200   cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin<3>
                                                       cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin_0
    RAMB16_X1Y36.ADDRB5  net (fanout=10)       0.174   cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rcb_bin<0>
    RAMB16_X1Y36.CLKB    Trckc_ADDRB (-Th)     0.066   cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2
                                                       cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2
    -------------------------------------------------  ---------------------------
    Total                                      0.308ns (0.134ns logic, 0.174ns route)
                                                       (43.5% logic, 56.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (MCB_X0Y1.P0WRDATA1), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.360ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data_1 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (CPU)
  Requirement:          0.000ns
  Data Path Delay:      0.366ns (Levels of Logic = 0)
  Clock Path Skew:      0.006ns (0.068 - 0.062)
  Source Clock:         sys_clk_125 rising at 8.000ns
  Destination Clock:    sys_clk_125 rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data_1 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X1Y56.BQ       Tcko                  0.198   cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data<3>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data_1
    MCB_X0Y1.P0WRDATA1   net (fanout=1)        0.123   cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data<1>
    MCB_X0Y1.P0WRCLK     Tmcbckd_WRDATA(-Th)    -0.045   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
    -------------------------------------------------  ---------------------------
    Total                                      0.366ns (0.243ns logic, 0.123ns route)
                                                       (66.4% logic, 33.6% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_clk_125_buf" TS_clk20_vcxo_i / 6.25
        HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKA
  Location pin: RAMB16_X0Y24.CLKA
  Clock network: sys_clk_125
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKB
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram1/CLKB
  Location pin: RAMB16_X0Y24.CLKB
  Clock network: sys_clk_125
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram2/CLKA
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/gen_dual_clk.U_RAM_DC/Mram_ram2/CLKA
  Location pin: RAMB16_X1Y26.CLKA
  Clock network: sys_clk_125
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_buf" 
TS_clk20_vcxo_i / 16.6666667         HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.572ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_buf" TS_clk20_vcxo_i / 16.6666667
        HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.428ns (period - (min low pulse limit / (low pulse / period)))
  Period: 3.000ns
  Low pulse: 1.500ns
  Low pulse limit: 1.286ns (Tdcmpw_CLKIN_300_350)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg
--------------------------------------------------------------------------------
Slack: 0.428ns (period - (min high pulse limit / (high pulse / period)))
  Period: 3.000ns
  High pulse: 1.500ns
  High pulse limit: 1.286ns (Tdcmpw_CLKIN_300_350)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg
--------------------------------------------------------------------------------
Slack: 0.575ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/u_pll_adv/CLKOUT0
  Location pin: PLL_ADV_X0Y0.CLKOUT0
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/clk_2x_0
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3
_infrastructure_inst_mcb_drp_clk_bufg_in         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i
nfrastructure_inst_mcb_drp_clk_bufg_in"         TS_SYS_CLK5 / 0.25 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.730ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_mcb_drp_clk_bufg_in
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_mcb_drp_clk_bufg_in"
        TS_SYS_CLK5 / 0.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 10.270ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 1.730ns (578.035MHz) (Tbcper_I)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Location pin: BUFGMUX_X2Y3.I0
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in
--------------------------------------------------------------------------------
Slack: 11.000ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 1.000ns (1000.000MHz) (Tmcbcper_UICLK)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Location pin: MCB_X0Y1.UICLK
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk
--------------------------------------------------------------------------------
Slack: 11.570ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 0.430ns (2325.581MHz) (Tcp)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter<3>/CLK
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_0/CK
  Location pin: SLICE_X16Y81.CLK
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3
_infrastructure_inst_clk_2x_180         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i
nfrastructure_inst_clk_2x_180"         TS_SYS_CLK5 / 2 PHASE 0.75 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_clk_2x_180
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_clk_2x_180"
        TS_SYS_CLK5 / 2 PHASE 0.75 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Location pin: MCB_X0Y1.PLLCLK1
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_sysclk_2x_180
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3
_infrastructure_inst_clk_2x_0         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i
nfrastructure_inst_clk_2x_0"         TS_SYS_CLK5 / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_clk_2x_0
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_clk_2x_0"
        TS_SYS_CLK5 / 2 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Location pin: MCB_X0Y1.PLLCLK0
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_sysclk_2x
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk = 
PERIOD TIMEGRP         "cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk" 
        TS_adc_dco_n_i HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.636ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk"
        TS_adc_dco_n_i HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.075ns (period - min period limit)
  Period: 1.000ns
  Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKOUT0
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKOUT0
  Location pin: PLL_ADV_X0Y1.CLKOUT0
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_clk
--------------------------------------------------------------------------------
Slack: 0.148ns (period - min period limit)
  Period: 2.000ns
  Min period limit: 1.852ns (539.957MHz) (Tpllper_CLKIN(Finmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y1.CLKIN2
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dco_clk
--------------------------------------------------------------------------------
Slack: 0.364ns (period - (min low pulse limit / (low pulse / period)))
  Period: 2.000ns
  Low pulse: 1.000ns
  Low pulse limit: 0.818ns (Tdcmpw_CLKIN_500_550)
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/PLL_ADV/CLKIN1
  Location pin: PLL_ADV_X0Y1.CLKIN2
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dco_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int = PERIOD 
TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int"         
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP  
       "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"         
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   3.124ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"
        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.876ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem1/CLKA
  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem1/CLKA
  Location pin: RAMB16_X1Y34.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------
Slack: 1.876ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2/CLKA
  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2/CLKA
  Location pin: RAMB16_X1Y36.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------
Slack: 1.876ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Location pin: RAMB8_X2Y21.CLKAWRCLK
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0 = PERIOD 
TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0"         
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD 
TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"         
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;

 29557 paths analyzed, 7858 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   4.965ns.
--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_11 (SLICE_X40Y51.D4), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.035ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_11 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.863ns (Levels of Logic = 1)
  Clock Path Skew:      -0.027ns (0.576 - 0.603)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid to cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y75.AMUX    Tshcko                0.461   cmp_gn4124_core/cmp_p2l_decode32/p2l_d_last
                                                       cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid
    SLICE_X40Y51.D4      net (fanout=76)       4.061   cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid
    SLICE_X40Y51.CLK     Tas                   0.341   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<11>
                                                       cmp_gn4124_core/cmp_wbmaster32/mux2111
                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_11
    -------------------------------------------------  ---------------------------
    Total                                      4.863ns (0.802ns logic, 4.061ns route)
                                                       (16.5% logic, 83.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_3 (SLICE_X38Y42.D6), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.051ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/cmp_p2l_decode32/target_mwr (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_3 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.815ns (Levels of Logic = 1)
  Clock Path Skew:      -0.059ns (0.546 - 0.605)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_decode32/target_mwr to cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y76.AQ      Tcko                  0.408   cmp_gn4124_core/cmp_p2l_decode32/target_mwr
                                                       cmp_gn4124_core/cmp_p2l_decode32/target_mwr
    SLICE_X38Y42.D6      net (fanout=66)       4.118   cmp_gn4124_core/cmp_p2l_decode32/target_mwr
    SLICE_X38Y42.CLK     Tas                   0.289   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<3>
                                                       cmp_gn4124_core/cmp_wbmaster32/mux3311
                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_3
    -------------------------------------------------  ---------------------------
    Total                                      4.815ns (0.697ns logic, 4.118ns route)
                                                       (14.5% logic, 85.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_61 (SLICE_X53Y55.B4), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.061ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_61 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.825ns (Levels of Logic = 1)
  Clock Path Skew:      -0.039ns (0.564 - 0.603)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid to cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_61
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y75.AMUX    Tshcko                0.461   cmp_gn4124_core/cmp_p2l_decode32/p2l_d_last
                                                       cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid
    SLICE_X53Y55.B4      net (fanout=76)       4.042   cmp_gn4124_core/cmp_p2l_decode32/p2l_d_valid
    SLICE_X53Y55.CLK     Tas                   0.322   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<63>
                                                       cmp_gn4124_core/cmp_wbmaster32/mux5711
                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_61
    -------------------------------------------------  ---------------------------
    Total                                      4.825ns (0.783ns logic, 4.042ns route)
                                                       (16.2% logic, 83.8% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[4].loop3.oserdes_m (OLOGIC_X27Y43.D1), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.042ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_4 (FF)
  Destination:          cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[4].loop3.oserdes_m (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.058ns (Levels of Logic = 0)
  Clock Path Skew:      0.016ns (0.253 - 0.237)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_4 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[4].loop3.oserdes_m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y43.AQ      Tcko                  0.421   cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<7>
                                                       cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_4
    OLOGIC_X27Y43.D1     net (fanout=1)        0.950   cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<4>
    OLOGIC_X27Y43.CLKDIV Tosckd_D    (-Th)     1.313   cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[4].loop3.oserdes_m
                                                       cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[4].loop3.oserdes_m
    -------------------------------------------------  ---------------------------
    Total                                      0.058ns (-0.892ns logic, 0.950ns route)
                                                       (-1537.9% logic, 1637.9% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m (OLOGIC_X27Y47.D1), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.045ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_10 (FF)
  Destination:          cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.061ns (Levels of Logic = 0)
  Clock Path Skew:      0.016ns (0.257 - 0.241)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_10 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y49.CQ      Tcko                  0.368   cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<11>
                                                       cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_10
    OLOGIC_X27Y47.D1     net (fanout=1)        1.006   cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<10>
    OLOGIC_X27Y47.CLKDIV Tosckd_D    (-Th)     1.313   cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m
                                                       cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m
    -------------------------------------------------  ---------------------------
    Total                                      0.061ns (-0.945ns logic, 1.006ns route)
                                                       (-1549.2% logic, 1649.2% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[15].loop3.oserdes_m (OLOGIC_X27Y39.D2), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.057ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_31 (FF)
  Destination:          cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[15].loop3.oserdes_m (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.077ns (Levels of Logic = 0)
  Clock Path Skew:      0.020ns (0.250 - 0.230)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_31 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[15].loop3.oserdes_m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y39.DQ      Tcko                  0.384   cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<31>
                                                       cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_31
    OLOGIC_X27Y39.D2     net (fanout=1)        1.015   cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<31>
    OLOGIC_X27Y39.CLKDIV Tosckd_D    (-Th)     1.322   cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[15].loop3.oserdes_m
                                                       cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[15].loop3.oserdes_m
    -------------------------------------------------  ---------------------------
    Total                                      0.077ns (-0.938ns logic, 1.015ns route)
                                                       (-1218.2% logic, 1318.2% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.876ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem1/CLKA
  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem1/CLKA
  Location pin: RAMB16_X1Y34.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------
Slack: 1.876ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2/CLKA
  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mram_mem2/CLKA
  Location pin: RAMB16_X1Y36.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------
Slack: 1.876ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Location pin: RAMB8_X2Y21.CLKAWRCLK
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3
_infrastructure_inst_mcb_drp_clk_bufg_in_0         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i
nfrastructure_inst_mcb_drp_clk_bufg_in_0"         TS_ddr_clk_buf / 0.25 HIGH 
50%;

 10400 paths analyzed, 1129 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.731ns.
--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (SLICE_X18Y82.CE), 246 paths
--------------------------------------------------------------------------------
Slack (setup path):     4.269ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.634ns (Levels of Logic = 6)
  Clock Path Skew:      -0.005ns (0.244 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.BQ      Tcko                  0.391   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_1
    SLICE_X23Y85.D1      net (fanout=11)       1.204   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<1>
    SLICE_X23Y85.D       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o3
    SLICE_X23Y85.C3      net (fanout=1)        0.624   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
    SLICE_X23Y85.C       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
    SLICE_X23Y85.A2      net (fanout=1)        0.437   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
    SLICE_X23Y85.A       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o12
    SLICE_X24Y84.D3      net (fanout=1)        0.487   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o2
    SLICE_X24Y84.D       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o21
    SLICE_X12Y84.D1      net (fanout=3)        1.195   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o
    SLICE_X12Y84.CMUX    Topdc                 0.338   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE<0>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2_F
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2
    SLICE_X17Y84.B1      net (fanout=1)        0.675   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2
    SLICE_X17Y84.B       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv3
    SLICE_X18Y82.CE      net (fanout=2)        0.711   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv
    SLICE_X18Y82.CLK     Tceck                 0.331   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      7.634ns (2.301ns logic, 5.333ns route)
                                                       (30.1% logic, 69.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.409ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_0 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.494ns (Levels of Logic = 6)
  Clock Path Skew:      -0.005ns (0.244 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_0 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.AQ      Tcko                  0.391   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_0
    SLICE_X23Y85.D3      net (fanout=10)       1.064   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<0>
    SLICE_X23Y85.D       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o3
    SLICE_X23Y85.C3      net (fanout=1)        0.624   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
    SLICE_X23Y85.C       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
    SLICE_X23Y85.A2      net (fanout=1)        0.437   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
    SLICE_X23Y85.A       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o12
    SLICE_X24Y84.D3      net (fanout=1)        0.487   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o2
    SLICE_X24Y84.D       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o21
    SLICE_X12Y84.D1      net (fanout=3)        1.195   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o
    SLICE_X12Y84.CMUX    Topdc                 0.338   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE<0>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2_F
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2
    SLICE_X17Y84.B1      net (fanout=1)        0.675   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2
    SLICE_X17Y84.B       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv3
    SLICE_X18Y82.CE      net (fanout=2)        0.711   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv
    SLICE_X18Y82.CLK     Tceck                 0.331   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      7.494ns (2.301ns logic, 5.193ns route)
                                                       (30.7% logic, 69.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.543ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.360ns (Levels of Logic = 6)
  Clock Path Skew:      -0.005ns (0.244 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.BMUX    Tshcko                0.461   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X23Y85.D6      net (fanout=12)       0.860   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X23Y85.D       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o3
    SLICE_X23Y85.C3      net (fanout=1)        0.624   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
    SLICE_X23Y85.C       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
    SLICE_X23Y85.A2      net (fanout=1)        0.437   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o11
    SLICE_X23Y85.A       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o12
    SLICE_X24Y84.D3      net (fanout=1)        0.487   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o2
    SLICE_X24Y84.D       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o21
    SLICE_X12Y84.D1      net (fanout=3)        1.195   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o
    SLICE_X12Y84.CMUX    Topdc                 0.338   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE<0>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2_F
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2
    SLICE_X17Y84.B1      net (fanout=1)        0.675   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv2
    SLICE_X17Y84.B       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv3
    SLICE_X18Y82.CE      net (fanout=2)        0.711   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1727_inv
    SLICE_X18Y82.CLK     Tceck                 0.331   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY<5>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_5
    -------------------------------------------------  ---------------------------
    Total                                      7.360ns (2.371ns logic, 4.989ns route)
                                                       (32.2% logic, 67.8% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4 (SLICE_X14Y87.CE), 160 paths
--------------------------------------------------------------------------------
Slack (setup path):     4.460ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.430ns (Levels of Logic = 6)
  Clock Path Skew:      -0.018ns (0.231 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.BMUX    Tshcko                0.461   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X14Y85.D3      net (fanout=12)       2.252   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X14Y85.D       Tilo                  0.203   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X14Y85.C4      net (fanout=1)        0.375   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X14Y85.CMUX    Tilo                  0.261   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X14Y85.A2      net (fanout=1)        0.624   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X14Y85.A       Tilo                  0.203   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X12Y83.D5      net (fanout=2)        0.693   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X12Y83.D       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_800_o_AND_2880_o
    SLICE_X12Y83.B1      net (fanout=2)        0.458   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_800_o_AND_2880_o
    SLICE_X12Y83.B       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A5      net (fanout=1)        0.169   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv2
    SLICE_X14Y87.CE      net (fanout=2)        0.785   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv
    SLICE_X14Y87.CLK     Tceck                 0.331   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<7>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4
    -------------------------------------------------  ---------------------------
    Total                                      7.430ns (2.074ns logic, 5.356ns route)
                                                       (27.9% logic, 72.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.477ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.413ns (Levels of Logic = 6)
  Clock Path Skew:      -0.018ns (0.231 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.BMUX    Tshcko                0.461   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X15Y86.D3      net (fanout=12)       2.298   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X15Y86.D       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
    SLICE_X15Y86.B2      net (fanout=1)        0.438   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
    SLICE_X15Y86.B       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o23_SW0
    SLICE_X15Y86.A5      net (fanout=1)        0.187   N492
    SLICE_X15Y86.A       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o23
    SLICE_X15Y86.C2      net (fanout=3)        0.432   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o
    SLICE_X15Y86.C       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_GND_800_o_AND_2881_o
    SLICE_X12Y83.B3      net (fanout=2)        0.866   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_GND_800_o_AND_2881_o
    SLICE_X12Y83.B       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A5      net (fanout=1)        0.169   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv2
    SLICE_X14Y87.CE      net (fanout=2)        0.785   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv
    SLICE_X14Y87.CLK     Tceck                 0.331   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<7>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4
    -------------------------------------------------  ---------------------------
    Total                                      7.413ns (2.238ns logic, 5.175ns route)
                                                       (30.2% logic, 69.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.723ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.167ns (Levels of Logic = 6)
  Clock Path Skew:      -0.018ns (0.231 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.AMUX    Tshcko                0.461   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3
    SLICE_X14Y85.D2      net (fanout=11)       1.989   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<3>
    SLICE_X14Y85.D       Tilo                  0.203   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X14Y85.C4      net (fanout=1)        0.375   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X14Y85.CMUX    Tilo                  0.261   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X14Y85.A2      net (fanout=1)        0.624   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X14Y85.A       Tilo                  0.203   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X12Y83.D5      net (fanout=2)        0.693   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X12Y83.D       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_800_o_AND_2880_o
    SLICE_X12Y83.B1      net (fanout=2)        0.458   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_800_o_AND_2880_o
    SLICE_X12Y83.B       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A5      net (fanout=1)        0.169   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv2
    SLICE_X14Y87.CE      net (fanout=2)        0.785   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv
    SLICE_X14Y87.CLK     Tceck                 0.331   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<7>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_4
    -------------------------------------------------  ---------------------------
    Total                                      7.167ns (2.074ns logic, 5.093ns route)
                                                       (28.9% logic, 71.1% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6 (SLICE_X14Y87.CE), 160 paths
--------------------------------------------------------------------------------
Slack (setup path):     4.496ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.394ns (Levels of Logic = 6)
  Clock Path Skew:      -0.018ns (0.231 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.BMUX    Tshcko                0.461   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X14Y85.D3      net (fanout=12)       2.252   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X14Y85.D       Tilo                  0.203   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X14Y85.C4      net (fanout=1)        0.375   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X14Y85.CMUX    Tilo                  0.261   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X14Y85.A2      net (fanout=1)        0.624   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X14Y85.A       Tilo                  0.203   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X12Y83.D5      net (fanout=2)        0.693   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X12Y83.D       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_800_o_AND_2880_o
    SLICE_X12Y83.B1      net (fanout=2)        0.458   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_800_o_AND_2880_o
    SLICE_X12Y83.B       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A5      net (fanout=1)        0.169   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv2
    SLICE_X14Y87.CE      net (fanout=2)        0.785   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv
    SLICE_X14Y87.CLK     Tceck                 0.295   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<7>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6
    -------------------------------------------------  ---------------------------
    Total                                      7.394ns (2.038ns logic, 5.356ns route)
                                                       (27.6% logic, 72.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.513ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.377ns (Levels of Logic = 6)
  Clock Path Skew:      -0.018ns (0.231 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.BMUX    Tshcko                0.461   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_2
    SLICE_X15Y86.D3      net (fanout=12)       2.298   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<2>
    SLICE_X15Y86.D       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
    SLICE_X15Y86.B2      net (fanout=1)        0.438   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
    SLICE_X15Y86.B       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o23_SW0
    SLICE_X15Y86.A5      net (fanout=1)        0.187   N492
    SLICE_X15Y86.A       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o23
    SLICE_X15Y86.C2      net (fanout=3)        0.432   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o
    SLICE_X15Y86.C       Tilo                  0.259   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_GND_800_o_AND_2881_o
    SLICE_X12Y83.B3      net (fanout=2)        0.866   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_LOWER_LIMIT[7]_GND_800_o_AND_2881_o
    SLICE_X12Y83.B       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A5      net (fanout=1)        0.169   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv2
    SLICE_X14Y87.CE      net (fanout=2)        0.785   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv
    SLICE_X14Y87.CLK     Tceck                 0.295   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<7>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6
    -------------------------------------------------  ---------------------------
    Total                                      7.377ns (2.202ns logic, 5.175ns route)
                                                       (29.8% logic, 70.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     4.759ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6 (FF)
  Requirement:          12.000ns
  Data Path Delay:      7.131ns (Levels of Logic = 6)
  Clock Path Skew:      -0.018ns (0.231 - 0.249)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.092ns

  Clock Uncertainty:          0.092ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.170ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y89.AMUX    Tshcko                0.461   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<6>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int_3
    SLICE_X14Y85.D2      net (fanout=11)       1.989   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Max_Value_int<3>
    SLICE_X14Y85.D       Tilo                  0.203   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X14Y85.C4      net (fanout=1)        0.375   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
    SLICE_X14Y85.CMUX    Tilo                  0.261   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X14Y85.A2      net (fanout=1)        0.624   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o11
    SLICE_X14Y85.A       Tilo                  0.203   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o1
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o12
    SLICE_X12Y83.D5      net (fanout=2)        0.693   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o2
    SLICE_X12Y83.D       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_800_o_AND_2880_o
    SLICE_X12Y83.B1      net (fanout=2)        0.458   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY[7]_GND_800_o_AND_2880_o
    SLICE_X12Y83.B       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A5      net (fanout=1)        0.169   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv1
    SLICE_X12Y83.A       Tilo                  0.205   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UILDQSINC
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv2
    SLICE_X14Y87.CE      net (fanout=2)        0.785   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/_n1685_inv
    SLICE_X14Y87.CLK     Tceck                 0.295   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY<7>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DQS_DELAY_6
    -------------------------------------------------  ---------------------------
    Total                                      7.131ns (2.038ns logic, 5.093ns route)
                                                       (28.6% logic, 71.4% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0"
        TS_ddr_clk_buf / 0.25 HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/rd_not_write_reg (SLICE_X18Y93.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.270ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/rd_not_write_reg (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.273ns (Levels of Logic = 0)
  Clock Path Skew:      0.003ns (0.042 - 0.039)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/rd_not_write_reg
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y92.DQ      Tcko                  0.234   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    SLICE_X18Y93.CE      net (fanout=15)       0.131   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    SLICE_X18Y93.CLK     Tckce       (-Th)     0.092   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/rd_not_write_reg
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/rd_not_write_reg
    -------------------------------------------------  ---------------------------
    Total                                      0.273ns (0.142ns logic, 0.131ns route)
                                                       (52.0% logic, 48.0% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_3 (SLICE_X18Y90.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.366ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.363ns (Levels of Logic = 0)
  Clock Path Skew:      -0.003ns (0.036 - 0.039)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y92.DQ      Tcko                  0.234   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    SLICE_X18Y90.CE      net (fanout=15)       0.237   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    SLICE_X18Y90.CLK     Tckce       (-Th)     0.108   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg<3>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_3
    -------------------------------------------------  ---------------------------
    Total                                      0.363ns (0.126ns logic, 0.237ns route)
                                                       (34.7% logic, 65.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_2 (SLICE_X18Y90.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.370ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 (FF)
  Destination:          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.367ns (Levels of Logic = 0)
  Clock Path Skew:      -0.003ns (0.036 - 0.039)
  Source Clock:         cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 0.000ns
  Destination Clock:    cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk rising at 12.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y92.DQ      Tcko                  0.234   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    SLICE_X18Y90.CE      net (fanout=15)       0.237   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/state_FSM_FFd8
    SLICE_X18Y90.CLK     Tckce       (-Th)     0.104   cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg<3>
                                                       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_2
    -------------------------------------------------  ---------------------------
    Total                                      0.367ns (0.130ns logic, 0.237ns route)
                                                       (35.4% logic, 64.6% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_mcb_drp_clk_bufg_in_0"
        TS_ddr_clk_buf / 0.25 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 10.270ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 1.730ns (578.035MHz) (Tbcper_I)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/U_BUFG_CLK1/I0
  Location pin: BUFGMUX_X2Y3.I0
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in
--------------------------------------------------------------------------------
Slack: 11.000ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 1.000ns (1000.000MHz) (Tmcbcper_UICLK)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/UICLK
  Location pin: MCB_X0Y1.UICLK
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk
--------------------------------------------------------------------------------
Slack: 11.570ns (period - min period limit)
  Period: 12.000ns
  Min period limit: 0.430ns (2325.581MHz) (Tcp)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter<3>/CLK
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RstCounter_0/CK
  Location pin: SLICE_X16Y81.CLK
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_mcb_drp_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3
_infrastructure_inst_clk_2x_180_0         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i
nfrastructure_inst_clk_2x_180_0"         TS_ddr_clk_buf / 2 PHASE 0.75 ns HIGH 
50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_clk_2x_180_0
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_clk_2x_180_0"
        TS_ddr_clk_buf / 2 PHASE 0.75 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK1
  Location pin: MCB_X0Y1.PLLCLK1
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_sysclk_2x_180
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3
_infrastructure_inst_clk_2x_0_0         = PERIOD TIMEGRP         
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i
nfrastructure_inst_clk_2x_0_0"         TS_ddr_clk_buf / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.499ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_clk_2x_0_0
        = PERIOD TIMEGRP
        "cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_infrastructure_inst_clk_2x_0_0"
        TS_ddr_clk_buf / 2 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.001ns (period - min period limit)
  Period: 1.500ns
  Min period limit: 1.499ns (667.111MHz) (Tmcbcper_PLLCLK)
  Physical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Logical resource: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0/PLLCLK0
  Location pin: MCB_X0Y1.PLLCLK0
  Clock network: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_sysclk_2x
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf 
= PERIOD TIMEGRP         
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf"         
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH         
50%;

 53971 paths analyzed, 2484 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.054ns.
--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7 (SLICE_X2Y14.DX), 35 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.946ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3 (DSP)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.968ns (Levels of Logic = 0)
  Clock Path Skew:      -0.005ns (0.244 - 0.249)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    DSP48_X0Y2.M22       Tdspcko_M_OPMODEREG   5.489   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X2Y14.DX       net (fanout=1)        1.393   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<22>
    SLICE_X2Y14.CLK      Tdick                 0.086   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<7>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7
    -------------------------------------------------  ---------------------------
    Total                                      6.968ns (5.575ns logic, 1.393ns route)
                                                       (80.0% logic, 20.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.628ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.285ns (Levels of Logic = 1)
  Clock Path Skew:      -0.006ns (0.244 - 0.250)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y5.DQ       Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3
    DSP48_X0Y2.B3        net (fanout=1)        1.034   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<3>
    DSP48_X0Y2.M22       Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X2Y14.DX       net (fanout=1)        1.393   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<22>
    SLICE_X2Y14.CLK      Tdick                 0.086   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<7>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7
    -------------------------------------------------  ---------------------------
    Total                                      6.285ns (3.858ns logic, 2.427ns route)
                                                       (61.4% logic, 38.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.671ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.247ns (Levels of Logic = 1)
  Clock Path Skew:      -0.001ns (0.244 - 0.245)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y7.AQ       Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<11>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8
    DSP48_X0Y2.B8        net (fanout=1)        0.996   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<8>
    DSP48_X0Y2.M22       Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X2Y14.DX       net (fanout=1)        1.393   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<22>
    SLICE_X2Y14.CLK      Tdick                 0.086   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<7>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_7
    -------------------------------------------------  ---------------------------
    Total                                      6.247ns (3.858ns logic, 2.389ns route)
                                                       (61.8% logic, 38.2% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11 (SLICE_X3Y14.D5), 35 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.970ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3 (DSP)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.944ns (Levels of Logic = 1)
  Clock Path Skew:      -0.005ns (0.244 - 0.249)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    DSP48_X0Y2.M26       Tdspcko_M_OPMODEREG   5.489   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X3Y14.D5       net (fanout=1)        1.228   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<26>
    SLICE_X3Y14.CLK      Tas                   0.227   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<26>_rt
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11
    -------------------------------------------------  ---------------------------
    Total                                      6.944ns (5.716ns logic, 1.228ns route)
                                                       (82.3% logic, 17.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.652ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.261ns (Levels of Logic = 2)
  Clock Path Skew:      -0.006ns (0.244 - 0.250)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y5.DQ       Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3
    DSP48_X0Y2.B3        net (fanout=1)        1.034   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<3>
    DSP48_X0Y2.M26       Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X3Y14.D5       net (fanout=1)        1.228   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<26>
    SLICE_X3Y14.CLK      Tas                   0.227   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<26>_rt
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11
    -------------------------------------------------  ---------------------------
    Total                                      6.261ns (3.999ns logic, 2.262ns route)
                                                       (63.9% logic, 36.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.695ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.223ns (Levels of Logic = 2)
  Clock Path Skew:      -0.001ns (0.244 - 0.245)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y7.AQ       Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<11>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8
    DSP48_X0Y2.B8        net (fanout=1)        0.996   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<8>
    DSP48_X0Y2.M26       Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X3Y14.D5       net (fanout=1)        1.228   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<26>
    SLICE_X3Y14.CLK      Tas                   0.227   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<26>_rt
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_11
    -------------------------------------------------  ---------------------------
    Total                                      6.223ns (3.999ns logic, 2.224ns route)
                                                       (64.3% logic, 35.7% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1 (SLICE_X3Y14.BX), 35 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.983ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3 (DSP)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.931ns (Levels of Logic = 0)
  Clock Path Skew:      -0.005ns (0.244 - 0.249)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    DSP48_X0Y2.M16       Tdspcko_M_OPMODEREG   5.489   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X3Y14.BX       net (fanout=1)        1.379   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<16>
    SLICE_X3Y14.CLK      Tdick                 0.063   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1
    -------------------------------------------------  ---------------------------
    Total                                      6.931ns (5.552ns logic, 1.379ns route)
                                                       (80.1% logic, 19.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.665ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.248ns (Levels of Logic = 1)
  Clock Path Skew:      -0.006ns (0.244 - 0.250)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y5.DQ       Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_3
    DSP48_X0Y2.B3        net (fanout=1)        1.034   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<3>
    DSP48_X0Y2.M16       Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X3Y14.BX       net (fanout=1)        1.379   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<16>
    SLICE_X3Y14.CLK      Tdick                 0.063   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1
    -------------------------------------------------  ---------------------------
    Total                                      6.248ns (3.835ns logic, 2.413ns route)
                                                       (61.4% logic, 38.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.708ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1 (FF)
  Requirement:          8.000ns
  Data Path Delay:      6.210ns (Levels of Logic = 1)
  Clock Path Skew:      -0.001ns (0.244 - 0.245)
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 0.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.081ns

  Clock Uncertainty:          0.081ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.144ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y7.AQ       Tcko                  0.408   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<11>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset_8
    DSP48_X0Y2.B8        net (fanout=1)        0.996   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/data_offset<8>
    DSP48_X0Y2.M16       Tdspdo_B_M            3.364   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    SLICE_X3Y14.BX       net (fanout=1)        1.379   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_t<16>
    SLICE_X3Y14.CLK      Tdick                 0.063   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[1].cmp_offset_gain_calibr/product_1
    -------------------------------------------------  ---------------------------
    Total                                      6.210ns (3.835ns logic, 2.375ns route)
                                                       (61.8% logic, 38.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf"
        TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH
        50%;
--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_1 (SLICE_X31Y14.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.399ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_0 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.399ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_0 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X31Y14.AQ      Tcko                  0.198   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_0
    SLICE_X31Y14.BX      net (fanout=2)        0.142   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_0
    SLICE_X31Y14.CLK     Tckdi       (-Th)    -0.059   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_output_pulse
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_sync_pulse_1
    -------------------------------------------------  ---------------------------
    Total                                      0.399ns (0.257ns logic, 0.142ns route)
                                                       (64.4% logic, 35.6% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_gray_2 (SLICE_X1Y35.C5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.430ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin_3 (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_gray_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.430ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin_3 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_gray_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X1Y35.CQ       Tcko                  0.198   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin_3
    SLICE_X1Y35.C5       net (fanout=7)        0.077   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin<3>
    SLICE_X1Y35.CLK      Tah         (-Th)    -0.155   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_bin<3>
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mxor_wcb_gray_next<3:0>_2_xo<0>1
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wcb_gray_2
    -------------------------------------------------  ---------------------------
    Total                                      0.430ns (0.353ns logic, 0.077ns route)
                                                       (82.1% logic, 17.9% route)

--------------------------------------------------------------------------------

Paths for end point cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o (SLICE_X37Y14.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.439ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o (FF)
  Destination:          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.439ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Destination Clock:    cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y14.DQ      Tcko                  0.198   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o
    SLICE_X37Y14.D6      net (fanout=35)       0.026   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o
    SLICE_X37Y14.CLK     Tah         (-Th)    -0.215   cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o_rstpot
                                                       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_sw_trig_wr_o
    -------------------------------------------------  ---------------------------
    Total                                      0.439ns (0.413ns logic, 0.026ns route)
                                                       (94.1% logic, 5.9% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf = PERIOD TIMEGRP
        "cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_fs_clk_buf"
        TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk / 0.25 HIGH
        50%;
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem1/CLKAWRCLK
  Location pin: RAMB8_X0Y21.CLKAWRCLK
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------
Slack: 4.876ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2/CLKAWRCLK
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2/CLKAWRCLK
  Location pin: RAMB8_X1Y18.CLKAWRCLK
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------
Slack: 5.780ns (period - min period limit)
  Period: 8.000ns
  Min period limit: 2.220ns (450.450MHz) (Tdspper_CARRYINREG_CARRYOUTREG)
  Physical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3/CLK
  Logical resource: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[0].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3/CLK
  Location pin: DSP48_X0Y4.CLK
  Clock network: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_serdes_clk 
= PERIOD TIMEGRP         
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_serdes_clk"         
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_dco_clk / 2 HIGH         50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_p2l_clkp
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkp                    |      5.000ns|      0.925ns|      3.124ns|            0|            0|            0|            0|
| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      3.124ns|            0|            0|            0|            0|
| buf_P_clk                     |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
|  _rx_pllout_xs_int            |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      3.124ns|          N/A|            0|            0|            0|            0|
|  _rx_pllout_x1                |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_p2l_clkn
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn                    |      5.000ns|      0.925ns|      4.965ns|            0|            0|            0|        29557|
| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      4.965ns|            0|            0|            0|        29557|
| buf_P_clk_0                   |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
|  _rx_pllout_xs_int_0          |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      4.965ns|          N/A|            0|            0|        29557|            0|
|  _rx_pllout_x1_0              |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_clk20_vcxo_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk20_vcxo_i                |     50.000ns|     20.000ns|     49.967ns|            0|            0|            0|       398349|
| TS_sys_clk_125_buf            |      8.000ns|      7.901ns|          N/A|            0|            0|       387949|            0|
| TS_ddr_clk_buf                |      3.000ns|      2.572ns|      2.998ns|            0|            0|            0|        10400|
|  TS_cmp_ddr_ctrl_cmp_ddr3_ctrl|     12.000ns|      7.731ns|          N/A|            0|            0|        10400|            0|
|  _wrapper_gen_spec_bank3_64b_3|             |             |             |             |             |             |             |
|  2b_cmp_ddr3_ctrl_memc3_infras|             |             |             |             |             |             |             |
|  tructure_inst_mcb_drp_clk_buf|             |             |             |             |             |             |             |
|  g_in_0                       |             |             |             |             |             |             |             |
|  TS_cmp_ddr_ctrl_cmp_ddr3_ctrl|      1.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  _wrapper_gen_spec_bank3_64b_3|             |             |             |             |             |             |             |
|  2b_cmp_ddr3_ctrl_memc3_infras|             |             |             |             |             |             |             |
|  tructure_inst_clk_2x_180_0   |             |             |             |             |             |             |             |
|  TS_cmp_ddr_ctrl_cmp_ddr3_ctrl|      1.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
|  _wrapper_gen_spec_bank3_64b_3|             |             |             |             |             |             |             |
|  2b_cmp_ddr3_ctrl_memc3_infras|             |             |             |             |             |             |             |
|  tructure_inst_clk_2x_0_0     |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_SYS_CLK5
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK5                    |      3.000ns|      2.572ns|      2.998ns|            0|            0|            0|            0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_|     12.000ns|      1.730ns|          N/A|            0|            0|            0|            0|
| wrapper_gen_spec_bank3_64b_32b|             |             |             |             |             |             |             |
| _cmp_ddr3_ctrl_memc3_infrastru|             |             |             |             |             |             |             |
| cture_inst_mcb_drp_clk_bufg_in|             |             |             |             |             |             |             |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_|      1.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
| wrapper_gen_spec_bank3_64b_32b|             |             |             |             |             |             |             |
| _cmp_ddr3_ctrl_memc3_infrastru|             |             |             |             |             |             |             |
| cture_inst_clk_2x_180         |             |             |             |             |             |             |             |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_|      1.500ns|      1.499ns|          N/A|            0|            0|            0|            0|
| wrapper_gen_spec_bank3_64b_32b|             |             |             |             |             |             |             |
| _cmp_ddr3_ctrl_memc3_infrastru|             |             |             |             |             |             |             |
| cture_inst_clk_2x_0           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_adc_dco_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_dco_n_i                 |      2.000ns|      0.925ns|      1.764ns|            0|            0|            0|        53971|
| TS_cmp_fmc_adc_mezzanine_0_cmp|      2.000ns|      1.636ns|      1.764ns|            0|            0|            0|        53971|
| _fmc_adc_100Ms_core_dco_clk   |             |             |             |             |             |             |             |
|  TS_cmp_fmc_adc_mezzanine_0_cm|      8.000ns|      7.054ns|          N/A|            0|            0|        53971|            0|
|  p_fmc_adc_100Ms_core_fs_clk_b|             |             |             |             |             |             |             |
|  uf                           |             |             |             |             |             |             |             |
|  TS_cmp_fmc_adc_mezzanine_0_cm|      1.000ns|          N/A|          N/A|            0|            0|            0|            0|
|  p_fmc_adc_100Ms_core_serdes_c|             |             |             |             |             |             |             |
|  lk                           |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock P2L_CLKn
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
P2L_CLKn       |    4.965|         |         |         |
P2L_CLKp       |    4.965|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock P2L_CLKp
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
P2L_CLKn       |    4.965|         |         |         |
P2L_CLKp       |    4.965|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock adc0_dco_n_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
adc0_dco_n_i   |    7.054|         |         |         |
adc0_dco_p_i   |    7.054|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock adc0_dco_p_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
adc0_dco_n_i   |    7.054|         |         |         |
adc0_dco_p_i   |    7.054|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock clk20_vcxo_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk20_vcxo_i   |    7.901|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 481877 paths, 0 nets, and 31888 connections

Design statistics:
   Minimum period:  20.000ns{1}   (Maximum frequency:  50.000MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Fri Apr 25 16:34:51 2014 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 269 MB



