Release 13.3 - xst O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> 
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.06 secs
 
--> 
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.06 secs
 
--> 
Reading design: spec_top_fmc_adc_100Ms.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "spec_top_fmc_adc_100Ms.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "spec_top_fmc_adc_100Ms"
Output Format                      : NGC
Target Device                      : xc6slx45t-3-fgg484

---- Source Options
Top Module Name                    : spec_top_fmc_adc_100Ms
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"../../ip_cores"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work
Parsing module <sockit_owm>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41.
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42.
Parsing module <spi_clgen>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41.
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42.
Parsing module <spi_shift>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 42.
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43.
Parsing module <spi_top>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work
Parsing module <lm32_top_full_debug>.
Parsing module <lm32_mc_arithmetic_full_debug>.
Parsing module <lm32_cpu_full_debug>.
Parsing module <lm32_load_store_unit_full_debug>.
Parsing module <lm32_decoder_full_debug>.
Parsing module <lm32_icache_full_debug>.
Parsing module <lm32_dcache_full_debug>.
Parsing module <lm32_debug_full_debug>.
Parsing module <lm32_instruction_unit_full_debug>.
Parsing module <lm32_jtag_full_debug>.
Parsing module <lm32_interrupt_full_debug>.
Parsing module <lm32_top_full>.
Parsing module <lm32_mc_arithmetic_full>.
Parsing module <lm32_cpu_full>.
Parsing module <lm32_load_store_unit_full>.
Parsing module <lm32_decoder_full>.
Parsing module <lm32_icache_full>.
Parsing module <lm32_dcache_full>.
Parsing module <lm32_instruction_unit_full>.
Parsing module <lm32_interrupt_full>.
Parsing module <lm32_top_medium_debug>.
Parsing module <lm32_mc_arithmetic_medium_debug>.
Parsing module <lm32_cpu_medium_debug>.
Parsing module <lm32_load_store_unit_medium_debug>.
Parsing module <lm32_decoder_medium_debug>.
Parsing module <lm32_icache_medium_debug>.
Parsing module <lm32_debug_medium_debug>.
Parsing module <lm32_instruction_unit_medium_debug>.
Parsing module <lm32_jtag_medium_debug>.
Parsing module <lm32_interrupt_medium_debug>.
Parsing module <lm32_top_medium_icache_debug>.
Parsing module <lm32_mc_arithmetic_medium_icache_debug>.
Parsing module <lm32_cpu_medium_icache_debug>.
Parsing module <lm32_load_store_unit_medium_icache_debug>.
Parsing module <lm32_decoder_medium_icache_debug>.
Parsing module <lm32_icache_medium_icache_debug>.
Parsing module <lm32_debug_medium_icache_debug>.
Parsing module <lm32_instruction_unit_medium_icache_debug>.
Parsing module <lm32_jtag_medium_icache_debug>.
Parsing module <lm32_interrupt_medium_icache_debug>.
Parsing module <lm32_top_medium_icache>.
Parsing module <lm32_mc_arithmetic_medium_icache>.
Parsing module <lm32_cpu_medium_icache>.
Parsing module <lm32_load_store_unit_medium_icache>.
Parsing module <lm32_decoder_medium_icache>.
Parsing module <lm32_icache_medium_icache>.
Parsing module <lm32_instruction_unit_medium_icache>.
Parsing module <lm32_interrupt_medium_icache>.
Parsing module <lm32_top_medium>.
Parsing module <lm32_mc_arithmetic_medium>.
Parsing module <lm32_cpu_medium>.
Parsing module <lm32_load_store_unit_medium>.
Parsing module <lm32_decoder_medium>.
Parsing module <lm32_instruction_unit_medium>.
Parsing module <lm32_interrupt_medium>.
Parsing module <lm32_top_minimal>.
Parsing module <lm32_mc_arithmetic_minimal>.
Parsing module <lm32_cpu_minimal>.
Parsing module <lm32_load_store_unit_minimal>.
Parsing module <lm32_decoder_minimal>.
Parsing module <lm32_instruction_unit_minimal>.
Parsing module <lm32_interrupt_minimal>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_mc_arithmetic>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work
Parsing module <jtag_cores>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_adder>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28.
Parsing module <lm32_addsub>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_logic_op>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work
Parsing verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_shifter>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" into library work
Parsing module <lm32_multiplier>.
Analyzing Verilog file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" into library work
Parsing module <jtag_tap>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/adc_serdes.vhd" into library work
Parsing entity <adc_serdes>.
Parsing architecture <xilinx> of entity <adc_serdes>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/monostable/monostable_rtl.vhd" into library work
Parsing entity <monostable>.
Parsing architecture <rtl> of entity <monostable>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/utils/utils_pkg.vhd" into library work
Parsing package <utils_pkg>.
Parsing package body <utils_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd" into library work
Parsing entity <ext_pulse_sync>.
Parsing architecture <rtl> of entity <ext_pulse_sync>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work
Parsing package <genram_pkg>.
Parsing package body <genram_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/carrier_csr.vhd" into library work
Parsing entity <carrier_csr>.
Parsing architecture <syn> of entity <carrier_csr>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work
Parsing package <wbgen2_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd" into library work
Parsing package <timetag_core_pkg>.
Parsing package body <timetag_core_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd" into library work
Parsing package <fmc_adc_100Ms_core_pkg>.
Parsing package body <fmc_adc_100Ms_core_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd" into library work
Parsing package <fmc_adc_mezzanine_pkg>.
Parsing package body <fmc_adc_mezzanine_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work
Parsing package <wishbone_pkg>.
Parsing package body <wishbone_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/sdb_meta_pkg.vhd" into library work
Parsing package <sdb_meta_pkg>.
Parsing package body <sdb_meta_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd" into library work
Parsing entity <fmc_adc_100Ms_csr>.
Parsing architecture <syn> of entity <fmc_adc_100ms_csr>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd" into library work
Parsing entity <fmc_adc_eic>.
Parsing architecture <syn> of entity <fmc_adc_eic>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/offset_gain_s.vhd" into library work
Parsing entity <offset_gain_s>.
Parsing architecture <rtl> of entity <offset_gain_s>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/var_sat_s.vhd" into library work
Parsing entity <var_sat_s>.
Parsing architecture <rtl> of entity <var_sat_s>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd" into library work
Parsing entity <timetag_core_regs>.
Parsing architecture <syn> of entity <timetag_core_regs>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd" into library work
Parsing entity <timetag_core>.
Parsing architecture <rtl> of entity <timetag_core>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" into library work
Parsing package <ddr3_ctrl_pkg>.
Parsing package body <ddr3_ctrl_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work
Parsing package <gencores_pkg>.
Parsing package body <gencores_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work
Parsing entity <gc_crc_gen>.
Parsing architecture <rtl> of entity <gc_crc_gen>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work
Parsing entity <gc_moving_average>.
Parsing architecture <rtl> of entity <gc_moving_average>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work
Parsing entity <gc_extend_pulse>.
Parsing architecture <rtl> of entity <gc_extend_pulse>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work
Parsing entity <gc_delay_gen>.
Parsing architecture <behavioral> of entity <gc_delay_gen>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work
Parsing entity <gc_dual_pi_controller>.
Parsing architecture <behavioral> of entity <gc_dual_pi_controller>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work
Parsing entity <gc_reset>.
Parsing architecture <rtl> of entity <gc_reset>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work
Parsing entity <gc_serial_dac>.
Parsing architecture <syn> of entity <gc_serial_dac>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work
Parsing entity <gc_sync_ffs>.
Parsing architecture <behavioral> of entity <gc_sync_ffs>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work
Parsing entity <gc_arbitrated_mux>.
Parsing architecture <rtl> of entity <gc_arbitrated_mux>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work
Parsing entity <gc_pulse_synchronizer>.
Parsing architecture <rtl> of entity <gc_pulse_synchronizer>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" into library work
Parsing entity <gc_pulse_synchronizer2>.
Parsing architecture <rtl> of entity <gc_pulse_synchronizer2>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work
Parsing entity <gc_frequency_meter>.
Parsing architecture <behavioral> of entity <gc_frequency_meter>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" into library work
Parsing entity <gc_rr_arbiter>.
Parsing architecture <rtl> of entity <gc_rr_arbiter>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" into library work
Parsing entity <gc_prio_encoder>.
Parsing architecture <rtl> of entity <gc_prio_encoder>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_word_packer.vhd" into library work
Parsing entity <gc_word_packer>.
Parsing architecture <rtl> of entity <gc_word_packer>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" into library work
Parsing entity <gc_i2c_slave>.
Parsing architecture <behav> of entity <gc_i2c_slave>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" into library work
Parsing entity <gc_glitch_filt>.
Parsing architecture <behav> of entity <gc_glitch_filt>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" into library work
Parsing entity <gc_dyn_glitch_filt>.
Parsing architecture <behav> of entity <gc_dyn_glitch_filt>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_big_adder.vhd" into library work
Parsing entity <gc_big_adder>.
Parsing architecture <rtl> of entity <gc_big_adder>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" into library work
Parsing entity <gc_fsm_watchdog>.
Parsing architecture <behav> of entity <gc_fsm_watchdog>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" into library work
Parsing entity <gc_bicolor_led_ctrl>.
Parsing architecture <rtl> of entity <gc_bicolor_led_ctrl>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" into library work
Parsing entity <fmc_adc_100Ms_core>.
Parsing architecture <rtl> of entity <fmc_adc_100ms_core>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work
Parsing package <memory_loader_pkg>.
Parsing package body <memory_loader_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work
Parsing entity <generic_shiftreg_fifo>.
Parsing architecture <rtl> of entity <generic_shiftreg_fifo>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" into library work
Parsing entity <inferred_sync_fifo>.
Parsing architecture <syn> of entity <inferred_sync_fifo>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" into library work
Parsing entity <inferred_async_fifo>.
Parsing architecture <syn> of entity <inferred_async_fifo>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" into library work
Parsing entity <fmc_adc_mezzanine>.
Parsing architecture <rtl> of entity <fmc_adc_mezzanine>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work
Parsing entity <generic_dpram>.
Parsing architecture <syn> of entity <generic_dpram>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work
Parsing entity <generic_dpram_sameclock>.
Parsing architecture <syn> of entity <generic_dpram_sameclock>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work
Parsing entity <generic_dpram_dualclock>.
Parsing architecture <syn> of entity <generic_dpram_dualclock>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" into library work
Parsing entity <generic_simple_dpram>.
Parsing architecture <syn> of entity <generic_simple_dpram>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work
Parsing entity <generic_spram>.
Parsing architecture <syn> of entity <generic_spram>.
WARNING:HDLCompiler:443 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value.
WARNING:HDLCompiler:443 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" into library work
Parsing entity <gc_shiftreg>.
Parsing architecture <wrapper> of entity <gc_shiftreg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" into library work
Parsing entity <generic_async_fifo>.
Parsing architecture <syn> of entity <generic_async_fifo>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" into library work
Parsing entity <generic_sync_fifo>.
Parsing architecture <syn> of entity <generic_sync_fifo>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work
Parsing entity <wb_async_bridge>.
Parsing architecture <behavioral> of entity <wb_async_bridge>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work
Parsing entity <xwb_async_bridge>.
Parsing architecture <wrapper> of entity <xwb_async_bridge>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work
Parsing entity <wb_onewire_master>.
Parsing architecture <rtl> of entity <wb_onewire_master>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work
Parsing entity <xwb_onewire_master>.
Parsing architecture <rtl> of entity <xwb_onewire_master>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work
Parsing entity <i2c_master_bit_ctrl>.
Parsing architecture <structural> of entity <i2c_master_bit_ctrl>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work
Parsing entity <i2c_master_byte_ctrl>.
Parsing architecture <structural> of entity <i2c_master_byte_ctrl>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work
Parsing entity <i2c_master_top>.
Parsing architecture <structural> of entity <i2c_master_top>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work
Parsing entity <wb_i2c_master>.
Parsing architecture <rtl> of entity <wb_i2c_master>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work
Parsing entity <xwb_i2c_master>.
Parsing architecture <rtl> of entity <xwb_i2c_master>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work
Parsing entity <xwb_bus_fanout>.
Parsing architecture <rtl> of entity <xwb_bus_fanout>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work
Parsing entity <xwb_dpram>.
Parsing architecture <struct> of entity <xwb_dpram>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work
Parsing entity <wb_gpio_port>.
Parsing architecture <behavioral> of entity <wb_gpio_port>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work
Parsing entity <xwb_gpio_port>.
Parsing architecture <rtl> of entity <xwb_gpio_port>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work
Parsing entity <wb_tics>.
Parsing architecture <behaviour> of entity <wb_tics>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work
Parsing entity <xwb_tics>.
Parsing architecture <rtl> of entity <xwb_tics>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work
Parsing entity <uart_async_rx>.
Parsing architecture <behavioral> of entity <uart_async_rx>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work
Parsing entity <uart_async_tx>.
Parsing architecture <behavioral> of entity <uart_async_tx>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work
Parsing entity <uart_baud_gen>.
Parsing architecture <behavioral> of entity <uart_baud_gen>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work
Parsing package <uart_wbgen2_pkg>.
Parsing package body <uart_wbgen2_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work
Parsing entity <simple_uart_wb>.
Parsing architecture <syn> of entity <simple_uart_wb>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work
Parsing entity <wb_simple_uart>.
Parsing architecture <syn> of entity <wb_simple_uart>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work
Parsing entity <xwb_simple_uart>.
Parsing architecture <rtl> of entity <xwb_simple_uart>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work
Parsing entity <vic_prio_enc>.
Parsing architecture <syn> of entity <vic_prio_enc>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work
Parsing entity <wb_slave_vic>.
Parsing architecture <syn> of entity <wb_slave_vic>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work
Parsing entity <wb_vic>.
Parsing architecture <syn> of entity <wb_vic>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work
Parsing entity <xwb_vic>.
Parsing architecture <wrapper> of entity <xwb_vic>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work
Parsing entity <wb_spi>.
Parsing architecture <rtl> of entity <wb_spi>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work
Parsing entity <xwb_spi>.
Parsing architecture <rtl> of entity <xwb_spi>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work
Parsing entity <sdb_rom>.
Parsing architecture <rtl> of entity <sdb_rom>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work
Parsing entity <xwb_crossbar>.
Parsing architecture <rtl> of entity <xwb_crossbar>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work
Parsing entity <xwb_sdb_crossbar>.
Parsing architecture <rtl> of entity <xwb_sdb_crossbar>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" into library work
Parsing entity <xwb_register_link>.
Parsing architecture <rtl> of entity <xwb_register_link>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" into library work
Parsing package <wb_irq_pkg>.
Parsing package body <wb_irq_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" into library work
Parsing entity <irqm_core>.
Parsing architecture <behavioral> of entity <irqm_core>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" into library work
Parsing entity <wb_irq_lm32>.
Parsing architecture <rtl> of entity <wb_irq_lm32>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" into library work
Parsing entity <wb_irq_slave>.
Parsing architecture <behavioral> of entity <wb_irq_slave>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" into library work
Parsing entity <wb_irq_master>.
Parsing architecture <behavioral> of entity <wb_irq_master>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" into library work
Parsing entity <wb_irq_timer>.
Parsing architecture <behavioral> of entity <wb_irq_timer>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work
Parsing entity <xwb_lm32>.
Parsing architecture <rtl> of entity <xwb_lm32>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" into library work
Parsing entity <lm32_dp_ram>.
Parsing architecture <syn> of entity <lm32_dp_ram>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" into library work
Parsing entity <lm32_ram>.
Parsing architecture <syn> of entity <lm32_ram>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work
Parsing entity <wb_slave_adapter>.
Parsing architecture <rtl> of entity <wb_slave_adapter>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work
Parsing entity <xwb_clock_crossing>.
Parsing architecture <rtl> of entity <xwb_clock_crossing>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work
Parsing entity <xwb_dma>.
Parsing architecture <rtl> of entity <xwb_dma>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" into library work
Parsing entity <xwb_streamer>.
Parsing architecture <rtl> of entity <xwb_streamer>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" into library work
Parsing entity <wb_serial_lcd>.
Parsing architecture <rtl> of entity <wb_serial_lcd>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" into library work
Parsing entity <wb_spi_flash>.
Parsing architecture <rtl> of entity <wb_spi_flash>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" into library work
Parsing package <spwm_wbgen2_pkg>.
Parsing package body <spwm_wbgen2_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" into library work
Parsing entity <simple_pwm_wb>.
Parsing architecture <syn> of entity <simple_pwm_wb>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" into library work
Parsing entity <wb_simple_pwm>.
Parsing architecture <behavioral> of entity <wb_simple_pwm>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" into library work
Parsing entity <xwb_simple_pwm>.
Parsing architecture <wrapper> of entity <xwb_simple_pwm>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" into library work
Parsing entity <wb_i2c_bridge>.
Parsing architecture <behav> of entity <wb_i2c_bridge>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work
Parsing entity <wbgen2_dpssram>.
Parsing architecture <syn> of entity <wbgen2_dpssram>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work
Parsing entity <wbgen2_eic>.
Parsing architecture <syn> of entity <wbgen2_eic>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work
Parsing entity <wbgen2_fifo_async>.
Parsing architecture <rtl> of entity <wbgen2_fifo_async>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work
Parsing entity <wbgen2_fifo_sync>.
Parsing architecture <rtl> of entity <wbgen2_fifo_sync>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd" into library work
Parsing entity <dma_eic>.
Parsing architecture <syn> of entity <dma_eic>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work
Parsing package <xldr_wbgen2_pkg>.
Parsing package body <xldr_wbgen2_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work
Parsing entity <xwb_xilinx_fpga_loader>.
Parsing architecture <rtl> of entity <xwb_xilinx_fpga_loader>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work
Parsing entity <wb_xilinx_fpga_loader>.
Parsing architecture <behavioral> of entity <wb_xilinx_fpga_loader>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work
Parsing entity <xloader_wb>.
Parsing architecture <syn> of entity <xloader_wb>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" into library work
Parsing entity <spi_master>.
Parsing architecture <behavioral> of entity <spi_master>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" into library work
Parsing entity <multiboot_fsm>.
Parsing architecture <behav> of entity <multiboot_fsm>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" into library work
Parsing entity <multiboot_regs>.
Parsing architecture <syn> of entity <multiboot_regs>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" into library work
Parsing entity <wb_xil_multiboot>.
Parsing architecture <struct> of entity <wb_xil_multiboot>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" into library work
Parsing entity <ddr3_ctrl>.
Parsing architecture <rtl> of entity <ddr3_ctrl>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" into library work
Parsing entity <ddr3_ctrl_wb>.
Parsing architecture <rtl> of entity <ddr3_ctrl_wb>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" into library work
Parsing package <ddr3_ctrl_wrapper_pkg>.
Parsing package body <ddr3_ctrl_wrapper_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" into library work
Parsing entity <ddr3_ctrl_wrapper>.
Parsing architecture <rtl> of entity <ddr3_ctrl_wrapper>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" into library work
Parsing package <gn4124_core_pkg>.
Parsing package body <gn4124_core_pkg>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" into library work
Parsing entity <ddr3_ctrl_spec_bank3_64b_32b>.
Parsing architecture <arc> of entity <ddr3_ctrl_spec_bank3_64b_32b>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" into library work
Parsing entity <memc3_infrastructure>.
Parsing architecture <syn> of entity <memc3_infrastructure>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" into library work
Parsing entity <memc3_wrapper>.
Parsing architecture <acch> of entity <memc3_wrapper>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" into library work
Parsing entity <iodrp_controller>.
Parsing architecture <trans> of entity <iodrp_controller>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" into library work
Parsing entity <iodrp_mcb_controller>.
Parsing architecture <trans> of entity <iodrp_mcb_controller>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" into library work
Parsing entity <mcb_raw_wrapper>.
Parsing architecture <aarch> of entity <mcb_raw_wrapper>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" into library work
Parsing entity <mcb_soft_calibration_top>.
Parsing architecture <trans> of entity <mcb_soft_calibration_top>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" into library work
Parsing entity <mcb_soft_calibration>.
Parsing architecture <trans> of entity <mcb_soft_calibration>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" into library work
Parsing entity <dma_controller>.
Parsing architecture <behaviour> of entity <dma_controller>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" into library work
Parsing entity <dma_controller_wb_slave>.
Parsing architecture <syn> of entity <dma_controller_wb_slave>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" into library work
Parsing entity <l2p_arbiter>.
Parsing architecture <rtl> of entity <l2p_arbiter>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" into library work
Parsing entity <l2p_dma_master>.
Parsing architecture <behaviour> of entity <l2p_dma_master>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" into library work
Parsing entity <p2l_decode32>.
Parsing architecture <rtl> of entity <p2l_decode32>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" into library work
Parsing entity <p2l_dma_master>.
Parsing architecture <behaviour> of entity <p2l_dma_master>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" into library work
Parsing entity <wbmaster32>.
Parsing architecture <behaviour> of entity <wbmaster32>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" into library work
Parsing entity <gn4124_core>.
Parsing architecture <rtl> of entity <gn4124_core>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" into library work
Parsing entity <spec_top_fmc_adc_100Ms>.
Parsing architecture <rtl> of entity <spec_top_fmc_adc_100ms>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" into library work
Parsing entity <l2p_ser>.
Parsing architecture <rtl> of entity <l2p_ser>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" into library work
Parsing entity <p2l_des>.
Parsing architecture <rtl> of entity <p2l_des>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" into library work
Parsing entity <serdes_1_to_n_clk_pll_s2_diff>.
Parsing architecture <arch_serdes_1_to_n_clk_pll_s2_diff> of entity <serdes_1_to_n_clk_pll_s2_diff>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" into library work
Parsing entity <serdes_1_to_n_data_s2_se>.
Parsing architecture <arch_serdes_1_to_n_data_s2_se> of entity <serdes_1_to_n_data_s2_se>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" into library work
Parsing entity <serdes_n_to_1_s2_diff>.
Parsing architecture <arch_serdes_n_to_1_s2_diff> of entity <serdes_n_to_1_s2_diff>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" into library work
Parsing entity <serdes_n_to_1_s2_se>.
Parsing architecture <arch_serdes_n_to_1_s2_se> of entity <serdes_n_to_1_s2_se>.
Parsing VHDL file "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" into library work
Parsing entity <pulse_synchronizer>.
Parsing architecture <rtl> of entity <pulse_synchronizer>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <spec_top_fmc_adc_100Ms> (architecture <rtl>) with generics from library <work>.

Elaborating entity <gn4124_core> (architecture <rtl>) with generics from library <work>.

Elaborating entity <serdes_1_to_n_clk_pll_s2_diff> (architecture <arch_serdes_1_to_n_clk_pll_s2_diff>) with generics from library <work>.

Elaborating entity <p2l_des> (architecture <rtl>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" Line 155: Assignment to p2l_data_bitslip_p ignored, since the identifier is never used

Elaborating entity <serdes_1_to_n_data_s2_se> (architecture <arch_serdes_1_to_n_data_s2_se>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" Line 97: Net <busys[15]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" Line 111: Net <valid_data[15]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" Line 119: Net <incdec_data[15]> does not have a driver.

Elaborating entity <serdes_1_to_n_data_s2_se> (architecture <arch_serdes_1_to_n_data_s2_se>) with generics from library <work>.

Elaborating entity <p2l_decode32> (architecture <rtl>) from library <work>.

Elaborating entity <wbmaster32> (architecture <behaviour>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" Line 298. Case statement is complete. others clause is never selected

Elaborating entity <generic_async_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <inferred_async_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <generic_async_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <inferred_async_fifo> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" Line 470. Case statement is complete. others clause is never selected

Elaborating entity <dma_controller> (architecture <behaviour>) from library <work>.

Elaborating entity <dma_controller_wb_slave> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" Line 167: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" Line 168: Assignment to bus_clock_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" Line 169: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" Line 170: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" Line 171: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" Line 172: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" Line 457. Case statement is complete. others clause is never selected

Elaborating entity <pulse_synchronizer> (architecture <rtl>) from library <work>.

Elaborating entity <l2p_dma_master> (architecture <behaviour>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" Line 487. Case statement is complete. others clause is never selected

Elaborating entity <generic_async_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <inferred_async_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <p2l_dma_master> (architecture <behaviour>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" Line 380. Case statement is complete. others clause is never selected

Elaborating entity <generic_async_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <inferred_async_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <l2p_arbiter> (architecture <rtl>) from library <work>.

Elaborating entity <l2p_ser> (architecture <rtl>) from library <work>.

Elaborating entity <serdes_n_to_1_s2_diff> (architecture <arch_serdes_n_to_1_s2_diff>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" Line 93: Net <mdatainb[3]> does not have a driver.

Elaborating entity <serdes_n_to_1_s2_se> (architecture <arch_serdes_n_to_1_s2_se>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" Line 92: Net <mdatainb[63]> does not have a driver.

Elaborating entity <serdes_n_to_1_s2_se> (architecture <arch_serdes_n_to_1_s2_se>) with generics from library <work>.

Elaborating entity <xwb_sdb_crossbar> (architecture <rtl>) with generics from library <work>.

Elaborating entity <sdb_rom> (architecture <rtl>) with generics from library <work>.

Elaborating entity <xwb_crossbar> (architecture <rtl>) with generics from library <work>.
Note: "Mapping slave #0[0x1000/0x3fc0]"
Note: "Mapping slave #1[0x1100/0x3f00]"
Note: "Mapping slave #2[0x1200/0x3fe0]"
Note: "Mapping slave #3[0x1300/0x3f00]"
Note: "Mapping slave #4[0x1400/0x3ff0]"
Note: "Mapping slave #5[0x2000/0x2000]"
Note: "Mapping slave #6[0x0/0x3c00]"

Elaborating entity <xwb_onewire_master> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_onewire_master> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
Going to verilog side to elaborate module sockit_owm

Elaborating module <sockit_owm(OVD_E=1,CDR_E=1,BDW=32,OWN=1,BAW=1,BTP_N="5.0",BTP_O="1.0")>.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 156: Net <owr_sel[0]> does not have a driver.
Back to vhdl to continue elaboration
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" Line 97: Net <adp_in_err> does not have a driver.

Elaborating entity <carrier_csr> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/carrier_csr.vhd" Line 76: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/carrier_csr.vhd" Line 77: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/carrier_csr.vhd" Line 78: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/carrier_csr.vhd" Line 79: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/carrier_csr.vhd" Line 80: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/carrier_csr.vhd" Line 230. Case statement is complete. others clause is never selected

Elaborating entity <xwb_vic> (architecture <wrapper>) with generics from library <work>.

Elaborating entity <wb_vic> (architecture <syn>) with generics from library <work>.

Elaborating entity <vic_prio_enc> (architecture <syn>) from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_slave_vic> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" Line 92: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" Line 95: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" Line 96: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" Line 331. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" Line 343. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" Line 367: Assignment to vic_ivt_ram_rd_int ignored, since the identifier is never used

Elaborating entity <dma_eic> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd" Line 63: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd" Line 64: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd" Line 65: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd" Line 66: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd" Line 67: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd" Line 243. Case statement is complete. others clause is never selected

Elaborating entity <wbgen2_eic> (architecture <syn>) with generics from library <work>.

Elaborating entity <fmc_adc_mezzanine> (architecture <rtl>) with generics from library <work>.

Elaborating entity <xwb_register_link> (architecture <rtl>) from library <work>.

Elaborating entity <xwb_sdb_crossbar> (architecture <rtl>) with generics from library <work>.

Elaborating entity <sdb_rom> (architecture <rtl>) with generics from library <work>.

Elaborating entity <xwb_crossbar> (architecture <rtl>) with generics from library <work>.
Note: "Mapping slave #0[0x1000/0x1f00]"
Note: "Mapping slave #1[0x1100/0x1fe0]"
Note: "Mapping slave #2[0x1200/0x1f00]"
Note: "Mapping slave #3[0x1300/0x1f00]"
Note: "Mapping slave #4[0x1400/0x1f00]"
Note: "Mapping slave #5[0x1500/0x1ff0]"
Note: "Mapping slave #6[0x1600/0x1f80]"
Note: "Mapping slave #7[0x0/0x1e00]"

Elaborating entity <xwb_i2c_master> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_i2c_master> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <i2c_master_top> (architecture <structural>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" Line 204. Case statement is complete. others clause is never selected

Elaborating entity <i2c_master_byte_ctrl> (architecture <structural>) from library <work>.

Elaborating entity <i2c_master_bit_ctrl> (architecture <structural>) from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" Line 561. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" Line 354. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" Line 90: Net <wb_out_err> does not have a driver.

Elaborating entity <xwb_spi> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_spi> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
Going to verilog side to elaborate module spi_top

Elaborating module <spi_top(Tp=1)>.

Elaborating module <spi_clgen>.

Elaborating module <spi_shift>.
Back to vhdl to continue elaboration
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" Line 61: Net <wb_out_rty> does not have a driver.

Elaborating entity <fmc_adc_100Ms_core> (architecture <rtl>) with generics from library <work>.

Elaborating entity <monostable> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" Line 495: Assignment to fs_rst ignored, since the identifier is never used

Elaborating entity <gc_frequency_meter> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <gc_pulse_synchronizer> (architecture <rtl>) from library <work>.

Elaborating entity <adc_serdes> (architecture <xilinx>) with generics from library <work>.

Elaborating entity <fmc_adc_100Ms_csr> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd" Line 262: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd" Line 263: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd" Line 264: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd" Line 265: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd" Line 266: Assignment to allzeros ignored, since the identifier is never used

Elaborating entity <offset_gain_s> (architecture <rtl>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/offset_gain_s.vhd" Line 110: Assignment to data_in_d ignored, since the identifier is never used

Elaborating entity <MULT_MACRO> (architecture <mult>) with generics from library <unimacro>.
WARNING:HDLCompiler:321 - "/build/xfndry10/O.76xd/rtf/devlib/vhdl/src/unimacro/MULT_MACRO.vhd" Line 63: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/build/xfndry10/O.76xd/rtf/devlib/vhdl/src/unimacro/MULT_MACRO.vhd" Line 82: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/build/xfndry10/O.76xd/rtf/devlib/vhdl/src/unimacro/MULT_MACRO.vhd" Line 101: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/build/xfndry10/O.76xd/rtf/devlib/vhdl/src/unimacro/MULT_MACRO.vhd" Line 156: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/build/xfndry10/O.76xd/rtf/devlib/vhdl/src/unimacro/MULT_MACRO.vhd" Line 309: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/build/xfndry10/O.76xd/rtf/devlib/vhdl/src/unimacro/MULT_MACRO.vhd" Line 319: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/build/xfndry10/O.76xd/rtf/devlib/vhdl/src/unimacro/MULT_MACRO.vhd" Line 439: Comparison between arrays of unequal length always returns FALSE.

Elaborating entity <ext_pulse_sync> (architecture <rtl>) with generics from library <work>.

Elaborating entity <gc_dyn_glitch_filt> (architecture <behav>) with generics from library <work>.

Elaborating entity <generic_async_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <inferred_async_fifo> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" Line 1252. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" Line 1319. Case statement is complete. others clause is never selected

Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.

Elaborating entity <generic_dpram_dualclock> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" Line 190: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" Line 219: Comparison between arrays of unequal length always returns FALSE.

Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.

Elaborating entity <generic_dpram_sameclock> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 175: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 198: Comparison between arrays of unequal length always returns FALSE.

Elaborating entity <generic_sync_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <inferred_sync_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.

Elaborating entity <generic_dpram_sameclock> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" Line 106: Assignment to q_reg ignored, since the identifier is never used

Elaborating entity <fmc_adc_eic> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd" Line 63: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd" Line 64: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd" Line 65: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd" Line 66: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd" Line 67: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd" Line 243. Case statement is complete. others clause is never selected

Elaborating entity <timetag_core> (architecture <rtl>) from library <work>.

Elaborating entity <timetag_core_regs> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd" Line 89: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd" Line 90: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd" Line 91: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd" Line 92: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd" Line 93: Assignment to allzeros ignored, since the identifier is never used

Elaborating entity <ddr3_ctrl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ddr3_ctrl_wb> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" Line 214: Assignment to wb_we_f_edge ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" Line 279: Assignment to ddr_cmd_en_r_edge ignored, since the identifier is never used

Elaborating entity <ddr3_ctrl_wb> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ddr3_ctrl_wrapper> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ddr3_ctrl_spec_bank3_64b_32b> (architecture <arc>) with generics from library <work>.

Elaborating entity <memc3_infrastructure> (architecture <syn>) with generics from library <work>.

Elaborating entity <memc3_wrapper> (architecture <acch>) with generics from library <work>.

Elaborating entity <mcb_raw_wrapper> (architecture <aarch>) with generics from library <work>.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 582: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2445: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2446: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2447: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2448: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2449: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2450: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2451: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2452: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2453: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2454: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2455: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2456: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2457: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2458: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2459: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2460: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2861: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2862: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2863: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2864: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2865: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2866: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2867: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2868: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2903: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2904: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2905: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2906: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2907: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2908: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2909: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2910: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2945: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2946: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2947: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2948: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2949: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2950: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2951: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2952: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2988: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2989: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2990: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2991: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2992: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2993: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2994: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 2995: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3029: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3030: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3031: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3032: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3033: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3034: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3035: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3036: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3072: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3073: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3074: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3075: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3076: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3077: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3078: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3079: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3111: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3112: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3113: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3114: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3115: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3116: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3117: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3118: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3156: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3157: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3158: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3159: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3160: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3161: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3162: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3163: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3207: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3757: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 3964: Comparison between arrays of unequal length always returns FALSE.

Elaborating entity <mcb_soft_calibration_top> (architecture <trans>) with generics from library <work>.

Elaborating entity <mcb_soft_calibration> (architecture <trans>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" Line 534: Assignment to half_mv_du ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" Line 536: Assignment to half_mv_dd ignored, since the identifier is never used

Elaborating entity <iodrp_controller> (architecture <trans>) from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" Line 352. Case statement is complete. others clause is never selected

Elaborating entity <iodrp_mcb_controller> (architecture <trans>) from library <work>.
INFO:HDLCompiler:679 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" Line 496. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" Line 598: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" Line 870: Assignment to state_start_dyncal_r1 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" Line 927: Assignment to mcb_uodatavalid_u ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" Line 971: Assignment to iodrpctrlr_use_bkst ignored, since the identifier is never used
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" Line 395: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" Line 222: Net <ZIO_IODRP_SDO> does not have a driver.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" Line 236: Net <ZIO_IN> does not have a driver.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 6992: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 7024: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 7050: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 7075: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 7086: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 7091: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 860: Net <mig_p2_wr_data[31]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 862: Net <mig_p4_wr_data[31]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 867: Net <mig_p2_wr_mask[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" Line 869: Net <mig_p4_wr_mask[3]> does not have a driver.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" Line 811: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" Line 906: Comparison between arrays of unequal length always returns FALSE.

Elaborating entity <gc_extend_pulse> (architecture <rtl>) with generics from library <work>.
WARNING:Xst:2972 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 1074. All outputs of instance <gen_irq_led[1].cmp_irq_led> of block <gc_extend_pulse> are unconnected in block <spec_top_fmc_adc_100Ms>. Underlying logic will be removed.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <spec_top_fmc_adc_100Ms>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd".
        g_SIMULATION = "FALSE"
        g_CALIB_SOFT_IP = "TRUE"
WARNING:Xst:647 - Input <aux_buttons_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 678: Output port <desc_o> of the instance <cmp_carrier_onewire> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 678: Output port <owr_pwren_o> of the instance <cmp_carrier_onewire> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 709: Output port <wb_stall_o> of the instance <cmp_carrier_csr> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 709: Output port <carrier_csr_ctrl_dac_clr_n_o> of the instance <cmp_carrier_csr> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <wb0_data_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_rd_count_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_wr_count_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_rd_count_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_wr_count_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_cmd_empty_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_cmd_full_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_rd_full_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_rd_empty_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_rd_overflow_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_rd_error_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_wr_full_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_wr_underrun_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p0_wr_error_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_cmd_empty_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_cmd_full_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_rd_full_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_rd_empty_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_rd_overflow_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_rd_error_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_wr_full_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_wr_empty_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_wr_underrun_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 897: Output port <p1_wr_error_o> of the instance <cmp_ddr_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd" line 1074: Output port <extended_o> of the instance <gen_irq_led[1].cmp_irq_led> is unconnected or connected to loadless signal.
    Found 8-bit register for signal <powerup_reset_cnt>.
    Found 1-bit register for signal <sw_rst_fmc0_n>.
    Found 10-bit register for signal <led_pwm_update_cnt>.
    Found 1-bit register for signal <led_pwm_update>.
    Found 17-bit register for signal <led_pwm_val>.
    Found 1-bit register for signal <led_pwm_val_down>.
    Found 17-bit register for signal <led_pwm_cnt>.
    Found 1-bit register for signal <led_pwm>.
    Found 1-bit register for signal <powerup_rst_n>.
    Found 8-bit adder for signal <powerup_reset_cnt[7]_GND_13_o_add_1_OUT> created at line 1241.
    Found 10-bit adder for signal <led_pwm_update_cnt[9]_GND_13_o_add_9_OUT> created at line 1241.
    Found 17-bit adder for signal <led_pwm_val[16]_GND_13_o_add_16_OUT> created at line 1241.
    Found 17-bit adder for signal <led_pwm_cnt[16]_GND_13_o_add_21_OUT> created at line 1241.
    Found 17-bit subtractor for signal <GND_13_o_GND_13_o_sub_15_OUT<16:0>> created at line 1308.
    Found 1-bit tristate buffer for signal <carrier_one_wire_b> created at line 699
    Found 17-bit comparator equal for signal <led_pwm_cnt[16]_led_pwm_val[16]_equal_26_o> created at line 1056
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  57 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Tristate(s).
Unit <spec_top_fmc_adc_100Ms> synthesized.

Synthesizing Unit <gn4124_core>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd".
        g_ACK_TIMEOUT = 100
WARNING:Xst:647 - Input <p_wr_req_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <vc_rdy_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_reg_adr_i<31:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" line 365: Output port <datain> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" line 365: Output port <rx_pll_lckd> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" line 365: Output port <rx_pllout_xs> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" line 365: Output port <bitslip> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" line 448: Output port <p2l_hdr_stat_o> of the instance <cmp_p2l_decode32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" line 448: Output port <p2l_hdr_last_o> of the instance <cmp_p2l_decode32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" line 613: Output port <done_o> of the instance <l_dma_irq_sync[0].cmp_dma_irq_sync> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" line 613: Output port <done_o> of the instance <l_dma_irq_sync[1].cmp_dma_irq_sync> is unconnected or connected to loadless signal.
    Found 2-bit register for signal <l_wr_rdy_t>.
    Found 2-bit register for signal <l_wr_rdy_t2>.
    Found 2-bit register for signal <l_wr_rdy>.
    Found 2-bit register for signal <p_rd_d_rdy_t>.
    Found 2-bit register for signal <p_rd_d_rdy_t2>.
    Found 2-bit register for signal <p_rd_d_rdy>.
    Found 1-bit register for signal <rst_reg>.
    Found 1-bit register for signal <l2p_rdy_t>.
    Found 1-bit register for signal <l2p_rdy_t2>.
    Found 1-bit register for signal <l2p_rdy>.
    Found 1-bit register for signal <l2p_edb_o>.
    Found 1-bit register for signal <l2p_edb_t>.
    Found 1-bit register for signal <l2p_edb_t2>.
    Found 1-bit register for signal <tx_error_t2>.
    Found 1-bit register for signal <tx_error_t>.
    Found 1-bit register for signal <tx_error>.
    Summary:
	inferred  22 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <gn4124_core> synthesized.

Synthesizing Unit <serdes_1_to_n_clk_pll_s2_diff>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd".
        PLLD = 1
        PLLX = 2
        CLKIN_PERIOD = 5.0
        S = 2
        BS = false
        DIFF_TERM = false
WARNING:Xst:647 - Input <pattern1<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pattern2<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <enable>.
    Found 1-bit register for signal <cal_clk>.
    Found 1-bit register for signal <rst_clk>.
    Found 1-bit register for signal <bslip>.
    Found 12-bit register for signal <counter>.
    Found 3-bit register for signal <count>.
    Found 4-bit register for signal <state>.
    Found 1-bit register for signal <busyd>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 24                                             |
    | Inputs             | 4                                              |
    | Outputs            | 9                                              |
    | Clock              | rx_bufg_pll_x1_int (rising_edge)               |
    | Reset              | not_rx_bufpll_lckd (positive)                  |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 12-bit adder for signal <counter[11]_GND_18_o_add_1_OUT> created at line 176.
    Found 3-bit adder for signal <count[2]_GND_18_o_add_14_OUT> created at line 205.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  19 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <serdes_1_to_n_clk_pll_s2_diff> synthesized.

Synthesizing Unit <p2l_des>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd".
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" line 160: Output port <debug> of the instance <cmp_data_in> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" line 180: Output port <debug> of the instance <cmp_dframe_in> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" line 203: Output port <debug> of the instance <cmp_valid_in> is unconnected or connected to loadless signal.
    Found 32-bit register for signal <p2l_data_o>.
    Found 32-bit register for signal <p2l_data_t2>.
    Found 1-bit register for signal <p2l_dframe_o>.
    Found 1-bit register for signal <p2l_valid_o>.
    Found 1-bit register for signal <p2l_dframe_t2>.
    Found 1-bit register for signal <p2l_valid_t2>.
    Summary:
	inferred  68 D-type flip-flop(s).
Unit <p2l_des> synthesized.

Synthesizing Unit <serdes_1_to_n_data_s2_se_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd".
        USE_PD = false
        S = 2
        D = 16
WARNING:Xst:653 - Signal <busys> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <valid_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <incdec_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 9-bit register for signal <counter>.
    Found 4-bit register for signal <state>.
    Found 16-bit register for signal <mux>.
    Found 1-bit register for signal <cal_data_master>.
    Found 1-bit register for signal <cal_data_sint>.
    Found 1-bit register for signal <enable>.
    Found 1-bit register for signal <rst_data>.
    Found 1-bit register for signal <busy_data_d>.
    Found 16-bit register for signal <ce_data>.
    Found 1-bit register for signal <inc_data_int>.
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 17                                             |
    | Inputs             | 3                                              |
    | Outputs            | 7                                              |
    | Clock              | gclk (rising_edge)                             |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit adder for signal <counter[8]_GND_63_o_add_2_OUT> created at line 150.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  47 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <serdes_1_to_n_data_s2_se_1> synthesized.

Synthesizing Unit <serdes_1_to_n_data_s2_se_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd".
        USE_PD = false
        S = 2
        D = 1
WARNING:Xst:653 - Signal <busys> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <valid_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <incdec_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 9-bit register for signal <counter>.
    Found 5-bit register for signal <pdcounter>.
    Found 4-bit register for signal <state>.
    Found 1-bit register for signal <cal_data_master>.
    Found 1-bit register for signal <cal_data_sint>.
    Found 1-bit register for signal <enable>.
    Found 1-bit register for signal <ce_data_inta>.
    Found 1-bit register for signal <flag>.
    Found 1-bit register for signal <rst_data>.
    Found 1-bit register for signal <busy_data_d>.
    Found 1-bit register for signal <incdec_data_d>.
    Found 1-bit register for signal <valid_data_d>.
    Found 1-bit register for signal <ce_data>.
    Found 1-bit register for signal <inc_data_int>.
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 17                                             |
    | Inputs             | 3                                              |
    | Outputs            | 9                                              |
    | Clock              | gclk (rising_edge)                             |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit adder for signal <counter[8]_GND_133_o_add_1_OUT> created at line 150.
    Found 5-bit adder for signal <pdcounter[4]_GND_133_o_add_34_OUT> created at line 242.
    Found 5-bit subtractor for signal <GND_133_o_GND_133_o_sub_37_OUT<4:0>> created at line 244.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  24 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <serdes_1_to_n_data_s2_se_2> synthesized.

Synthesizing Unit <p2l_decode32>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd".
    Found 10-bit register for signal <p2l_hdr_length>.
    Found 2-bit register for signal <p2l_hdr_cid>.
    Found 2-bit register for signal <p2l_hdr_stat>.
    Found 4-bit register for signal <p2l_hdr_fbe>.
    Found 4-bit register for signal <p2l_hdr_lbe>.
    Found 4-bit register for signal <p2l_be>.
    Found 32-bit register for signal <p2l_addr>.
    Found 32-bit register for signal <p2l_d>.
    Found 1-bit register for signal <des_p2l_valid_d>.
    Found 1-bit register for signal <target_mrd>.
    Found 1-bit register for signal <target_mwr>.
    Found 1-bit register for signal <master_cpld>.
    Found 1-bit register for signal <master_cpln>.
    Found 1-bit register for signal <p2l_hdr_strobe>.
    Found 1-bit register for signal <p2l_hdr_last>.
    Found 1-bit register for signal <p2l_addr_cycle>.
    Found 1-bit register for signal <p2l_addr_start>.
    Found 1-bit register for signal <p2l_data_cycle>.
    Found 1-bit register for signal <p2l_d_valid>.
    Found 1-bit register for signal <p2l_d_last>.
    Found 1-bit register for signal <des_p2l_dframe_d>.
    Found 30-bit adder for signal <p2l_addr[31]_GND_148_o_add_17_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 103 D-type flip-flop(s).
	inferred  38 Multiplexer(s).
Unit <p2l_decode32> synthesized.

Synthesizing Unit <wbmaster32>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd".
        g_ACK_TIMEOUT = 100
WARNING:Xst:647 - Input <pd_wbm_hdr_length_i<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_wbm_addr_i<0:30>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_wbm_be_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_wbm_data_last_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 315: Output port <wr_count_o> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 315: Output port <rd_count_o> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 315: Output port <wr_empty_o> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 315: Output port <wr_full_o> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 315: Output port <wr_almost_empty_o> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 315: Output port <rd_full_o> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 315: Output port <rd_almost_empty_o> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 315: Output port <rd_almost_full_o> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <wr_count_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <rd_count_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <wr_empty_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <wr_full_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <wr_almost_empty_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <wr_almost_full_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <rd_full_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <rd_almost_empty_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" line 356: Output port <rd_almost_full_o> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
    Found 7-bit register for signal <wb_ack_timeout_cnt>.
    Found 2-bit register for signal <p2l_cid>.
    Found 2-bit register for signal <l2p_read_cpl_current_state>.
    Found 2-bit register for signal <wishbone_current_state>.
    Found 32-bit register for signal <wbm_arb_data_o>.
    Found 32-bit register for signal <wb_dat_o_t>.
    Found 32-bit register for signal <from_wb_fifo_din>.
    Found 4-bit register for signal <wb_sel_t>.
    Found 31-bit register for signal <wb_adr_t>.
    Found 64-bit register for signal <to_wb_fifo_din>.
    Found 1-bit register for signal <to_wb_fifo_wr>.
    Found 1-bit register for signal <wbm_arb_req_o>.
    Found 1-bit register for signal <wbm_arb_valid_o>.
    Found 1-bit register for signal <wbm_arb_dframe_o>.
    Found 1-bit register for signal <from_wb_fifo_rd>.
    Found 1-bit register for signal <to_wb_fifo_rd>.
    Found 1-bit register for signal <wb_cyc_t>.
    Found 1-bit register for signal <wb_stb_t>.
    Found 1-bit register for signal <wb_we_t>.
    Found 1-bit register for signal <from_wb_fifo_wr>.
    Found 1-bit register for signal <wb_ack_timeout>.
    Found finite state machine <FSM_3> for signal <l2p_read_cpl_current_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 5                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | l2p_idle                                       |
    | Power Up State     | l2p_idle                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_4> for signal <wishbone_current_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 7                                              |
    | Inputs             | 3                                              |
    | Outputs            | 11                                             |
    | Clock              | wb_clk_i (rising_edge)                         |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | wb_idle                                        |
    | Power Up State     | wb_idle                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 7-bit subtractor for signal <GND_149_o_GND_149_o_sub_48_OUT<6:0>> created at line 1308.
    Found 32-bit 3-to-1 multiplexer for signal <l2p_read_cpl_current_state[1]_X_23_o_wide_mux_11_OUT> created at line 269.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 215 D-type flip-flop(s).
	inferred  39 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <wbmaster32> synthesized.

Synthesizing Unit <generic_async_fifo_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd".
        g_data_width = 64
        g_size = 128
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = false
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = true
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 500
    Summary:
	no macro.
Unit <generic_async_fifo_1> synthesized.

Synthesizing Unit <inferred_async_fifo_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd".
        g_data_width = 64
        g_size = 128
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = false
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = true
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 500
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<7>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<6:0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<7>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<6>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<5>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_xm>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<7>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<6:0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<7>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<6>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<5>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_xm>.
    Found 128x64-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 1-bit register for signal <almost_empty_int>.
    Found 1-bit register for signal <empty_int>.
    Found 8-bit register for signal <wcb_bin>.
    Found 8-bit register for signal <wcb_gray>.
    Found 8-bit register for signal <rcb_bin>.
    Found 8-bit register for signal <rcb_gray>.
    Found 1-bit register for signal <full_int>.
    Found 8-bit register for signal <rcb_gray_x>.
    Found 8-bit register for signal <rcb_gray_xm>.
    Found 8-bit register for signal <wcb_gray_x>.
    Found 8-bit register for signal <wcb_gray_xm>.
    Found 1-bit register for signal <wr_empty_xm>.
    Found 1-bit register for signal <wr_empty_x>.
    Found 1-bit register for signal <rd_full_xm>.
    Found 1-bit register for signal <rd_full_x>.
    Found 8-bit register for signal <wr_count>.
    Found 8-bit register for signal <rd_count>.
    Found 1-bit register for signal <almost_empty_xm>.
    Found 1-bit register for signal <almost_empty_x>.
    Found 64-bit register for signal <q_o>.
    Found 8-bit adder for signal <wcb_bin_next> created at line 1241.
    Found 8-bit adder for signal <rcb_bin_next> created at line 1241.
    Found 8-bit subtractor for signal <GND_151_o_GND_151_o_sub_25_OUT<7:0>> created at line 272.
    Found 8-bit subtractor for signal <GND_151_o_GND_151_o_sub_28_OUT<7:0>> created at line 297.
    Found 8-bit comparator equal for signal <rcb_gray[7]_wcb_gray_x[7]_equal_21_o> created at line 214
    Found 8-bit comparator equal for signal <wcb_gray_x[7]_rcb_gray_next[7]_equal_22_o> created at line 214
    Found 7-bit comparator equal for signal <wcb_bin[6]_rcb_bin_x[6]_equal_23_o> created at line 235
    Found 7-bit comparator equal for signal <wcb_bin_next[6]_rcb_bin_x[6]_equal_24_o> created at line 239
    Found 8-bit comparator lessequal for signal <n0116> created at line 298
    WARNING:Xst:2404 -  FFs/Latches <almost_full_int<0:0>> (without init value) have a constant value of 0 in block <inferred_async_fifo_1>.
    WARNING:Xst:2404 -  FFs/Latches <almost_full_xm<0:0>> (without init value) have a constant value of 0 in block <inferred_async_fifo_1>.
    WARNING:Xst:2404 -  FFs/Latches <almost_full_x<0:0>> (without init value) have a constant value of 0 in block <inferred_async_fifo_1>.
    Summary:
	inferred   1 RAM(s).
	inferred   4 Adder/Subtractor(s).
	inferred 153 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <inferred_async_fifo_1> synthesized.

Synthesizing Unit <generic_async_fifo_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd".
        g_data_width = 32
        g_size = 128
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = false
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = true
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 500
    Summary:
	no macro.
Unit <generic_async_fifo_2> synthesized.

Synthesizing Unit <inferred_async_fifo_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd".
        g_data_width = 32
        g_size = 128
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = false
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = true
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 500
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<7>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<6:0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<7>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<6>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<5>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_xm>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<7>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<6:0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<7>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<6>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<5>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_xm>.
    Found 128x32-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 1-bit register for signal <almost_empty_int>.
    Found 1-bit register for signal <empty_int>.
    Found 8-bit register for signal <wcb_bin>.
    Found 8-bit register for signal <wcb_gray>.
    Found 8-bit register for signal <rcb_bin>.
    Found 8-bit register for signal <rcb_gray>.
    Found 1-bit register for signal <full_int>.
    Found 8-bit register for signal <rcb_gray_x>.
    Found 8-bit register for signal <rcb_gray_xm>.
    Found 8-bit register for signal <wcb_gray_x>.
    Found 8-bit register for signal <wcb_gray_xm>.
    Found 1-bit register for signal <wr_empty_xm>.
    Found 1-bit register for signal <wr_empty_x>.
    Found 1-bit register for signal <rd_full_xm>.
    Found 1-bit register for signal <rd_full_x>.
    Found 8-bit register for signal <wr_count>.
    Found 8-bit register for signal <rd_count>.
    Found 1-bit register for signal <almost_empty_xm>.
    Found 1-bit register for signal <almost_empty_x>.
    Found 32-bit register for signal <q_o>.
    Found 8-bit adder for signal <wcb_bin_next> created at line 1241.
    Found 8-bit adder for signal <rcb_bin_next> created at line 1241.
    Found 8-bit subtractor for signal <GND_154_o_GND_154_o_sub_25_OUT<7:0>> created at line 272.
    Found 8-bit subtractor for signal <GND_154_o_GND_154_o_sub_28_OUT<7:0>> created at line 297.
    Found 8-bit comparator equal for signal <rcb_gray[7]_wcb_gray_x[7]_equal_21_o> created at line 214
    Found 8-bit comparator equal for signal <wcb_gray_x[7]_rcb_gray_next[7]_equal_22_o> created at line 214
    Found 7-bit comparator equal for signal <wcb_bin[6]_rcb_bin_x[6]_equal_23_o> created at line 235
    Found 7-bit comparator equal for signal <wcb_bin_next[6]_rcb_bin_x[6]_equal_24_o> created at line 239
    Found 8-bit comparator lessequal for signal <n0116> created at line 298
    WARNING:Xst:2404 -  FFs/Latches <almost_full_int<0:0>> (without init value) have a constant value of 0 in block <inferred_async_fifo_2>.
    WARNING:Xst:2404 -  FFs/Latches <almost_full_xm<0:0>> (without init value) have a constant value of 0 in block <inferred_async_fifo_2>.
    WARNING:Xst:2404 -  FFs/Latches <almost_full_x<0:0>> (without init value) have a constant value of 0 in block <inferred_async_fifo_2>.
    Summary:
	inferred   1 RAM(s).
	inferred   4 Adder/Subtractor(s).
	inferred 121 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <inferred_async_fifo_2> synthesized.

Synthesizing Unit <dma_controller>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd".
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" line 216: Output port <dma_stat_o> of the instance <dma_controller_wb_slave_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" line 216: Output port <dma_stat_load_o> of the instance <dma_controller_wb_slave_0> is unconnected or connected to loadless signal.
    Found 32-bit register for signal <dma_cstart_reg>.
    Found 32-bit register for signal <dma_hstartl_reg>.
    Found 32-bit register for signal <dma_hstarth_reg>.
    Found 32-bit register for signal <dma_len_reg>.
    Found 32-bit register for signal <dma_nextl_reg>.
    Found 32-bit register for signal <dma_nexth_reg>.
    Found 32-bit register for signal <dma_attrib_reg>.
    Found 32-bit register for signal <dma_ctrl_carrier_addr_o>.
    Found 32-bit register for signal <dma_ctrl_host_addr_h_o>.
    Found 32-bit register for signal <dma_ctrl_host_addr_l_o>.
    Found 32-bit register for signal <dma_ctrl_len_o>.
    Found 32-bit register for signal <dma_ctrl_reg>.
    Found 3-bit register for signal <dma_ctrl_current_state>.
    Found 3-bit register for signal <dma_status>.
    Found 3-bit register for signal <dma_stat_reg>.
    Found 1-bit register for signal <dma_ctrl_start_l2p_o>.
    Found 1-bit register for signal <dma_ctrl_start_p2l_o>.
    Found 1-bit register for signal <dma_ctrl_start_next_o>.
    Found 1-bit register for signal <dma_error_irq>.
    Found 1-bit register for signal <dma_done_irq>.
    Found 1-bit register for signal <dma_ctrl_abort_o>.
    Found finite state machine <FSM_5> for signal <dma_ctrl_current_state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 18                                             |
    | Inputs             | 7                                              |
    | Outputs            | 12                                             |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | dma_idle                                       |
    | Power Up State     | dma_idle                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    WARNING:Xst:2404 -  FFs/Latches <dma_stat_reg<31:3>> (without init value) have a constant value of 0 in block <dma_controller>.
    Summary:
	inferred 396 D-type flip-flop(s).
	inferred  13 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <dma_controller> synthesized.

Synthesizing Unit <dma_controller_wb_slave>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 32-bit register for signal <dma_ctrl_int_write>.
    Found 32-bit register for signal <dma_stat_int_write>.
    Found 32-bit register for signal <dma_cstart_int_write>.
    Found 32-bit register for signal <dma_hstartl_int_write>.
    Found 32-bit register for signal <dma_hstarth_int_write>.
    Found 32-bit register for signal <dma_len_int_write>.
    Found 32-bit register for signal <dma_nextl_int_write>.
    Found 32-bit register for signal <dma_nexth_int_write>.
    Found 32-bit register for signal <dma_attrib_int_write>.
    Found 32-bit register for signal <dma_ctrl_o>.
    Found 32-bit register for signal <dma_ctrl_int_read>.
    Found 32-bit register for signal <dma_stat_o>.
    Found 32-bit register for signal <dma_stat_int_read>.
    Found 32-bit register for signal <dma_cstart_o>.
    Found 32-bit register for signal <dma_cstart_int_read>.
    Found 32-bit register for signal <dma_hstartl_o>.
    Found 32-bit register for signal <dma_hstartl_int_read>.
    Found 32-bit register for signal <dma_hstarth_o>.
    Found 32-bit register for signal <dma_hstarth_int_read>.
    Found 32-bit register for signal <dma_len_o>.
    Found 32-bit register for signal <dma_len_int_read>.
    Found 32-bit register for signal <dma_nextl_o>.
    Found 32-bit register for signal <dma_nextl_int_read>.
    Found 32-bit register for signal <dma_nexth_o>.
    Found 32-bit register for signal <dma_nexth_int_read>.
    Found 32-bit register for signal <dma_attrib_o>.
    Found 32-bit register for signal <dma_attrib_int_read>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <dma_ctrl_lw>.
    Found 1-bit register for signal <dma_ctrl_lw_delay>.
    Found 1-bit register for signal <dma_ctrl_lw_read_in_progress>.
    Found 1-bit register for signal <dma_ctrl_rwsel>.
    Found 1-bit register for signal <dma_stat_lw>.
    Found 1-bit register for signal <dma_stat_lw_delay>.
    Found 1-bit register for signal <dma_stat_lw_read_in_progress>.
    Found 1-bit register for signal <dma_stat_rwsel>.
    Found 1-bit register for signal <dma_cstart_lw>.
    Found 1-bit register for signal <dma_cstart_lw_delay>.
    Found 1-bit register for signal <dma_cstart_lw_read_in_progress>.
    Found 1-bit register for signal <dma_cstart_rwsel>.
    Found 1-bit register for signal <dma_hstartl_lw>.
    Found 1-bit register for signal <dma_hstartl_lw_delay>.
    Found 1-bit register for signal <dma_hstartl_lw_read_in_progress>.
    Found 1-bit register for signal <dma_hstartl_rwsel>.
    Found 1-bit register for signal <dma_hstarth_lw>.
    Found 1-bit register for signal <dma_hstarth_lw_delay>.
    Found 1-bit register for signal <dma_hstarth_lw_read_in_progress>.
    Found 1-bit register for signal <dma_hstarth_rwsel>.
    Found 1-bit register for signal <dma_len_lw>.
    Found 1-bit register for signal <dma_len_lw_delay>.
    Found 1-bit register for signal <dma_len_lw_read_in_progress>.
    Found 1-bit register for signal <dma_len_rwsel>.
    Found 1-bit register for signal <dma_nextl_lw>.
    Found 1-bit register for signal <dma_nextl_lw_delay>.
    Found 1-bit register for signal <dma_nextl_lw_read_in_progress>.
    Found 1-bit register for signal <dma_nextl_rwsel>.
    Found 1-bit register for signal <dma_nexth_lw>.
    Found 1-bit register for signal <dma_nexth_lw_delay>.
    Found 1-bit register for signal <dma_nexth_lw_read_in_progress>.
    Found 1-bit register for signal <dma_nexth_rwsel>.
    Found 1-bit register for signal <dma_attrib_lw>.
    Found 1-bit register for signal <dma_attrib_lw_delay>.
    Found 1-bit register for signal <dma_attrib_lw_read_in_progress>.
    Found 1-bit register for signal <dma_attrib_rwsel>.
    Found 1-bit register for signal <dma_ctrl_lw_s0>.
    Found 1-bit register for signal <dma_ctrl_lw_s1>.
    Found 1-bit register for signal <dma_ctrl_lw_s2>.
    Found 1-bit register for signal <dma_ctrl_load_o>.
    Found 1-bit register for signal <dma_stat_lw_s0>.
    Found 1-bit register for signal <dma_stat_lw_s1>.
    Found 1-bit register for signal <dma_stat_lw_s2>.
    Found 1-bit register for signal <dma_stat_load_o>.
    Found 1-bit register for signal <dma_cstart_lw_s0>.
    Found 1-bit register for signal <dma_cstart_lw_s1>.
    Found 1-bit register for signal <dma_cstart_lw_s2>.
    Found 1-bit register for signal <dma_cstart_load_o>.
    Found 1-bit register for signal <dma_hstartl_lw_s0>.
    Found 1-bit register for signal <dma_hstartl_lw_s1>.
    Found 1-bit register for signal <dma_hstartl_lw_s2>.
    Found 1-bit register for signal <dma_hstartl_load_o>.
    Found 1-bit register for signal <dma_hstarth_lw_s0>.
    Found 1-bit register for signal <dma_hstarth_lw_s1>.
    Found 1-bit register for signal <dma_hstarth_lw_s2>.
    Found 1-bit register for signal <dma_hstarth_load_o>.
    Found 1-bit register for signal <dma_len_lw_s0>.
    Found 1-bit register for signal <dma_len_lw_s1>.
    Found 1-bit register for signal <dma_len_lw_s2>.
    Found 1-bit register for signal <dma_len_load_o>.
    Found 1-bit register for signal <dma_nextl_lw_s0>.
    Found 1-bit register for signal <dma_nextl_lw_s1>.
    Found 1-bit register for signal <dma_nextl_lw_s2>.
    Found 1-bit register for signal <dma_nextl_load_o>.
    Found 1-bit register for signal <dma_nexth_lw_s0>.
    Found 1-bit register for signal <dma_nexth_lw_s1>.
    Found 1-bit register for signal <dma_nexth_lw_s2>.
    Found 1-bit register for signal <dma_nexth_load_o>.
    Found 1-bit register for signal <dma_attrib_lw_s0>.
    Found 1-bit register for signal <dma_attrib_lw_s1>.
    Found 1-bit register for signal <dma_attrib_lw_s2>.
    Found 1-bit register for signal <dma_attrib_load_o>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <dma_controller_wb_slave>.
    Summary:
	inferred 978 D-type flip-flop(s).
	inferred  41 Multiplexer(s).
Unit <dma_controller_wb_slave> synthesized.

Synthesizing Unit <pulse_synchronizer>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd".
    Found 3-bit register for signal <s_input_sync>.
    Found 1-bit register for signal <s_gotit_toggle>.
    Found 3-bit register for signal <s_gotit_sync>.
    Found 1-bit register for signal <s_input_toggle>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <pulse_synchronizer> synthesized.

Synthesizing Unit <l2p_dma_master>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd".
        g_BYTE_SWAP = false
WARNING:Xst:647 - Input <dma_ctrl_target_addr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_ctrl_len_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_ctrl_byte_swap_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 504: Output port <wr_count_o> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 504: Output port <rd_count_o> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 504: Output port <wr_empty_o> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 504: Output port <wr_full_o> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 504: Output port <wr_almost_empty_o> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 504: Output port <rd_full_o> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 504: Output port <rd_almost_empty_o> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 504: Output port <rd_almost_full_o> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 547: Output port <wr_count_o> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 547: Output port <rd_count_o> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 547: Output port <wr_empty_o> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 547: Output port <wr_full_o> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 547: Output port <wr_almost_empty_o> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 547: Output port <rd_full_o> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 547: Output port <rd_almost_empty_o> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 547: Output port <rd_almost_full_o> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
    Found 30-bit register for signal <dma_length_cnt>.
    Found 30-bit register for signal <l2p_len_cnt>.
    Found 30-bit register for signal <target_addr_cnt>.
    Found 11-bit register for signal <l2p_data_cnt>.
    Found 32-bit register for signal <l2p_address_h>.
    Found 32-bit register for signal <l2p_address_l>.
    Found 32-bit register for signal <ldm_arb_data_o>.
    Found 32-bit register for signal <l2p_dma_adr_o>.
    Found 32-bit register for signal <wb_read_cnt>.
    Found 32-bit register for signal <wb_ack_cnt>.
    Found 10-bit register for signal <l2p_len_header>.
    Found 3-bit register for signal <l2p_dma_current_state>.
    Found 4-bit register for signal <l2p_dma_sel_o>.
    Found 1-bit register for signal <dma_ctrl_error_o>.
    Found 1-bit register for signal <addr_fifo_wr>.
    Found 1-bit register for signal <l2p_64b_address>.
    Found 1-bit register for signal <l2p_last_packet>.
    Found 1-bit register for signal <ldm_arb_req_o>.
    Found 1-bit register for signal <ldm_arb_valid_o>.
    Found 1-bit register for signal <ldm_arb_dframe_o>.
    Found 1-bit register for signal <data_fifo_rd>.
    Found 1-bit register for signal <dma_ctrl_done_o>.
    Found 1-bit register for signal <l2p_edb_o>.
    Found 1-bit register for signal <l2p_dma_stb_t>.
    Found 1-bit register for signal <l2p_dma_cyc_t>.
    Found 32-bit register for signal <addr_fifo_din>.
    Found 1-bit register for signal <addr_fifo_valid>.
    Found 1-bit register for signal <data_fifo_valid>.
    Found finite state machine <FSM_6> for signal <l2p_dma_current_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 23                                             |
    | Inputs             | 9                                              |
    | Outputs            | 11                                             |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | l2p_idle                                       |
    | Power Up State     | l2p_idle                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 30-bit adder for signal <target_addr_cnt[29]_GND_160_o_add_4_OUT> created at line 1241.
    Found 32-bit adder for signal <l2p_address_l[31]_GND_160_o_add_35_OUT> created at line 284.
    Found 32-bit adder for signal <wb_read_cnt[31]_GND_160_o_add_112_OUT> created at line 1241.
    Found 32-bit adder for signal <wb_ack_cnt[31]_GND_160_o_add_115_OUT> created at line 1241.
    Found 30-bit subtractor for signal <GND_160_o_GND_160_o_sub_6_OUT<29:0>> created at line 1308.
    Found 30-bit subtractor for signal <GND_160_o_GND_160_o_sub_31_OUT<29:0>> created at line 276.
    Found 11-bit subtractor for signal <GND_160_o_GND_160_o_sub_34_OUT<10:0>> created at line 1308.
    Found 32-bit subtractor for signal <GND_160_o_GND_160_o_sub_109_OUT<31:0>> created at line 1308.
    Found 30-bit comparator greater for signal <GND_160_o_l2p_len_cnt[29]_LessThan_37_o> created at line 286
    Found 11-bit comparator greater for signal <n0100> created at line 424
    Found 11-bit comparator greater for signal <n0113> created at line 437
    Found 32-bit comparator equal for signal <wb_ack_cnt[31]_GND_160_o_equal_110_o> created at line 634
    Summary:
	inferred   8 Adder/Subtractor(s).
	inferred 353 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  31 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <l2p_dma_master> synthesized.

Synthesizing Unit <generic_async_fifo_3>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd".
        g_data_width = 32
        g_size = 512
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = false
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = true
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 500
    Summary:
	no macro.
Unit <generic_async_fifo_3> synthesized.

Synthesizing Unit <inferred_async_fifo_3>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd".
        g_data_width = 32
        g_size = 512
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = false
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = true
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 500
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<9>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<8:0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<9>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<8>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<7>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<6>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<5>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_xm>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<9>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<8:0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<9>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<8>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<7>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<6>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<5>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_xm>.
    Found 512x32-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 1-bit register for signal <almost_empty_int>.
    Found 1-bit register for signal <empty_int>.
    Found 10-bit register for signal <wcb_bin>.
    Found 10-bit register for signal <wcb_gray>.
    Found 10-bit register for signal <rcb_bin>.
    Found 10-bit register for signal <rcb_gray>.
    Found 1-bit register for signal <full_int>.
    Found 1-bit register for signal <almost_full_int>.
    Found 10-bit register for signal <rcb_gray_x>.
    Found 10-bit register for signal <rcb_gray_xm>.
    Found 10-bit register for signal <wcb_gray_x>.
    Found 10-bit register for signal <wcb_gray_xm>.
    Found 1-bit register for signal <wr_empty_xm>.
    Found 1-bit register for signal <wr_empty_x>.
    Found 1-bit register for signal <rd_full_xm>.
    Found 1-bit register for signal <rd_full_x>.
    Found 10-bit register for signal <wr_count>.
    Found 1-bit register for signal <almost_full_xm>.
    Found 1-bit register for signal <almost_full_x>.
    Found 10-bit register for signal <rd_count>.
    Found 1-bit register for signal <almost_empty_xm>.
    Found 1-bit register for signal <almost_empty_x>.
    Found 32-bit register for signal <q_o>.
    Found 10-bit adder for signal <wcb_bin_next> created at line 1241.
    Found 10-bit adder for signal <rcb_bin_next> created at line 1241.
    Found 10-bit subtractor for signal <GND_162_o_GND_162_o_sub_25_OUT<9:0>> created at line 272.
    Found 10-bit subtractor for signal <GND_162_o_GND_162_o_sub_29_OUT<9:0>> created at line 297.
    Found 10-bit comparator equal for signal <rcb_gray[9]_wcb_gray_x[9]_equal_21_o> created at line 214
    Found 10-bit comparator equal for signal <wcb_gray_x[9]_rcb_gray_next[9]_equal_22_o> created at line 214
    Found 9-bit comparator equal for signal <wcb_bin[8]_rcb_bin_x[8]_equal_23_o> created at line 235
    Found 9-bit comparator equal for signal <wcb_bin_next[8]_rcb_bin_x[8]_equal_24_o> created at line 239
    Found 10-bit comparator lessequal for signal <n0142> created at line 273
    Found 10-bit comparator lessequal for signal <n0152> created at line 298
    Summary:
	inferred   1 RAM(s).
	inferred   4 Adder/Subtractor(s).
	inferred 144 D-type flip-flop(s).
	inferred   6 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <inferred_async_fifo_3> synthesized.

Synthesizing Unit <p2l_dma_master>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd".
        g_BYTE_SWAP = false
WARNING:Xst:647 - Input <dma_ctrl_carrier_addr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_ctrl_len_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_ctrl_byte_swap_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_pdm_hdr_length_i<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_pdm_hdr_cid_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_pdm_be_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2l_dma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_pdm_hdr_start_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 512: Output port <wr_count_o> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 512: Output port <rd_count_o> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 512: Output port <wr_empty_o> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 512: Output port <wr_full_o> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 512: Output port <wr_almost_empty_o> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 512: Output port <rd_full_o> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 512: Output port <rd_almost_empty_o> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 512: Output port <rd_almost_full_o> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
    Found 32-bit register for signal <l2p_address_l>.
    Found 32-bit register for signal <pdm_arb_data_o>.
    Found 32-bit register for signal <next_item_carrier_addr_o>.
    Found 32-bit register for signal <next_item_host_addr_h_o>.
    Found 32-bit register for signal <next_item_host_addr_l_o>.
    Found 32-bit register for signal <next_item_len_o>.
    Found 32-bit register for signal <next_item_next_l_o>.
    Found 32-bit register for signal <next_item_next_h_o>.
    Found 32-bit register for signal <next_item_attrib_o>.
    Found 32-bit register for signal <p2l_dma_adr_o>.
    Found 32-bit register for signal <p2l_dma_dat_o>.
    Found 32-bit register for signal <wb_write_cnt>.
    Found 32-bit register for signal <wb_ack_cnt>.
    Found 32-bit register for signal <l2p_address_h>.
    Found 30-bit register for signal <l2p_len_cnt>.
    Found 30-bit register for signal <target_addr_cnt>.
    Found 10-bit register for signal <l2p_len_header>.
    Found 3-bit register for signal <p2l_dma_current_state>.
    Found 11-bit register for signal <p2l_data_cnt>.
    Found 4-bit register for signal <p2l_dma_sel_o>.
    Found 1-bit register for signal <l2p_64b_address>.
    Found 1-bit register for signal <is_next_item>.
    Found 1-bit register for signal <l2p_last_packet>.
    Found 1-bit register for signal <pdm_arb_req_o>.
    Found 1-bit register for signal <pdm_arb_valid_o>.
    Found 1-bit register for signal <pdm_arb_dframe_o>.
    Found 1-bit register for signal <dma_ctrl_done_t>.
    Found 1-bit register for signal <next_item_valid_o>.
    Found 1-bit register for signal <completion_error>.
    Found 1-bit register for signal <rx_error_t>.
    Found 1-bit register for signal <rx_error_o>.
    Found 1-bit register for signal <dma_ctrl_done_o>.
    Found 1-bit register for signal <dma_busy_error>.
    Found 1-bit register for signal <to_wb_fifo_din<61>>.
    Found 1-bit register for signal <to_wb_fifo_din<60>>.
    Found 1-bit register for signal <to_wb_fifo_din<59>>.
    Found 1-bit register for signal <to_wb_fifo_din<58>>.
    Found 1-bit register for signal <to_wb_fifo_din<57>>.
    Found 1-bit register for signal <to_wb_fifo_din<56>>.
    Found 1-bit register for signal <to_wb_fifo_din<55>>.
    Found 1-bit register for signal <to_wb_fifo_din<54>>.
    Found 1-bit register for signal <to_wb_fifo_din<53>>.
    Found 1-bit register for signal <to_wb_fifo_din<52>>.
    Found 1-bit register for signal <to_wb_fifo_din<51>>.
    Found 1-bit register for signal <to_wb_fifo_din<50>>.
    Found 1-bit register for signal <to_wb_fifo_din<49>>.
    Found 1-bit register for signal <to_wb_fifo_din<48>>.
    Found 1-bit register for signal <to_wb_fifo_din<47>>.
    Found 1-bit register for signal <to_wb_fifo_din<46>>.
    Found 1-bit register for signal <to_wb_fifo_din<45>>.
    Found 1-bit register for signal <to_wb_fifo_din<44>>.
    Found 1-bit register for signal <to_wb_fifo_din<43>>.
    Found 1-bit register for signal <to_wb_fifo_din<42>>.
    Found 1-bit register for signal <to_wb_fifo_din<41>>.
    Found 1-bit register for signal <to_wb_fifo_din<40>>.
    Found 1-bit register for signal <to_wb_fifo_din<39>>.
    Found 1-bit register for signal <to_wb_fifo_din<38>>.
    Found 1-bit register for signal <to_wb_fifo_din<37>>.
    Found 1-bit register for signal <to_wb_fifo_din<36>>.
    Found 1-bit register for signal <to_wb_fifo_din<35>>.
    Found 1-bit register for signal <to_wb_fifo_din<34>>.
    Found 1-bit register for signal <to_wb_fifo_din<33>>.
    Found 1-bit register for signal <to_wb_fifo_din<32>>.
    Found 1-bit register for signal <to_wb_fifo_din<31>>.
    Found 1-bit register for signal <to_wb_fifo_din<30>>.
    Found 1-bit register for signal <to_wb_fifo_din<29>>.
    Found 1-bit register for signal <to_wb_fifo_din<28>>.
    Found 1-bit register for signal <to_wb_fifo_din<27>>.
    Found 1-bit register for signal <to_wb_fifo_din<26>>.
    Found 1-bit register for signal <to_wb_fifo_din<25>>.
    Found 1-bit register for signal <to_wb_fifo_din<24>>.
    Found 1-bit register for signal <to_wb_fifo_din<23>>.
    Found 1-bit register for signal <to_wb_fifo_din<22>>.
    Found 1-bit register for signal <to_wb_fifo_din<21>>.
    Found 1-bit register for signal <to_wb_fifo_din<20>>.
    Found 1-bit register for signal <to_wb_fifo_din<19>>.
    Found 1-bit register for signal <to_wb_fifo_din<18>>.
    Found 1-bit register for signal <to_wb_fifo_din<17>>.
    Found 1-bit register for signal <to_wb_fifo_din<16>>.
    Found 1-bit register for signal <to_wb_fifo_din<15>>.
    Found 1-bit register for signal <to_wb_fifo_din<14>>.
    Found 1-bit register for signal <to_wb_fifo_din<13>>.
    Found 1-bit register for signal <to_wb_fifo_din<12>>.
    Found 1-bit register for signal <to_wb_fifo_din<11>>.
    Found 1-bit register for signal <to_wb_fifo_din<10>>.
    Found 1-bit register for signal <to_wb_fifo_din<9>>.
    Found 1-bit register for signal <to_wb_fifo_din<8>>.
    Found 1-bit register for signal <to_wb_fifo_din<7>>.
    Found 1-bit register for signal <to_wb_fifo_din<6>>.
    Found 1-bit register for signal <to_wb_fifo_din<5>>.
    Found 1-bit register for signal <to_wb_fifo_din<4>>.
    Found 1-bit register for signal <to_wb_fifo_din<3>>.
    Found 1-bit register for signal <to_wb_fifo_din<2>>.
    Found 1-bit register for signal <to_wb_fifo_din<1>>.
    Found 1-bit register for signal <to_wb_fifo_din<0>>.
    Found 1-bit register for signal <to_wb_fifo_wr>.
    Found 1-bit register for signal <p2l_dma_cyc_t>.
    Found 1-bit register for signal <p2l_dma_stb_t>.
    Found 1-bit register for signal <to_wb_fifo_valid>.
    Found finite state machine <FSM_7> for signal <p2l_dma_current_state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 16                                             |
    | Inputs             | 9                                              |
    | Outputs            | 13                                             |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | p2l_idle                                       |
    | Power Up State     | p2l_idle                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 30-bit adder for signal <target_addr_cnt[29]_GND_164_o_add_81_OUT> created at line 1241.
    Found 32-bit adder for signal <wb_write_cnt[31]_GND_164_o_add_95_OUT> created at line 1241.
    Found 32-bit adder for signal <wb_ack_cnt[31]_GND_164_o_add_98_OUT> created at line 1241.
    Found 30-bit subtractor for signal <GND_164_o_GND_164_o_sub_12_OUT<29:0>> created at line 263.
    Found 11-bit subtractor for signal <GND_164_o_GND_164_o_sub_52_OUT<10:0>> created at line 1308.
    Found 32-bit subtractor for signal <GND_164_o_GND_164_o_sub_91_OUT<31:0>> created at line 1308.
    Found 30-bit comparator greater for signal <GND_164_o_l2p_len_cnt[29]_LessThan_7_o> created at line 248
    Found 11-bit comparator greater for signal <n0049> created at line 356
    Found 32-bit comparator equal for signal <wb_ack_cnt[31]_GND_164_o_equal_92_o> created at line 596
    Summary:
	inferred   6 Adder/Subtractor(s).
	inferred 612 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   9 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <p2l_dma_master> synthesized.

Synthesizing Unit <generic_async_fifo_4>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd".
        g_data_width = 64
        g_size = 512
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = false
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = true
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 500
    Summary:
	no macro.
Unit <generic_async_fifo_4> synthesized.

Synthesizing Unit <inferred_async_fifo_4>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd".
        g_data_width = 64
        g_size = 512
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = false
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = true
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 500
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<9>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<8:0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<9>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<8>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<7>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<6>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<5>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_xm>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<9>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<8:0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<9>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<8>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<7>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<6>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<5>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_xm>.
    Found 512x64-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 1-bit register for signal <almost_empty_int>.
    Found 1-bit register for signal <empty_int>.
    Found 10-bit register for signal <wcb_bin>.
    Found 10-bit register for signal <wcb_gray>.
    Found 10-bit register for signal <rcb_bin>.
    Found 10-bit register for signal <rcb_gray>.
    Found 1-bit register for signal <full_int>.
    Found 1-bit register for signal <almost_full_int>.
    Found 10-bit register for signal <rcb_gray_x>.
    Found 10-bit register for signal <rcb_gray_xm>.
    Found 10-bit register for signal <wcb_gray_x>.
    Found 10-bit register for signal <wcb_gray_xm>.
    Found 1-bit register for signal <wr_empty_xm>.
    Found 1-bit register for signal <wr_empty_x>.
    Found 1-bit register for signal <rd_full_xm>.
    Found 1-bit register for signal <rd_full_x>.
    Found 10-bit register for signal <wr_count>.
    Found 1-bit register for signal <almost_full_xm>.
    Found 1-bit register for signal <almost_full_x>.
    Found 10-bit register for signal <rd_count>.
    Found 1-bit register for signal <almost_empty_xm>.
    Found 1-bit register for signal <almost_empty_x>.
    Found 64-bit register for signal <q_o>.
    Found 10-bit adder for signal <wcb_bin_next> created at line 1241.
    Found 10-bit adder for signal <rcb_bin_next> created at line 1241.
    Found 10-bit subtractor for signal <GND_168_o_GND_168_o_sub_25_OUT<9:0>> created at line 272.
    Found 10-bit subtractor for signal <GND_168_o_GND_168_o_sub_29_OUT<9:0>> created at line 297.
    Found 10-bit comparator equal for signal <rcb_gray[9]_wcb_gray_x[9]_equal_21_o> created at line 214
    Found 10-bit comparator equal for signal <wcb_gray_x[9]_rcb_gray_next[9]_equal_22_o> created at line 214
    Found 9-bit comparator equal for signal <wcb_bin[8]_rcb_bin_x[8]_equal_23_o> created at line 235
    Found 9-bit comparator equal for signal <wcb_bin_next[8]_rcb_bin_x[8]_equal_24_o> created at line 239
    Found 10-bit comparator lessequal for signal <n0142> created at line 273
    Found 10-bit comparator lessequal for signal <n0152> created at line 298
    Summary:
	inferred   1 RAM(s).
	inferred   4 Adder/Subtractor(s).
	inferred 176 D-type flip-flop(s).
	inferred   6 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <inferred_async_fifo_4> synthesized.

Synthesizing Unit <l2p_arbiter>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd".
    Found 32-bit register for signal <arb_ser_data_t>.
    Found 32-bit register for signal <arb_ser_data_o>.
    Found 1-bit register for signal <arb_pdm_gnt>.
    Found 1-bit register for signal <arb_ldm_gnt>.
    Found 1-bit register for signal <arb_ser_valid_t>.
    Found 1-bit register for signal <arb_ser_dframe_t>.
    Found 1-bit register for signal <arb_ser_valid_o>.
    Found 1-bit register for signal <arb_ser_dframe_o>.
    Found 1-bit register for signal <arb_wbm_gnt>.
    Summary:
	inferred  71 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <l2p_arbiter> synthesized.

Synthesizing Unit <l2p_ser>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd".
    Summary:
	no macro.
Unit <l2p_ser> synthesized.

Synthesizing Unit <serdes_n_to_1_s2_diff>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd".
        S = 2
        D = 1
WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <serdes_n_to_1_s2_diff> synthesized.

Synthesizing Unit <serdes_n_to_1_s2_se_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd".
        S = 2
        D = 16
WARNING:Xst:653 - Signal <mdatainb<63:62>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<59:58>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<55:54>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<51:50>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<47:46>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<43:42>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<39:38>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<35:34>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<31:30>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<27:26>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<23:22>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<19:18>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<15:14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<11:10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<7:6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <serdes_n_to_1_s2_se_1> synthesized.

Synthesizing Unit <serdes_n_to_1_s2_se_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd".
        S = 2
        D = 1
WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <serdes_n_to_1_s2_se_2> synthesized.

Synthesizing Unit <xwb_sdb_crossbar_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd".
        g_num_masters = 1
        g_num_slaves = 6
        g_registered = true
        g_wraparound = true
        g_layout =
("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001110010000100100011111000111100001101010001000000000000001000000000000000000001000000001010000000100001001010111001101110000011001010110001101011111011001100110110101100011011000010110010001100011001100010011000000110000011011010011000100110100011000100010000010000000","011100110111000001100101011000110101111101110100011011110111000001011111011001100110110101100011010111110110000101100100011000111011110101010011001110101000101000100100100100110011101110111010010100010010110000110111100000011010000011111001010001110110001001001001010100110100010100100000001000000010000000100000001000000000000000000000000000010011001100100000000101000000010000100101011011010110001101100001011101000111010001101001011011100010000000100000001000000010000000100000001000000010000000100000100
00010","01100111011010010111010000111010001011110010111101101111011010000111011101110010001011100110111101110010011001110010111101100110011011010110001100101101011100000111001001101111011010100110010101100011011101000111001100101111011001100110110101100011001011010110000101100100011000110010110100110001001100000011000001101101001100010011010001100010001101000110001101101000011000010010111001100111011010010111010000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000010000001","000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100
00000000010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000000000000001010000000000000000000000000000000000000000000000000000000000000101000000111100000000000000000000000000000000000000000000000011001110010000101101010101110011010110101011010000000000000000000000000000000001001000000001001100010010000001000101011101000010001011010100010001001101010000010010111001000101010010010100001100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000001001111111111000000000000000000000000000000000000000000000000110011100100001000000000000000000000000000010011000000000000000000000000000000100010000000010010000000010001001101010111010000100010110101010110010010010100001100101101010010010110111001110100001011100100001101101111011011100111010001110010011011110110110
00010000000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000000100100001111100000000000000000000000000000000000000000000000011001110010000100000000000000000000001100000001100000000000000000000000000000001001000000001001000010001000101100101011101000010001011010101001101010000010001010100001100101101010000110101001101010010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000001000111111111000000000000000000000000000000000000000000000000110011100100001001110111100111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001111011011100110010101010111011010010111001001100101001011010100110101100001011100110111010001100101011100100
01000000010000000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000011111100000000000000000000000000000000000000000000000011001110010000100000000000000000000001100000000100000000000000000000000000000001001000000001001000010001000101100101011101000010001011010100010001001101010000010010111001000011011011110110111001110100011100100110111101101100001000000010000000100000001000000010000000000001")
        g_sdb_addr = "00000000000000000000000000000000"
    Summary:
	no macro.
Unit <xwb_sdb_crossbar_1> synthesized.

Synthesizing Unit <sdb_rom_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd".
        g_layout =
("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001110010000100100011111000111100001101010001000000000000001000000000000000000001000000001010000000100001001010111001101110000011001010110001101011111011001100110110101100011011000010110010001100011001100010011000000110000011011010011000100110100011000100010000010000000","011100110111000001100101011000110101111101110100011011110111000001011111011001100110110101100011010111110110000101100100011000111011110101010011001110101000101000100100100100110011101110111010010100010010110000110111100000011010000011111001010001110110001001001001010100110100010100100000001000000010000000100000001000000000000000000000000000010011001100100000000101000000010000100101011011010110001101100001011101000111010001101001011011100010000000100000001000000010000000100000001000000010000000100000100
00010","01100111011010010111010000111010001011110010111101101111011010000111011101110010001011100110111101110010011001110010111101100110011011010110001100101101011100000111001001101111011010100110010101100011011101000111001100101111011001100110110101100011001011010110000101100100011000110010110100110001001100000011000001101101001100010011010001100010001101000110001101101000011000010010111001100111011010010111010000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000010000001","000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100
00000000010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000000000000001010000000000000000000000000000000000000000000000000000000000000101000000111100000000000000000000000000000000000000000000000011001110010000101101010101110011010110101011010000000000000000000000000000000001001000000001001100010010000001000101011101000010001011010100010001001101010000010010111001000101010010010100001100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000001001111111111000000000000000000000000000000000000000000000000110011100100001000000000000000000000000000010011000000000000000000000000000000100010000000010010000000010001001101010111010000100010110101010110010010010100001100101101010010010110111001110100001011100100001101101111011011100111010001110010011011110110110
00010000000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000000100100001111100000000000000000000000000000000000000000000000011001110010000100000000000000000000001100000001100000000000000000000000000000001001000000001001000010001000101100101011101000010001011010101001101010000010001010100001100101101010000110101001101010010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000001000111111111000000000000000000000000000000000000000000000000110011100100001001110111100111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001111011011100110010101010111011010010111001001100101001011010100110101100001011100110111010001100101011100100
01000000010000000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000011111100000000000000000000000000000000000000000000000011001110010000100000000000000000000001100000000100000000000000000000000000000001001000000001001000010001000101100101011101000010001011010100010001001101010000010010111001000011011011110110111001110100011100100110111101101100001000000010000000100000001000000010000000000001")
        g_bus_end = "0000000000000000000000000000000000000000000000000011111111111111"
WARNING:Xst:647 - Input <slave_i_adr<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_1', is tied to its initial value.
    Found 256x32-bit single-port Read Only RAM <Mram_rom> for signal <rom>.
    Found 1-bit register for signal <slave_o_ack>.
    Found 8-bit register for signal <adr_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   9 D-type flip-flop(s).
Unit <sdb_rom_1> synthesized.

Synthesizing Unit <xwb_crossbar_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd".
        g_num_masters = 1
        g_num_slaves = 7
        g_registered = true
        g_address = ("00000000000000000000000000000000","00000000000000000010000000000000","00000000000000000001010000000000","00000000000000000001001100000000","00000000000000000001001000000000","00000000000000000001000100000000","00000000000000000001000000000000")
        g_mask = ("00000000000000000011110000000000","00000000000000000010000000000000","00000000000000000011111111110000","00000000000000000011111100000000","00000000000000000011111111100000","00000000000000000011111100000000","00000000000000000011111111000000")
WARNING:Xst:647 - Input <master_i[6]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[5]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[4]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[3]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[2]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[1]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[0]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 8-bit register for signal <matrix_old<0>>.
    Found 1-bit register for signal <virtual_ERR>.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <xwb_crossbar_1> synthesized.

Synthesizing Unit <xwb_onewire_master>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
        g_num_ports = 1
        g_ow_btp_normal = "5.0"
        g_ow_btp_overdrive = "1.0"
WARNING:Xst:647 - Input <slave_i_adr<31:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <xwb_onewire_master> synthesized.

Synthesizing Unit <wb_onewire_master>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
        g_num_ports = 1
        g_ow_btp_normal = "5.0"
        g_ow_btp_overdrive = "1.0"
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <sl_dat_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <ma_adr_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <ma_dat_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <ma_sel_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <master_o_sel> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <sl_err_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <sl_rty_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <sl_ack_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <sl_stall_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <sl_int_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <slave_o_err> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <slave_o_rty> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <ma_cyc_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <ma_stb_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port <ma_we_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <adp_in_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <adp_in_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <adp_in_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 32-bit register for signal <adp_in_dat>.
    Found 1-bit register for signal <adp_in_ack>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <wb_onewire_master> synthesized.

Synthesizing Unit <wb_slave_adapter_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = word
        g_slave_use_struct = true
        g_slave_mode = classic
        g_slave_granularity = byte
WARNING:Xst:647 - Input <sl_adr_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_cyc_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_stb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_we_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <wb_slave_adapter_1> synthesized.

Synthesizing Unit <sockit_owm>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v".
        OVD_E = 1
        CDR_E = 1
        BDW = 32
        OWN = 1
        BAW = 1
        BTP_N = "5.0"
        BTP_O = "1.0"
        T_RSTH_N = 96
        T_RSTL_N = 96
        T_RSTP_N = 15
        T_DAT0_N = 12
        T_DAT1_N = 1
        T_BITS_N = 3
        T_RCVR_N = 1
        T_IDLE_N = 200
        T_RSTH_O = 48
        T_RSTL_O = 48
        T_RSTP_O = 10
        T_DAT0_O = 6
        T_DAT1_O = 1
        T_BITS_O = 2
        T_RCVR_O = 2
        T_IDLE_O = 96
        CDR_N = 4
        CDR_O = 0
WARNING:Xst:2935 - Signal 'owr_sel', unconnected in block 'sockit_owm', is tied to its initial value (0).
    Found 16-bit register for signal <cdr_o>.
    Found 16-bit register for signal <div>.
    Found 8-bit register for signal <cnt>.
    Found 16-bit register for signal <cdr_n>.
    Found 1-bit register for signal <owr_pwr>.
    Found 1-bit register for signal <irq_ena>.
    Found 1-bit register for signal <irq_sts>.
    Found 1-bit register for signal <owr_ovd>.
    Found 1-bit register for signal <owr_rst>.
    Found 1-bit register for signal <owr_dat>.
    Found 1-bit register for signal <owr_cyc>.
    Found 1-bit register for signal <owr_oen>.
    Found 1-bit register for signal <owr_smp>.
    Found 8-bit subtractor for signal <t_bit[7]_GND_299_o_sub_37_OUT> created at line 392.
    Found 8-bit subtractor for signal <cnt[7]_GND_299_o_sub_38_OUT> created at line 393.
    Found 16-bit adder for signal <div[15]_GND_299_o_add_23_OUT> created at line 305.
    Found 1-bit shifter logical left for signal <owr_e> created at line 100
    Found 16-bit comparator equal for signal <pls> created at line 309
    Found 8-bit comparator equal for signal <cnt[7]_t_rstp[7]_equal_43_o> created at line 399
    Found 8-bit comparator equal for signal <cnt[7]_t_bits[7]_equal_44_o> created at line 400
    Found 8-bit comparator equal for signal <cnt[7]_t_rsth[7]_equal_46_o> created at line 409
    Found 8-bit comparator equal for signal <cnt[7]_t_dat1[7]_equal_47_o> created at line 410
    Found 8-bit comparator not equal for signal <cnt[7]_t_dat0[7]_equal_48_o> created at line 411
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  65 D-type flip-flop(s).
	inferred   6 Comparator(s).
	inferred  11 Multiplexer(s).
	inferred   1 Combinational logic shifter(s).
Unit <sockit_owm> synthesized.

Synthesizing Unit <carrier_csr>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/carrier_csr.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 6-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <carrier_csr_ctrl_led_green_int>.
    Found 1-bit register for signal <carrier_csr_ctrl_led_red_int>.
    Found 1-bit register for signal <carrier_csr_ctrl_dac_clr_n_int>.
    Found 1-bit register for signal <carrier_csr_rst_fmc0_n_load_o>.
    Found 32-bit 4-to-1 multiplexer for signal <rwaddr_reg[1]_X_53_o_wide_mux_4_OUT> created at line 106.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <carrier_csr>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <carrier_csr>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<7:7>> (without init value) have a constant value of 0 in block <carrier_csr>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<6:6>> (without init value) have a constant value of 0 in block <carrier_csr>.
    Summary:
	inferred  43 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <carrier_csr> synthesized.

Synthesizing Unit <xwb_vic>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd".
        g_interface_mode = pipelined
        g_address_granularity = byte
        g_num_interrupts = 2
        g_init_vectors = ("00000000000000000011010100000000","00000000000000000001010000000000")
    Summary:
	no macro.
Unit <xwb_vic> synthesized.

Synthesizing Unit <wb_vic>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd".
        g_interface_mode = pipelined
        g_address_granularity = byte
        g_num_interrupts = 2
        g_init_vectors = ("00000000000000000011010100000000","00000000000000000001010000000000")
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <slave_o_dat> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <ma_adr_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <ma_dat_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <ma_sel_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <sl_err_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <sl_rty_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <sl_int_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <slave_o_ack> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <slave_o_err> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <slave_o_rty> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <slave_o_stall> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <slave_o_int> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <ma_cyc_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <ma_stb_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 232: Output port <ma_we_o> of the instance <U_Slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" line 260: Output port <vic_eoir_o> of the instance <U_wb_controller> is unconnected or connected to loadless signal.
    Found 32x32-bit dual-port RAM <Mram_vector_table> for signal <vector_table>.
    Found 32-bit register for signal <vic_ivt_ram_data_int>.
    Found 33-bit register for signal <irqs_i_reg>.
    Found 32-bit register for signal <vic_imr>.
    Found 3-bit register for signal <state>.
    Found 5-bit register for signal <current_irq>.
    Found 1-bit register for signal <irq_master_o>.
    Found 32-bit register for signal <vic_var>.
    Found 32-bit register for signal <swi_mask>.
    Found 16-bit register for signal <timeout_count>.
    Found 32-bit register for signal <vic_ivt_ram_data_towb>.
    Found finite state machine <FSM_8> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | clk_sys_i (rising_edge)                        |
    | Reset              | rst_n_i_INV_585_o (positive)                   |
    | Reset type         | synchronous                                    |
    | Reset State        | wait_irq                                       |
    | Power Up State     | wait_irq                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <timeout_count[15]_GND_332_o_add_20_OUT> created at line 1241.
    Found 16-bit comparator equal for signal <timeout_count[15]_vic_ctl_emu_len[15]_equal_22_o> created at line 384
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred 215 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  20 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <wb_vic> synthesized.

Synthesizing Unit <vic_prio_enc>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd".
    Summary:
	inferred  30 Multiplexer(s).
Unit <vic_prio_enc> synthesized.

Synthesizing Unit <wb_slave_adapter_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = pipelined
        g_master_granularity = word
        g_slave_use_struct = false
        g_slave_mode = pipelined
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <wb_slave_adapter_2> synthesized.

Synthesizing Unit <wb_slave_vic>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 16-bit register for signal <vic_ctl_emu_len_int>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <vic_ctl_enable_int>.
    Found 1-bit register for signal <vic_ctl_pol_int>.
    Found 1-bit register for signal <vic_ctl_emu_edge_int>.
    Found 1-bit register for signal <vic_ier_wr_o>.
    Found 1-bit register for signal <vic_idr_wr_o>.
    Found 1-bit register for signal <vic_swir_wr_o>.
    Found 1-bit register for signal <vic_eoir_wr_o>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <wb_slave_vic>.
    Summary:
	inferred  65 D-type flip-flop(s).
	inferred  11 Multiplexer(s).
Unit <wb_slave_vic> synthesized.

Synthesizing Unit <dma_eic>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/spec/rtl/dma_eic.vhd" line 263: Output port <irq_ack_o> of the instance <eic_irq_controller_inst> is unconnected or connected to loadless signal.
    Found 7-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <eic_idr_write_int>.
    Found 1-bit register for signal <eic_ier_write_int>.
    Found 1-bit register for signal <eic_isr_write_int>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <dma_eic>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <dma_eic>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<7:7>> (without init value) have a constant value of 0 in block <dma_eic>.
    Summary:
	inferred  43 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <dma_eic> synthesized.

Synthesizing Unit <wbgen2_eic>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd".
        g_num_interrupts = 2
        g_irq00_mode = 0
        g_irq01_mode = 0
        g_irq02_mode = 0
        g_irq03_mode = 0
        g_irq04_mode = 0
        g_irq05_mode = 0
        g_irq06_mode = 0
        g_irq07_mode = 0
        g_irq08_mode = 0
        g_irq09_mode = 0
        g_irq0a_mode = 0
        g_irq0b_mode = 0
        g_irq0c_mode = 0
        g_irq0d_mode = 0
        g_irq0e_mode = 0
        g_irq0f_mode = 0
        g_irq10_mode = 0
        g_irq11_mode = 0
        g_irq12_mode = 0
        g_irq13_mode = 0
        g_irq14_mode = 0
        g_irq15_mode = 0
        g_irq16_mode = 0
        g_irq17_mode = 0
        g_irq18_mode = 0
        g_irq19_mode = 0
        g_irq1a_mode = 0
        g_irq1b_mode = 0
        g_irq1c_mode = 0
        g_irq1d_mode = 0
        g_irq1e_mode = 0
        g_irq1f_mode = 0
    Found 2-bit register for signal <irq_i_d1>.
    Found 2-bit register for signal <irq_pending>.
    Found 2-bit register for signal <irq_mask>.
    Found 2-bit register for signal <irq_i_d0>.
    Found 1-bit register for signal <wb_irq_o>.
    Found 2-bit register for signal <irq_i_d2>.
    Summary:
	inferred  11 D-type flip-flop(s).
	inferred  14 Multiplexer(s).
Unit <wbgen2_eic> synthesized.

Synthesizing Unit <fmc_adc_mezzanine>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd".
        g_multishot_ram_size = 2048
        g_carrier_type = "SPEC"
WARNING:Xst:647 - Input <wb_ddr_clk_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" line 303: Output port <slave_o_err> of the instance <cmp_xwb_reg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" line 303: Output port <slave_o_rty> of the instance <cmp_xwb_reg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" line 303: Output port <slave_o_int> of the instance <cmp_xwb_reg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" line 344: Output port <desc_o> of the instance <cmp_fmc_sys_i2c> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" line 377: Output port <desc_o> of the instance <cmp_fmc_spi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" line 421: Output port <desc_o> of the instance <cmp_fmc_i2c> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" line 523: Output port <desc_o> of the instance <cmp_fmc_onewire> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_mezzanine.vhd" line 523: Output port <owr_pwren_o> of the instance <cmp_fmc_onewire> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <ddr_wr_fifo_empty_d>.
    Found 1-bit register for signal <acq_end_extend>.
    Found 4-bit register for signal <spi_din_t>.
    Found 1-bit tristate buffer for signal <sys_scl_b> created at line 366
    Found 1-bit tristate buffer for signal <sys_sda_b> created at line 369
    Found 1-bit tristate buffer for signal <si570_scl_b> created at line 443
    Found 1-bit tristate buffer for signal <si570_sda_b> created at line 446
    Found 1-bit tristate buffer for signal <mezz_one_wire_b> created at line 544
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   5 Tristate(s).
Unit <fmc_adc_mezzanine> synthesized.

Synthesizing Unit <xwb_register_link>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd".
    Register <r_master_stb> equivalent to <r_slave_stall> has been removed
    Found 1-bit register for signal <r_slave_err>.
    Found 1-bit register for signal <r_slave_rty>.
    Found 1-bit register for signal <r_slave_stall>.
    Found 1-bit register for signal <r_slave_int>.
    Found 1-bit register for signal <r_master_cyc>.
    Found 1-bit register for signal <r_master_we>.
    Found 1-bit register for signal <r_slave_ack>.
    Found 32-bit register for signal <r_slave_dat>.
    Found 32-bit register for signal <r_master_adr>.
    Found 4-bit register for signal <r_master_sel>.
    Found 32-bit register for signal <r_master_dat>.
    Summary:
	inferred 107 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <xwb_register_link> synthesized.

Synthesizing Unit <xwb_sdb_crossbar_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd".
        g_num_masters = 1
        g_num_slaves = 7
        g_registered = true
        g_wraparound = true
        g_layout =
("00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000000000000001011000000000000000000000000000000000000000000000000000000000000101100111111100000000000000000000000000000000000000000000000011001110010000100000000000000000000001100000010000000000000000000000000000000001001000000001001000010001000101100101011101000010001011010101010001101001011011010110010101110100011000010110011100101101010000110110111101110010011001010010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000000000000000000000010101000000000000000000000000000000000000000000000000000000000001010100001111000000000000000000000000000000000000000000000000110011100100001000100110111011000110000010000110000000000000000000000000000000010010000000010011000100100000010001010111010000100010110101000110010011010100001100101101010000010100010001000011001011100100010101001001010000110010000000100000001000000010000000100000000
00001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000001010000000000000000000000000000000000000000000000000000000000000101001111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100111101101110011001010101011101101001011100100110010100101101010011010110000101110011011101000110010101110010001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000001001111111111000000000000000000000000000000000000000000000000110011100100001000000000000000000000011000001000000000000000000000000000000000010010000000010010000100010001011001010111010000100010110101000110010011010100001100101101010000010100010001000011001011010100001101101111011100100110010100100000001000000010000000100
00000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000000100101111111100000000000000000000000000000000000000000000000011001110010000100001001000111100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000001000100011111000000000000000000000000000000000000000000000000110011100100001011100101000000111001010001111110000000000000000000000000000000010010000000010010000100010001011001010111010000100010110101010011010100000100100100101110010000110110111101101110011101000111001001101111011011000010000000100000001000000010000
00010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001111111100000000000000000000000000000000000000000000000011001110010000100001001000111100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001")
        g_sdb_addr = "00000000000000000000000000000000"
    Summary:
	no macro.
Unit <xwb_sdb_crossbar_2> synthesized.

Synthesizing Unit <sdb_rom_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd".
        g_layout =
("00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000000000000001011000000000000000000000000000000000000000000000000000000000000101100111111100000000000000000000000000000000000000000000000011001110010000100000000000000000000001100000010000000000000000000000000000000001001000000001001000010001000101100101011101000010001011010101010001101001011011010110010101110100011000010110011100101101010000110110111101110010011001010010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000000000000000000000010101000000000000000000000000000000000000000000000000000000000001010100001111000000000000000000000000000000000000000000000000110011100100001000100110111011000110000010000110000000000000000000000000000000010010000000010011000100100000010001010111010000100010110101000110010011010100001100101101010000010100010001000011001011100100010101001001010000110010000000100000001000000010000000100000000
00001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000001010000000000000000000000000000000000000000000000000000000000000101001111111100000000000000000000000000000000000000000000000011001110010000100111011110011100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100111101101110011001010101011101101001011100100110010100101101010011010110000101110011011101000110010101110010001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000001001111111111000000000000000000000000000000000000000000000000110011100100001000000000000000000000011000001000000000000000000000000000000000010010000000010010000100010001011001010111010000100010110101000110010011010100001100101101010000010100010001000011001011010100001101101111011100100110010100100000001000000010000000100
00000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000000100101111111100000000000000000000000000000000000000000000000011001110010000100001001000111100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000001000100011111000000000000000000000000000000000000000000000000110011100100001011100101000000111001010001111110000000000000000000000000000000010010000000010010000100010001011001010111010000100010110101010011010100000100100100101110010000110110111101101110011101000111001001101111011011000010000000100000001000000010000
00010000000000001","00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001111111100000000000000000000000000000000000000000000000011001110010000100001001000111100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001")
        g_bus_end = "0000000000000000000000000000000000000000000000000001111111111111"
WARNING:Xst:647 - Input <slave_i_adr<31:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_2', is tied to its initial value.
    Found 128x32-bit single-port Read Only RAM <Mram_rom> for signal <rom>.
    Found 1-bit register for signal <slave_o_ack>.
    Found 7-bit register for signal <adr_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   8 D-type flip-flop(s).
Unit <sdb_rom_2> synthesized.

Synthesizing Unit <xwb_crossbar_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd".
        g_num_masters = 1
        g_num_slaves = 8
        g_registered = true
        g_address = ("00000000000000000000000000000000","00000000000000000001011000000000","00000000000000000001010100000000","00000000000000000001010000000000","00000000000000000001001100000000","00000000000000000001001000000000","00000000000000000001000100000000","00000000000000000001000000000000")
        g_mask = ("00000000000000000001111000000000","00000000000000000001111110000000","00000000000000000001111111110000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111100000000","00000000000000000001111111100000","00000000000000000001111100000000")
WARNING:Xst:647 - Input <master_i[7]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[6]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[5]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[4]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[3]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[2]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[1]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[0]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <matrix_old<0>>.
    Found 1-bit register for signal <virtual_ERR>.
    Summary:
	inferred  10 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <xwb_crossbar_2> synthesized.

Synthesizing Unit <xwb_i2c_master>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <slave_o_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <slave_o_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <xwb_i2c_master> synthesized.

Synthesizing Unit <wb_i2c_master>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <master_o_sel> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_i2c_master> synthesized.

Synthesizing Unit <wb_slave_adapter_3>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = word
        g_slave_use_struct = false
        g_slave_mode = classic
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <wb_slave_adapter_3> synthesized.

Synthesizing Unit <i2c_master_top>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd".
        ARST_LVL = '0'
WARNING:Xst:647 - Input <arst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <prer>.
    Found 8-bit register for signal <ctr>.
    Found 8-bit register for signal <txr>.
    Found 8-bit register for signal <cr>.
    Found 1-bit register for signal <al>.
    Found 1-bit register for signal <rxack>.
    Found 1-bit register for signal <tip>.
    Found 1-bit register for signal <irq_flag>.
    Found 1-bit register for signal <wb_inta_o>.
    Found 8-bit register for signal <wb_dat_o>.
    Found 1-bit register for signal <iack_o>.
    Found 8-bit 8-to-1 multiplexer for signal <wb_adr_i[2]_GND_361_o_wide_mux_0_OUT> created at line 191.
    Summary:
	inferred  54 D-type flip-flop(s).
	inferred  16 Multiplexer(s).
Unit <i2c_master_top> synthesized.

Synthesizing Unit <i2c_master_byte_ctrl>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd".
    Found 3-bit register for signal <dcnt>.
    Found 3-bit register for signal <c_state>.
    Found 4-bit register for signal <core_cmd>.
    Found 8-bit register for signal <sr>.
    Found 1-bit register for signal <core_txd>.
    Found 1-bit register for signal <shift>.
    Found 1-bit register for signal <ld>.
    Found 1-bit register for signal <host_ack>.
    Found 1-bit register for signal <ack_out>.
    Found finite state machine <FSM_9> for signal <c_state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 26                                             |
    | Inputs             | 9                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | nReset (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | st_idle                                        |
    | Power Up State     | st_idle                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit subtractor for signal <GND_362_o_GND_362_o_sub_6_OUT<2:0>> created at line 1308.
    Found 4-bit 6-to-1 multiplexer for signal <c_state[2]_X_72_o_wide_mux_38_OUT> created at line 264.
    Found 1-bit 3-to-1 multiplexer for signal <c_state[1]_GND_362_o_Mux_40_o> created at line 264.
    Found 1-bit 3-to-1 multiplexer for signal <c_state[2]_core_ack_Mux_42_o> created at line 264.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  20 D-type flip-flop(s).
	inferred  34 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <i2c_master_byte_ctrl> synthesized.

Synthesizing Unit <i2c_master_bit_ctrl>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd".
    Found 3-bit register for signal <bus_status_ctrl.fSCL>.
    Found 3-bit register for signal <bus_status_ctrl.fSDA>.
    Found 16-bit register for signal <cnt>.
    Found 2-bit register for signal <bus_status_ctrl.cSCL>.
    Found 2-bit register for signal <bus_status_ctrl.cSDA>.
    Found 14-bit register for signal <bus_status_ctrl.filter_cnt>.
    Found 5-bit register for signal <c_state>.
    Found 1-bit register for signal <slave_wait>.
    Found 1-bit register for signal <bus_status_ctrl.sta_condition>.
    Found 1-bit register for signal <bus_status_ctrl.sto_condition>.
    Found 1-bit register for signal <bus_status_ctrl.ibusy>.
    Found 1-bit register for signal <bus_status_ctrl.cmd_stop>.
    Found 1-bit register for signal <ial>.
    Found 1-bit register for signal <dout>.
    Found 1-bit register for signal <cmd_ack>.
    Found 1-bit register for signal <sda_chk>.
    Found 1-bit register for signal <dscl_oen>.
    Found 1-bit register for signal <sSCL>.
    Found 1-bit register for signal <sSDA>.
    Found 1-bit register for signal <dSCL>.
    Found 1-bit register for signal <dSDA>.
    Found 1-bit register for signal <iscl_oen>.
    Found 1-bit register for signal <isda_oen>.
    Found 1-bit register for signal <clk_en>.
    Found finite state machine <FSM_10> for signal <c_state>.
    -----------------------------------------------------------------------
    | States             | 18                                             |
    | Transitions        | 64                                             |
    | Inputs             | 6                                              |
    | Outputs            | 11                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | nReset (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit subtractor for signal <GND_363_o_GND_363_o_sub_2_OUT<15:0>> created at line 1308.
    Found 14-bit subtractor for signal <GND_363_o_GND_363_o_sub_11_OUT<13:0>> created at line 1308.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  57 D-type flip-flop(s).
	inferred  26 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <i2c_master_bit_ctrl> synthesized.

Synthesizing Unit <xwb_spi>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <slave_o_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <xwb_spi> synthesized.

Synthesizing Unit <wb_spi>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 70: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_spi> synthesized.

Synthesizing Unit <wb_slave_adapter_4>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = byte
        g_slave_use_struct = false
        g_slave_mode = classic
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <wb_slave_adapter_4> synthesized.

Synthesizing Unit <spi_top>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v".
        Tp = 1
WARNING:Xst:647 - Input <wb_adr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_sel_i<2:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <divider>.
    Found 8-bit register for signal <ss>.
    Found 32-bit register for signal <wb_dat_o>.
    Found 1-bit register for signal <wb_ack_o>.
    Found 1-bit register for signal <wb_int_o>.
    Found 1-bit register for signal <ctrl<13>>.
    Found 1-bit register for signal <ctrl<12>>.
    Found 1-bit register for signal <ctrl<11>>.
    Found 1-bit register for signal <ctrl<10>>.
    Found 1-bit register for signal <ctrl<9>>.
    Found 1-bit register for signal <ctrl<8>>.
    Found 1-bit register for signal <ctrl<7>>.
    Found 1-bit register for signal <ctrl<6>>.
    Found 1-bit register for signal <ctrl<5>>.
    Found 1-bit register for signal <ctrl<4>>.
    Found 1-bit register for signal <ctrl<3>>.
    Found 1-bit register for signal <ctrl<2>>.
    Found 1-bit register for signal <ctrl<1>>.
    Found 1-bit register for signal <ctrl<0>>.
    Found 32-bit 7-to-1 multiplexer for signal <wb_dat> created at line 115.
    Summary:
	inferred  72 D-type flip-flop(s).
	inferred  18 Multiplexer(s).
Unit <spi_top> synthesized.

Synthesizing Unit <spi_clgen>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v".
        Tp = 1
    Found 16-bit register for signal <cnt>.
    Found 1-bit register for signal <clk_out>.
    Found 1-bit register for signal <pos_edge>.
    Found 1-bit register for signal <neg_edge>.
    Found 16-bit subtractor for signal <cnt[15]_GND_378_o_sub_3_OUT> created at line 80.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  19 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <spi_clgen> synthesized.

Synthesizing Unit <spi_shift>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v".
        Tp = 1
    Found 8-bit register for signal <cnt>.
    Found 1-bit register for signal <tip>.
    Found 1-bit register for signal <s_out>.
    Found 1-bit register for signal <data<127>>.
    Found 1-bit register for signal <data<126>>.
    Found 1-bit register for signal <data<125>>.
    Found 1-bit register for signal <data<124>>.
    Found 1-bit register for signal <data<123>>.
    Found 1-bit register for signal <data<122>>.
    Found 1-bit register for signal <data<121>>.
    Found 1-bit register for signal <data<120>>.
    Found 1-bit register for signal <data<119>>.
    Found 1-bit register for signal <data<118>>.
    Found 1-bit register for signal <data<117>>.
    Found 1-bit register for signal <data<116>>.
    Found 1-bit register for signal <data<115>>.
    Found 1-bit register for signal <data<114>>.
    Found 1-bit register for signal <data<113>>.
    Found 1-bit register for signal <data<112>>.
    Found 1-bit register for signal <data<111>>.
    Found 1-bit register for signal <data<110>>.
    Found 1-bit register for signal <data<109>>.
    Found 1-bit register for signal <data<108>>.
    Found 1-bit register for signal <data<107>>.
    Found 1-bit register for signal <data<106>>.
    Found 1-bit register for signal <data<105>>.
    Found 1-bit register for signal <data<104>>.
    Found 1-bit register for signal <data<103>>.
    Found 1-bit register for signal <data<102>>.
    Found 1-bit register for signal <data<101>>.
    Found 1-bit register for signal <data<100>>.
    Found 1-bit register for signal <data<99>>.
    Found 1-bit register for signal <data<98>>.
    Found 1-bit register for signal <data<97>>.
    Found 1-bit register for signal <data<96>>.
    Found 1-bit register for signal <data<95>>.
    Found 1-bit register for signal <data<94>>.
    Found 1-bit register for signal <data<93>>.
    Found 1-bit register for signal <data<92>>.
    Found 1-bit register for signal <data<91>>.
    Found 1-bit register for signal <data<90>>.
    Found 1-bit register for signal <data<89>>.
    Found 1-bit register for signal <data<88>>.
    Found 1-bit register for signal <data<87>>.
    Found 1-bit register for signal <data<86>>.
    Found 1-bit register for signal <data<85>>.
    Found 1-bit register for signal <data<84>>.
    Found 1-bit register for signal <data<83>>.
    Found 1-bit register for signal <data<82>>.
    Found 1-bit register for signal <data<81>>.
    Found 1-bit register for signal <data<80>>.
    Found 1-bit register for signal <data<79>>.
    Found 1-bit register for signal <data<78>>.
    Found 1-bit register for signal <data<77>>.
    Found 1-bit register for signal <data<76>>.
    Found 1-bit register for signal <data<75>>.
    Found 1-bit register for signal <data<74>>.
    Found 1-bit register for signal <data<73>>.
    Found 1-bit register for signal <data<72>>.
    Found 1-bit register for signal <data<71>>.
    Found 1-bit register for signal <data<70>>.
    Found 1-bit register for signal <data<69>>.
    Found 1-bit register for signal <data<68>>.
    Found 1-bit register for signal <data<67>>.
    Found 1-bit register for signal <data<66>>.
    Found 1-bit register for signal <data<65>>.
    Found 1-bit register for signal <data<64>>.
    Found 1-bit register for signal <data<63>>.
    Found 1-bit register for signal <data<62>>.
    Found 1-bit register for signal <data<61>>.
    Found 1-bit register for signal <data<60>>.
    Found 1-bit register for signal <data<59>>.
    Found 1-bit register for signal <data<58>>.
    Found 1-bit register for signal <data<57>>.
    Found 1-bit register for signal <data<56>>.
    Found 1-bit register for signal <data<55>>.
    Found 1-bit register for signal <data<54>>.
    Found 1-bit register for signal <data<53>>.
    Found 1-bit register for signal <data<52>>.
    Found 1-bit register for signal <data<51>>.
    Found 1-bit register for signal <data<50>>.
    Found 1-bit register for signal <data<49>>.
    Found 1-bit register for signal <data<48>>.
    Found 1-bit register for signal <data<47>>.
    Found 1-bit register for signal <data<46>>.
    Found 1-bit register for signal <data<45>>.
    Found 1-bit register for signal <data<44>>.
    Found 1-bit register for signal <data<43>>.
    Found 1-bit register for signal <data<42>>.
    Found 1-bit register for signal <data<41>>.
    Found 1-bit register for signal <data<40>>.
    Found 1-bit register for signal <data<39>>.
    Found 1-bit register for signal <data<38>>.
    Found 1-bit register for signal <data<37>>.
    Found 1-bit register for signal <data<36>>.
    Found 1-bit register for signal <data<35>>.
    Found 1-bit register for signal <data<34>>.
    Found 1-bit register for signal <data<33>>.
    Found 1-bit register for signal <data<32>>.
    Found 1-bit register for signal <data<31>>.
    Found 1-bit register for signal <data<30>>.
    Found 1-bit register for signal <data<29>>.
    Found 1-bit register for signal <data<28>>.
    Found 1-bit register for signal <data<27>>.
    Found 1-bit register for signal <data<26>>.
    Found 1-bit register for signal <data<25>>.
    Found 1-bit register for signal <data<24>>.
    Found 1-bit register for signal <data<23>>.
    Found 1-bit register for signal <data<22>>.
    Found 1-bit register for signal <data<21>>.
    Found 1-bit register for signal <data<20>>.
    Found 1-bit register for signal <data<19>>.
    Found 1-bit register for signal <data<18>>.
    Found 1-bit register for signal <data<17>>.
    Found 1-bit register for signal <data<16>>.
    Found 1-bit register for signal <data<15>>.
    Found 1-bit register for signal <data<14>>.
    Found 1-bit register for signal <data<13>>.
    Found 1-bit register for signal <data<12>>.
    Found 1-bit register for signal <data<11>>.
    Found 1-bit register for signal <data<10>>.
    Found 1-bit register for signal <data<9>>.
    Found 1-bit register for signal <data<8>>.
    Found 1-bit register for signal <data<7>>.
    Found 1-bit register for signal <data<6>>.
    Found 1-bit register for signal <data<5>>.
    Found 1-bit register for signal <data<4>>.
    Found 1-bit register for signal <data<3>>.
    Found 1-bit register for signal <data<2>>.
    Found 1-bit register for signal <data<1>>.
    Found 1-bit register for signal <data<0>>.
    Found 8-bit subtractor for signal <len[6]_cnt[7]_sub_3_OUT> created at line 82.
    Found 8-bit subtractor for signal <cnt[7]_GND_380_o_sub_4_OUT> created at line 82.
    Found 8-bit subtractor for signal <len[6]_cnt[7]_sub_9_OUT> created at line 83.
    Found 8-bit adder for signal <cnt[7]_GND_380_o_add_6_OUT> created at line 83.
    Found 1-bit 128-to-1 multiplexer for signal <tx_bit_pos[6]_data[127]_Mux_19_o> created at line 122.
    Found 1-bit 128-to-1 multiplexer for signal <rx_bit_pos[6]_data[127]_Mux_20_o> created at line 234.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred 138 D-type flip-flop(s).
	inferred 141 Multiplexer(s).
Unit <spi_shift> synthesized.

Synthesizing Unit <fmc_adc_100Ms_core>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd".
        g_multishot_ram_size = 2048
        g_carrier_type = "SPEC"
WARNING:Xst:647 - Input <wb_ddr_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 718: Output port <fmc_adc_core_sw_trig_o> of the instance <cmp_fmc_adc_100Ms_csr> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 718: Output port <wb_stall_o> of the instance <cmp_fmc_adc_100Ms_csr> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 718: Output port <fmc_adc_core_trig_cfg_reserved_o> of the instance <cmp_fmc_adc_100Ms_csr> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 968: Output port <wr_count_o> of the instance <cmp_adc_sync_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 968: Output port <rd_count_o> of the instance <cmp_adc_sync_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 968: Output port <wr_empty_o> of the instance <cmp_adc_sync_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 968: Output port <wr_almost_empty_o> of the instance <cmp_adc_sync_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 968: Output port <wr_almost_full_o> of the instance <cmp_adc_sync_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 968: Output port <rd_full_o> of the instance <cmp_adc_sync_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 968: Output port <rd_almost_empty_o> of the instance <cmp_adc_sync_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 968: Output port <rd_almost_full_o> of the instance <cmp_adc_sync_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 1383: Output port <qa_o> of the instance <cmp_multishot_dpram0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 1409: Output port <qa_o> of the instance <cmp_multishot_dpram1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 1463: Output port <count_o> of the instance <cmp_wb_ddr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 1463: Output port <almost_empty_o> of the instance <cmp_wb_ddr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" line 1463: Output port <almost_full_o> of the instance <cmp_wb_ddr_fifo> is unconnected or connected to loadless signal.
    Found 16-bit register for signal <shots_cnt>.
    Found 32-bit register for signal <pre_trig_cnt>.
    Found 32-bit register for signal <post_trig_cnt>.
    Found 32-bit register for signal <samples_cnt>.
    Found 32-bit register for signal <trig_addr>.
    Found 32-bit register for signal <wb_ddr_adr_o>.
    Found 3-bit register for signal <acq_fsm_current_state>.
    Found 11-bit register for signal <dpram_addra_cnt>.
    Found 11-bit register for signal <dpram_addra_trig>.
    Found 11-bit register for signal <dpram_addra_post_done>.
    Found 11-bit register for signal <dpram_addrb_cnt>.
    Found 65-bit register for signal <wb_ddr_fifo_din>.
    Found 25-bit register for signal <ram_addr_cnt>.
    Found 64-bit register for signal <wb_ddr_dat_o>.
    Found 8-bit register for signal <bitslip_sreg>.
    Found 1-bit register for signal <serdes_auto_bitslip>.
    Found 1-bit register for signal <serdes_synced>.
    Found 1-bit register for signal <single_shot>.
    Found 1-bit register for signal <acq_in_trig_tag_d>.
    Found 1-bit register for signal <dpram_valid_t>.
    Found 1-bit register for signal <dpram_valid>.
    Found 1-bit register for signal <wb_ddr_fifo_wr_en>.
    Found 1-bit register for signal <wb_ddr_cyc_o>.
    Found 1-bit register for signal <wb_ddr_we_o>.
    Found 1-bit register for signal <wb_ddr_stb_o>.
    Found 1-bit register for signal <wb_ddr_stall_t>.
    Found 1-bit register for signal <int_trig_over_thres>.
    Found 1-bit register for signal <int_trig_over_thres_filt_d>.
    Found 32-bit register for signal <trig_delay_cnt>.
    Found 1-bit register for signal <trig_d>.
    Found 1-bit register for signal <decim_en>.
    Found 1-bit register for signal <trig_align>.
    Found 1-bit register for signal <sync_fifo_valid>.
    Found 64-bit register for signal <data_calibr_out_d<3>>.
    Found 64-bit register for signal <data_calibr_out_d<2>>.
    Found 64-bit register for signal <data_calibr_out_d<1>>.
    Found 64-bit register for signal <data_calibr_out_d<0>>.
    Found 1-bit register for signal <acq_end_d>.
    Found 1-bit register for signal <acq_config_ok>.
    Found 1-bit register for signal <wb_ddr_fifo_valid>.
    Found 32-bit register for signal <fs_freq>.
    Found 1-bit register for signal <decim_cnt<31>>.
    Found 1-bit register for signal <decim_cnt<30>>.
    Found 1-bit register for signal <decim_cnt<29>>.
    Found 1-bit register for signal <decim_cnt<28>>.
    Found 1-bit register for signal <decim_cnt<27>>.
    Found 1-bit register for signal <decim_cnt<26>>.
    Found 1-bit register for signal <decim_cnt<25>>.
    Found 1-bit register for signal <decim_cnt<24>>.
    Found 1-bit register for signal <decim_cnt<23>>.
    Found 1-bit register for signal <decim_cnt<22>>.
    Found 1-bit register for signal <decim_cnt<21>>.
    Found 1-bit register for signal <decim_cnt<20>>.
    Found 1-bit register for signal <decim_cnt<19>>.
    Found 1-bit register for signal <decim_cnt<18>>.
    Found 1-bit register for signal <decim_cnt<17>>.
    Found 1-bit register for signal <decim_cnt<16>>.
    Found 1-bit register for signal <decim_cnt<15>>.
    Found 1-bit register for signal <decim_cnt<14>>.
    Found 1-bit register for signal <decim_cnt<13>>.
    Found 1-bit register for signal <decim_cnt<12>>.
    Found 1-bit register for signal <decim_cnt<11>>.
    Found 1-bit register for signal <decim_cnt<10>>.
    Found 1-bit register for signal <decim_cnt<9>>.
    Found 1-bit register for signal <decim_cnt<8>>.
    Found 1-bit register for signal <decim_cnt<7>>.
    Found 1-bit register for signal <decim_cnt<6>>.
    Found 1-bit register for signal <decim_cnt<5>>.
    Found 1-bit register for signal <decim_cnt<4>>.
    Found 1-bit register for signal <decim_cnt<3>>.
    Found 1-bit register for signal <decim_cnt<2>>.
    Found 1-bit register for signal <decim_cnt<1>>.
    Found 1-bit register for signal <decim_cnt<0>>.
    Found finite state machine <FSM_11> for signal <acq_fsm_current_state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 43                                             |
    | Inputs             | 15                                             |
    | Outputs            | 9                                              |
    | Clock              | sys_clk_i (rising_edge)                        |
    | Reset              | sys_rst_n_i (negative)                         |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <samples_cnt[31]_GND_383_o_add_58_OUT> created at line 1241.
    Found 32-bit adder for signal <n0636> created at line 1182.
    Found 32-bit adder for signal <pre_trig_value[31]_GND_383_o_add_67_OUT> created at line 1241.
    Found 11-bit adder for signal <dpram_addra_cnt[10]_GND_383_o_add_91_OUT> created at line 1241.
    Found 11-bit adder for signal <dpram_addra_post_done[10]_GND_383_o_add_104_OUT> created at line 1241.
    Found 11-bit adder for signal <dpram_addrb_cnt[10]_GND_383_o_add_106_OUT> created at line 1241.
    Found 25-bit adder for signal <ram_addr_cnt[24]_GND_383_o_add_116_OUT> created at line 1241.
    Found 32-bit subtractor for signal <GND_383_o_GND_383_o_sub_18_OUT<31:0>> created at line 1308.
    Found 32-bit subtractor for signal <GND_383_o_GND_383_o_sub_26_OUT<31:0>> created at line 1308.
    Found 32-bit subtractor for signal <GND_383_o_GND_383_o_sub_28_OUT<31:0>> created at line 1308.
    Found 16-bit subtractor for signal <GND_383_o_GND_383_o_sub_38_OUT<15:0>> created at line 1308.
    Found 32-bit subtractor for signal <GND_383_o_GND_383_o_sub_46_OUT<31:0>> created at line 1308.
    Found 32-bit subtractor for signal <GND_383_o_GND_383_o_sub_48_OUT<31:0>> created at line 1308.
    Found 32-bit subtractor for signal <GND_383_o_GND_383_o_sub_53_OUT<31:0>> created at line 1308.
    Found 32-bit subtractor for signal <GND_383_o_GND_383_o_sub_54_OUT<31:0>> created at line 1308.
    Found 11-bit subtractor for signal <GND_383_o_GND_383_o_sub_104_OUT<10:0>> created at line 1444.
    Found 16-bit 4-to-1 multiplexer for signal <int_trig_data> created at line 321.
    Found 16-bit comparator greater for signal <int_trig_data[15]_int_trig_thres[15]_LessThan_16_o> created at line 846
    Found 32-bit comparator greater for signal <GND_383_o_pre_trig_value[31]_LessThan_69_o> created at line 1182
    Found 11-bit comparator equal for signal <dpram_addrb_cnt[10]_dpram_addra_post_done[10]_equal_106_o> created at line 1446
    Summary:
	inferred  12 Adder/Subtractor(s).
	inferred 754 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred 160 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <fmc_adc_100Ms_core> synthesized.

Synthesizing Unit <monostable>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/monostable/monostable_rtl.vhd".
        g_INPUT_POLARITY = '1'
        g_OUTPUT_POLARITY = '1'
        g_OUTPUT_RETRIG = true
        g_OUTPUT_LENGTH = 12500000
    Found 25-bit register for signal <s_monostable_cnt>.
    Found 1-bit register for signal <s_output_pulse>.
    Found 1-bit register for signal <s_trigger_d<0>>.
    Found 25-bit subtractor for signal <GND_384_o_GND_384_o_sub_4_OUT<24:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  27 D-type flip-flop(s).
Unit <monostable> synthesized.

Synthesizing Unit <gc_frequency_meter>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd".
        g_with_internal_timebase = true
        g_clk_sys_freq = 125000000
        g_counter_bits = 32
WARNING:Xst:647 - Input <pps_p1_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <cntr_meas>.
    Found 32-bit register for signal <freq_reg>.
    Found 1-bit register for signal <gate_pulse>.
    Found 32-bit register for signal <cntr_gate>.
    Found 32-bit adder for signal <cntr_gate[31]_GND_385_o_add_1_OUT> created at line 1241.
    Found 32-bit adder for signal <cntr_meas[31]_GND_385_o_add_5_OUT> created at line 1241.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  97 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <gc_frequency_meter> synthesized.

Synthesizing Unit <gc_pulse_synchronizer>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd".
    Found 1-bit register for signal <ready>.
    Found 3-bit register for signal <d_out2in>.
    Found 3-bit register for signal <d_in2out>.
    Found 1-bit register for signal <out_ext>.
    Found 1-bit register for signal <in_ext>.
    Found 1-bit register for signal <d_p_d0>.
    Found 1-bit register for signal <q_p_o>.
    Summary:
	inferred  11 D-type flip-flop(s).
Unit <gc_pulse_synchronizer> synthesized.

Synthesizing Unit <adc_serdes>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/adc_serdes.vhd".
        sys_w = 9
        dev_w = 72
WARNING:Xst:647 - Input <CLK_RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <adc_serdes> synthesized.

Synthesizing Unit <fmc_adc_100Ms_csr>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <rddata_reg>.
    Found 32-bit register for signal <fmc_adc_core_trig_dly_int>.
    Found 32-bit register for signal <fmc_adc_core_sr_deci_int>.
    Found 32-bit register for signal <fmc_adc_core_pre_samples_int>.
    Found 32-bit register for signal <fmc_adc_core_post_samples_int>.
    Found 32-bit register for signal <fmc_adc_core_fs_freq_int>.
    Found 32-bit register for signal <fmc_adc_core_sr_deci_o>.
    Found 2-bit register for signal <fmc_adc_core_trig_cfg_int_trig_sel_int>.
    Found 2-bit register for signal <fmc_adc_core_trig_cfg_int_trig_sel_o>.
    Found 8-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_filt_int>.
    Found 8-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_filt_o>.
    Found 8-bit register for signal <ack_sreg>.
    Found 16-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_int>.
    Found 16-bit register for signal <fmc_adc_core_shots_nb_int>.
    Found 16-bit register for signal <fmc_adc_core_ch1_gain_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch1_offset_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch2_gain_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch2_offset_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch3_gain_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch3_offset_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch4_gain_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch4_offset_val_int>.
    Found 16-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_o>.
    Found 16-bit register for signal <fmc_adc_core_ch1_sta_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch2_sta_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch3_sta_val_int>.
    Found 16-bit register for signal <fmc_adc_core_ch4_sta_val_int>.
    Found 7-bit register for signal <fmc_adc_core_ch1_ctl_ssr_int>.
    Found 7-bit register for signal <fmc_adc_core_ch2_ctl_ssr_int>.
    Found 7-bit register for signal <fmc_adc_core_ch3_ctl_ssr_int>.
    Found 7-bit register for signal <fmc_adc_core_ch4_ctl_ssr_int>.
    Found 15-bit register for signal <fmc_adc_core_ch1_sat_val_int>.
    Found 15-bit register for signal <fmc_adc_core_ch2_sat_val_int>.
    Found 15-bit register for signal <fmc_adc_core_ch3_sat_val_int>.
    Found 15-bit register for signal <fmc_adc_core_ch4_sat_val_int>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <fmc_adc_core_ctl_fsm_cmd_wr_o>.
    Found 1-bit register for signal <fmc_adc_core_ctl_fmc_clk_oe_int>.
    Found 1-bit register for signal <fmc_adc_core_ctl_offset_dac_clr_n_int>.
    Found 1-bit register for signal <fmc_adc_core_ctl_man_bitslip_int>.
    Found 1-bit register for signal <fmc_adc_core_ctl_man_bitslip_int_delay>.
    Found 1-bit register for signal <fmc_adc_core_ctl_test_data_en_int>.
    Found 1-bit register for signal <fmc_adc_core_ctl_trig_led_int>.
    Found 1-bit register for signal <fmc_adc_core_ctl_acq_led_int>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_sel_int>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_pol_int>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_en_int>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_sw_trig_en_int>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_sel_swb>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_sel_swb_delay>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_test_en_int>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_reserved_int>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_swb>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_swb_delay>.
    Found 1-bit register for signal <fmc_adc_core_sw_trig_wr_int>.
    Found 1-bit register for signal <fmc_adc_core_sw_trig_wr_int_delay>.
    Found 1-bit register for signal <fmc_adc_core_fs_freq_lwb>.
    Found 1-bit register for signal <fmc_adc_core_fs_freq_lwb_delay>.
    Found 1-bit register for signal <fmc_adc_core_fs_freq_lwb_in_progress>.
    Found 1-bit register for signal <fmc_adc_core_sr_deci_swb>.
    Found 1-bit register for signal <fmc_adc_core_sr_deci_swb_delay>.
    Found 1-bit register for signal <fmc_adc_core_ch1_sta_val_lwb>.
    Found 1-bit register for signal <fmc_adc_core_ch1_sta_val_lwb_delay>.
    Found 1-bit register for signal <fmc_adc_core_ch1_sta_val_lwb_in_progress>.
    Found 1-bit register for signal <fmc_adc_core_ch2_sta_val_lwb>.
    Found 1-bit register for signal <fmc_adc_core_ch2_sta_val_lwb_delay>.
    Found 1-bit register for signal <fmc_adc_core_ch2_sta_val_lwb_in_progress>.
    Found 1-bit register for signal <fmc_adc_core_ch3_sta_val_lwb>.
    Found 1-bit register for signal <fmc_adc_core_ch3_sta_val_lwb_delay>.
    Found 1-bit register for signal <fmc_adc_core_ch3_sta_val_lwb_in_progress>.
    Found 1-bit register for signal <fmc_adc_core_ch4_sta_val_lwb>.
    Found 1-bit register for signal <fmc_adc_core_ch4_sta_val_lwb_delay>.
    Found 1-bit register for signal <fmc_adc_core_ch4_sta_val_lwb_in_progress>.
    Found 1-bit register for signal <fmc_adc_core_ctl_man_bitslip_o>.
    Found 1-bit register for signal <fmc_adc_core_ctl_man_bitslip_sync0>.
    Found 1-bit register for signal <fmc_adc_core_ctl_man_bitslip_sync1>.
    Found 1-bit register for signal <fmc_adc_core_ctl_man_bitslip_sync2>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_sel_o>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_sel_sync0>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_sel_sync1>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_pol_o>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_pol_sync0>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_pol_sync1>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_en_o>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_en_sync0>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_hw_trig_en_sync1>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_sw_trig_en_o>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_sw_trig_en_sync0>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_sw_trig_en_sync1>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_sel_swb_s0>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_sel_swb_s1>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_sel_swb_s2>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_test_en_o>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_test_en_sync0>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_test_en_sync1>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s0>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s1>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s2>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_swb_s0>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_swb_s1>.
    Found 1-bit register for signal <fmc_adc_core_trig_cfg_int_trig_thres_swb_s2>.
    Found 1-bit register for signal <fmc_adc_core_sw_trig_wr_sync0>.
    Found 1-bit register for signal <fmc_adc_core_sw_trig_wr_sync1>.
    Found 1-bit register for signal <fmc_adc_core_sw_trig_wr_sync2>.
    Found 1-bit register for signal <fmc_adc_core_fs_freq_lwb_s0>.
    Found 1-bit register for signal <fmc_adc_core_fs_freq_lwb_s1>.
    Found 1-bit register for signal <fmc_adc_core_fs_freq_lwb_s2>.
    Found 1-bit register for signal <fmc_adc_core_sr_deci_swb_s0>.
    Found 1-bit register for signal <fmc_adc_core_sr_deci_swb_s1>.
    Found 1-bit register for signal <fmc_adc_core_sr_deci_swb_s2>.
    Found 1-bit register for signal <fmc_adc_core_ch1_sta_val_lwb_s0>.
    Found 1-bit register for signal <fmc_adc_core_ch1_sta_val_lwb_s1>.
    Found 1-bit register for signal <fmc_adc_core_ch1_sta_val_lwb_s2>.
    Found 1-bit register for signal <fmc_adc_core_ch2_sta_val_lwb_s0>.
    Found 1-bit register for signal <fmc_adc_core_ch2_sta_val_lwb_s1>.
    Found 1-bit register for signal <fmc_adc_core_ch2_sta_val_lwb_s2>.
    Found 1-bit register for signal <fmc_adc_core_ch3_sta_val_lwb_s0>.
    Found 1-bit register for signal <fmc_adc_core_ch3_sta_val_lwb_s1>.
    Found 1-bit register for signal <fmc_adc_core_ch3_sta_val_lwb_s2>.
    Found 1-bit register for signal <fmc_adc_core_ch4_sta_val_lwb_s0>.
    Found 1-bit register for signal <fmc_adc_core_ch4_sta_val_lwb_s1>.
    Found 1-bit register for signal <fmc_adc_core_ch4_sta_val_lwb_s2>.
    Found 1-bit register for signal <fmc_adc_core_sw_trig_wr_o>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <fmc_adc_100Ms_csr>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <fmc_adc_100Ms_csr>.
    Summary:
	inferred 670 D-type flip-flop(s).
	inferred 120 Multiplexer(s).
Unit <fmc_adc_100Ms_csr> synthesized.

Synthesizing Unit <offset_gain_s>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/offset_gain_s.vhd".
    Found 18-bit register for signal <gain>.
    Found 17-bit register for signal <product>.
    Found 16-bit register for signal <data_o>.
    Found 18-bit register for signal <data_offset>.
    Found 18-bit adder for signal <data_i[15]_offset_i[15]_add_0_OUT> created at line 120.
    Found 17-bit adder for signal <neg_sat> created at line 165.
    Found 17-bit comparator lessequal for signal <n0011> created at line 172
    Found 17-bit comparator lessequal for signal <n0013> created at line 174
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  69 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <offset_gain_s> synthesized.

Synthesizing Unit <MULT_MACRO>.
    Related source file is "/build/xfndry10/O.76xd/rtf/devlib/vhdl/src/unimacro/MULT_MACRO.vhd".
        DEVICE = "SPARTAN6"
        LATENCY = 0
        STYLE = "DSP"
        WIDTH_A = 18
        WIDTH_B = 18
    Summary:
	no macro.
Unit <MULT_MACRO> synthesized.

Synthesizing Unit <ext_pulse_sync>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd".
        g_MIN_PULSE_WIDTH = 1
        g_CLK_FREQUENCY = 100
        g_OUTPUT_POLARITY = '0'
        g_OUTPUT_RETRIG = false
        g_OUTPUT_LENGTH = 1
    Found 2-bit register for signal <s_pulse_length_cnt>.
    Found 2-bit register for signal <s_monostable_cnt>.
    Found 2-bit register for signal <s_pulse_sync_reg>.
    Found 1-bit register for signal <s_sync_pulse<0>>.
    Found 1-bit register for signal <s_sync_pulse<1>>.
    Found 1-bit register for signal <s_output_pulse>.
    Found 2-bit adder for signal <s_pulse_length_cnt[1]_GND_547_o_add_2_OUT> created at line 1241.
    Found 2-bit subtractor for signal <GND_547_o_GND_547_o_sub_9_OUT<1:0>> created at line 1308.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <ext_pulse_sync> synthesized.

Synthesizing Unit <gc_dyn_glitch_filt>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd".
        g_len_width = 8
    Found 1-bit register for signal <dat_o>.
    Found 8-bit register for signal <filt_cnt>.
    Found 8-bit adder for signal <filt_cnt[7]_GND_548_o_add_4_OUT> created at line 1241.
    Found 8-bit subtractor for signal <GND_548_o_GND_548_o_sub_2_OUT<7:0>> created at line 1308.
    Found 8-bit comparator equal for signal <n0007> created at line 100
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <gc_dyn_glitch_filt> synthesized.

Synthesizing Unit <generic_async_fifo_5>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd".
        g_data_width = 65
        g_size = 16
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = true
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = false
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 0
    Summary:
	no macro.
Unit <generic_async_fifo_5> synthesized.

Synthesizing Unit <inferred_async_fifo_5>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd".
        g_data_width = 65
        g_size = 16
        g_show_ahead = false
        g_with_rd_empty = true
        g_with_rd_full = false
        g_with_rd_almost_empty = false
        g_with_rd_almost_full = false
        g_with_rd_count = false
        g_with_wr_empty = false
        g_with_wr_full = true
        g_with_wr_almost_empty = false
        g_with_wr_almost_full = false
        g_with_wr_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 0
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<4>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_next<3:0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <rcb_gray_xm>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_next>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<4>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_next<3:0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<4>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<3>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<2>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<1>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_bin_x<0>>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_x>.
    Set property "ASYNC_REG = TRUE" for signal <wcb_gray_xm>.
    Found 16x65-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 1-bit register for signal <almost_empty_int>.
    Found 1-bit register for signal <empty_int>.
    Found 5-bit register for signal <wcb_bin>.
    Found 5-bit register for signal <wcb_gray>.
    Found 5-bit register for signal <rcb_bin>.
    Found 5-bit register for signal <rcb_gray>.
    Found 1-bit register for signal <full_int>.
    Found 1-bit register for signal <almost_full_int>.
    Found 5-bit register for signal <rcb_gray_x>.
    Found 5-bit register for signal <rcb_gray_xm>.
    Found 5-bit register for signal <wcb_gray_x>.
    Found 5-bit register for signal <wcb_gray_xm>.
    Found 1-bit register for signal <wr_empty_xm>.
    Found 1-bit register for signal <wr_empty_x>.
    Found 1-bit register for signal <rd_full_xm>.
    Found 1-bit register for signal <rd_full_x>.
    Found 5-bit register for signal <wr_count>.
    Found 1-bit register for signal <almost_full_xm>.
    Found 1-bit register for signal <almost_full_x>.
    Found 5-bit register for signal <rd_count>.
    Found 1-bit register for signal <almost_empty_xm>.
    Found 1-bit register for signal <almost_empty_x>.
    Found 65-bit register for signal <q_o>.
    Found 5-bit adder for signal <wcb_bin_next> created at line 1241.
    Found 5-bit adder for signal <rcb_bin_next> created at line 1241.
    Found 5-bit subtractor for signal <GND_550_o_GND_550_o_sub_25_OUT<4:0>> created at line 272.
    Found 5-bit subtractor for signal <GND_550_o_GND_550_o_sub_28_OUT<4:0>> created at line 297.
    Found 5-bit comparator equal for signal <rcb_gray[4]_wcb_gray_x[4]_equal_21_o> created at line 214
    Found 5-bit comparator equal for signal <wcb_gray_x[4]_rcb_gray_next[4]_equal_22_o> created at line 214
    Found 4-bit comparator equal for signal <wcb_bin[3]_rcb_bin_x[3]_equal_23_o> created at line 235
    Found 4-bit comparator equal for signal <wcb_bin_next[3]_rcb_bin_x[3]_equal_24_o> created at line 239
    Found 5-bit comparator lessequal for signal <n0080> created at line 298
    Summary:
	inferred   1 RAM(s).
	inferred   4 Adder/Subtractor(s).
	inferred 127 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <inferred_async_fifo_5> synthesized.

Synthesizing Unit <generic_dpram_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd".
        g_data_width = 64
        g_size = 2048
        g_with_byte_enable = false
        g_addr_conflict_resolution = "read_first"
        g_init_file = "none"
        g_dual_clock = true
        g_fail_if_file_not_found = true
    Summary:
	no macro.
Unit <generic_dpram_1> synthesized.

Synthesizing Unit <generic_dpram_dualclock>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd".
        g_data_width = 64
        g_size = 2048
        g_with_byte_enable = false
        g_addr_conflict_resolution = "read_first"
        g_init_file = "none"
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <bwea_i<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bweb_i<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2048x64-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 64-bit register for signal <qb_o>.
    Found 64-bit register for signal <qa_o>.
    Summary:
	inferred   1 RAM(s).
	inferred 128 D-type flip-flop(s).
Unit <generic_dpram_dualclock> synthesized.

Synthesizing Unit <generic_dpram_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd".
        g_data_width = 64
        g_size = 2048
        g_with_byte_enable = false
        g_addr_conflict_resolution = "read_first"
        g_init_file = "none"
        g_dual_clock = false
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <clkb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <generic_dpram_2> synthesized.

Synthesizing Unit <generic_dpram_sameclock_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd".
        g_data_width = 64
        g_size = 2048
        g_with_byte_enable = false
        g_addr_conflict_resolution = "read_first"
        g_init_file = "none"
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <bwea_i<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bweb_i<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2048x64-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 64-bit register for signal <qb_o>.
    Found 64-bit register for signal <qa_o>.
    Summary:
	inferred   1 RAM(s).
	inferred 128 D-type flip-flop(s).
Unit <generic_dpram_sameclock_1> synthesized.

Synthesizing Unit <generic_sync_fifo>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd".
        g_data_width = 65
        g_size = 64
        g_show_ahead = false
        g_with_empty = true
        g_with_full = true
        g_with_almost_empty = false
        g_with_almost_full = false
        g_with_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 0
        g_register_flag_outputs = true
    Summary:
	no macro.
Unit <generic_sync_fifo> synthesized.

Synthesizing Unit <inferred_sync_fifo>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd".
        g_data_width = 65
        g_size = 64
        g_show_ahead = false
        g_with_empty = true
        g_with_full = true
        g_with_almost_empty = false
        g_with_almost_full = false
        g_with_count = false
        g_almost_empty_threshold = 0
        g_almost_full_threshold = 0
        g_register_flag_outputs = true
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" line 89: Output port <qa_o> of the instance <U_FIFO_Ram> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <almost_empty_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <almost_full_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 6-bit register for signal <wr_ptr>.
    Found 6-bit register for signal <rd_ptr>.
    Found 1-bit register for signal <full>.
    Found 1-bit register for signal <empty>.
    Found 7-bit register for signal <usedw>.
    Found 6-bit adder for signal <wr_ptr[5]_GND_688_o_add_5_OUT> created at line 1241.
    Found 6-bit adder for signal <rd_ptr[5]_GND_688_o_add_7_OUT> created at line 1241.
    Found 7-bit adder for signal <usedw[6]_GND_688_o_add_16_OUT> created at line 1241.
    Found 6-bit subtractor for signal <GND_688_o_GND_688_o_sub_3_OUT<5:0>> created at line 1308.
    Found 7-bit subtractor for signal <GND_688_o_GND_688_o_sub_18_OUT<6:0>> created at line 1308.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  21 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <inferred_sync_fifo> synthesized.

Synthesizing Unit <generic_dpram_3>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd".
        g_data_width = 65
        g_size = 64
        g_with_byte_enable = false
        g_addr_conflict_resolution = "read_first"
        g_init_file = "none"
        g_dual_clock = false
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <clkb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <generic_dpram_3> synthesized.

Synthesizing Unit <generic_dpram_sameclock_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd".
        g_data_width = 65
        g_size = 64
        g_with_byte_enable = false
        g_addr_conflict_resolution = "read_first"
        g_init_file = "none"
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <bwea_i<8:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bweb_i<8:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 64x65-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 65-bit register for signal <qb_o>.
    Found 65-bit register for signal <qa_o>.
    Summary:
	inferred   1 RAM(s).
	inferred 130 D-type flip-flop(s).
Unit <generic_dpram_sameclock_2> synthesized.

Synthesizing Unit <fmc_adc_eic>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/adc/rtl/fmc_adc_eic.vhd" line 263: Output port <irq_ack_o> of the instance <eic_irq_controller_inst> is unconnected or connected to loadless signal.
    Found 8-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <eic_idr_write_int>.
    Found 1-bit register for signal <eic_ier_write_int>.
    Found 1-bit register for signal <eic_isr_write_int>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <fmc_adc_eic>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <fmc_adc_eic>.
    Summary:
	inferred  44 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <fmc_adc_eic> synthesized.

Synthesizing Unit <timetag_core>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd".
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd" line 152: Output port <wb_stall_o> of the instance <cmp_timetag_core_regs> is unconnected or connected to loadless signal.
    Found 32-bit register for signal <timetag_coarse_cnt>.
    Found 1-bit register for signal <local_pps>.
    Found 32-bit register for signal <trig_tag_seconds>.
    Found 32-bit register for signal <trig_tag_coarse>.
    Found 32-bit register for signal <trig_tag_fine>.
    Found 32-bit register for signal <acq_start_tag_seconds>.
    Found 32-bit register for signal <acq_start_tag_coarse>.
    Found 32-bit register for signal <acq_start_tag_fine>.
    Found 32-bit register for signal <acq_stop_tag_seconds>.
    Found 32-bit register for signal <acq_stop_tag_coarse>.
    Found 32-bit register for signal <acq_stop_tag_fine>.
    Found 32-bit register for signal <acq_end_tag_seconds>.
    Found 32-bit register for signal <acq_end_tag_coarse>.
    Found 32-bit register for signal <acq_end_tag_fine>.
    Found 32-bit register for signal <timetag_seconds_cnt>.
    Found 32-bit adder for signal <timetag_seconds_cnt[31]_GND_761_o_add_0_OUT> created at line 1241.
    Found 32-bit adder for signal <timetag_coarse_cnt[31]_GND_761_o_add_7_OUT> created at line 1241.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 449 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <timetag_core> synthesized.

Synthesizing Unit <timetag_core_regs>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <timetag_core_seconds_load_o>.
    Found 1-bit register for signal <timetag_core_coarse_load_o>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <timetag_core_regs>.
    Summary:
	inferred  44 D-type flip-flop(s).
	inferred  19 Multiplexer(s).
Unit <timetag_core_regs> synthesized.

Synthesizing Unit <ddr3_ctrl>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd".
        g_BANK_PORT_SELECT = "SPEC_BANK3_64B_32B"
        g_MEMCLK_PERIOD = 3000
        g_CALIB_SOFT_IP = "TRUE"
        g_MEM_ADDR_ORDER = "ROW_BANK_COLUMN"
        g_SIMULATION = "FALSE"
        g_NUM_DQ_PINS = 16
        g_MEM_ADDR_WIDTH = 14
        g_MEM_BANKADDR_WIDTH = 3
        g_P0_MASK_SIZE = 8
        g_P0_DATA_PORT_SIZE = 64
        g_P0_BYTE_ADDR_WIDTH = 30
        g_P1_MASK_SIZE = 4
        g_P1_DATA_PORT_SIZE = 32
        g_P1_BYTE_ADDR_WIDTH = 30
WARNING:Xst:653 - Signal <status_o<31:1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <ddr3_ctrl> synthesized.

Synthesizing Unit <ddr3_ctrl_wb_1>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd".
        g_BYTE_ADDR_WIDTH = 30
        g_MASK_SIZE = 8
        g_DATA_PORT_SIZE = 64
WARNING:Xst:647 - Input <ddr_cmd_empty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_wr_empty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_wr_underrun_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_wr_error_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_rd_overflow_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_rd_error_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <rst_n>.
    Found 1-bit register for signal <wb_cyc_d>.
    Found 1-bit register for signal <wb_stb_d>.
    Found 1-bit register for signal <wb_we_d>.
    Found 64-bit register for signal <ddr_wr_data>.
    Found 1-bit register for signal <ddr_wr_en>.
    Found 8-bit register for signal <ddr_wr_mask>.
    Found 30-bit register for signal <ddr_cmd_byte_addr>.
    Found 3-bit register for signal <ddr_cmd_instr>.
    Found 6-bit register for signal <ddr_cmd_bl>.
    Found 27-bit register for signal <wb_addr_d<26:0>>.
    Found 1-bit register for signal <ddr_cmd_en>.
    Found 6-bit register for signal <ddr_burst_cnt>.
    Found 1-bit register for signal <wb_ack_o>.
    Found 64-bit register for signal <wb_data_o>.
    Found 1-bit register for signal <wb_stall_o>.
    Found 6-bit adder for signal <ddr_burst_cnt[5]_GND_764_o_add_21_OUT> created at line 1241.
    Found 6-bit subtractor for signal <GND_764_o_GND_764_o_sub_10_OUT<5:0>> created at line 1308.
    Found 7-bit comparator greater for signal <GND_764_o_ddr_wr_count_i[6]_LessThan_32_o> created at line 333
    Found 7-bit comparator greater for signal <GND_764_o_ddr_rd_count_i[6]_LessThan_33_o> created at line 335
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 216 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <ddr3_ctrl_wb_1> synthesized.

Synthesizing Unit <ddr3_ctrl_wb_2>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd".
        g_BYTE_ADDR_WIDTH = 30
        g_MASK_SIZE = 4
        g_DATA_PORT_SIZE = 32
WARNING:Xst:647 - Input <ddr_cmd_empty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_wr_empty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_wr_underrun_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_wr_error_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_rd_overflow_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr_rd_error_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <rst_n>.
    Found 1-bit register for signal <wb_cyc_d>.
    Found 1-bit register for signal <wb_stb_d>.
    Found 1-bit register for signal <wb_we_d>.
    Found 32-bit register for signal <ddr_wr_data>.
    Found 1-bit register for signal <ddr_wr_en>.
    Found 4-bit register for signal <ddr_wr_mask>.
    Found 30-bit register for signal <ddr_cmd_byte_addr>.
    Found 3-bit register for signal <ddr_cmd_instr>.
    Found 6-bit register for signal <ddr_cmd_bl>.
    Found 28-bit register for signal <wb_addr_d<27:0>>.
    Found 1-bit register for signal <ddr_cmd_en>.
    Found 6-bit register for signal <ddr_burst_cnt>.
    Found 1-bit register for signal <wb_ack_o>.
    Found 32-bit register for signal <wb_data_o>.
    Found 1-bit register for signal <wb_stall_o>.
    Found 6-bit adder for signal <ddr_burst_cnt[5]_GND_765_o_add_21_OUT> created at line 1241.
    Found 6-bit subtractor for signal <GND_765_o_GND_765_o_sub_10_OUT<5:0>> created at line 1308.
    Found 7-bit comparator greater for signal <GND_765_o_ddr_wr_count_i[6]_LessThan_32_o> created at line 333
    Found 7-bit comparator greater for signal <GND_765_o_ddr_rd_count_i[6]_LessThan_33_o> created at line 335
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 149 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <ddr3_ctrl_wb_2> synthesized.

Synthesizing Unit <ddr3_ctrl_wrapper>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd".
        g_BANK_PORT_SELECT = "SPEC_BANK3_64B_32B"
        g_MEMCLK_PERIOD = 3000
        g_CALIB_SOFT_IP = "TRUE"
        g_MEM_ADDR_ORDER = "ROW_BANK_COLUMN"
        g_SIMULATION = "FALSE"
        g_NUM_DQ_PINS = 16
        g_MEM_ADDR_WIDTH = 14
        g_MEM_BANKADDR_WIDTH = 3
        g_P0_MASK_SIZE = 8
        g_P0_DATA_PORT_SIZE = 64
        g_P0_BYTE_ADDR_WIDTH = 30
        g_P1_MASK_SIZE = 4
        g_P1_DATA_PORT_SIZE = 32
        g_P1_BYTE_ADDR_WIDTH = 30
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" line 329: Output port <c3_clk0> of the instance <gen_spec_bank3_64b_32b.cmp_ddr3_ctrl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" line 329: Output port <c3_rst0> of the instance <gen_spec_bank3_64b_32b.cmp_ddr3_ctrl> is unconnected or connected to loadless signal.
    Found 1-bit tristate buffer for signal <ddr3_zio_b> created at line 1005
    Summary:
	inferred   1 Tristate(s).
Unit <ddr3_ctrl_wrapper> synthesized.

Synthesizing Unit <ddr3_ctrl_spec_bank3_64b_32b>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd".
        C3_P0_MASK_SIZE = 8
        C3_P0_DATA_PORT_SIZE = 64
        C3_P1_MASK_SIZE = 4
        C3_P1_DATA_PORT_SIZE = 32
        C3_MEMCLK_PERIOD = 3000
        C3_RST_ACT_LOW = 1
        C3_INPUT_CLK_TYPE = "SINGLE_ENDED"
        C3_CALIB_SOFT_IP = "TRUE"
        C3_SIMULATION = "FALSE"
        DEBUG_EN = 0
        C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN"
        C3_NUM_DQ_PINS = 16
        C3_MEM_ADDR_WIDTH = 14
        C3_MEM_BANKADDR_WIDTH = 3
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" line 511: Output port <selfrefresh_mode> of the instance <memc3_wrapper_inst> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <ddr3_ctrl_spec_bank3_64b_32b> synthesized.

Synthesizing Unit <memc3_infrastructure>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd".
        C_INCLK_PERIOD = 3000
        C_RST_ACT_LOW = 1
        C_INPUT_CLK_TYPE = "SINGLE_ENDED"
        C_CLKOUT0_DIVIDE = 1
        C_CLKOUT1_DIVIDE = 1
        C_CLKOUT2_DIVIDE = 16
        C_CLKOUT3_DIVIDE = 8
        C_CLKFBOUT_MULT = 2
        C_DIVCLK_DIVIDE = 1
    Set property "MAX_FANOUT = 10" for signal <rst0_sync_r>.
    Set property "syn_maxfan = 10" for signal <rst0_sync_r>.
    Set property "KEEP = TRUE" for signal <sys_clk_ibufg>.
WARNING:Xst:647 - Input <sys_clk_p> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sys_clk_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <syn_clk0_powerup_pll_locked>.
    Found 1-bit register for signal <powerup_pll_locked>.
    Found 25-bit register for signal <rst0_sync_r>.
    Summary:
	inferred  27 D-type flip-flop(s).
Unit <memc3_infrastructure> synthesized.

Synthesizing Unit <memc3_wrapper>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd".
        C_MEMCLK_PERIOD = 3000
        C_P0_MASK_SIZE = 8
        C_P0_DATA_PORT_SIZE = 64
        C_P1_MASK_SIZE = 4
        C_P1_DATA_PORT_SIZE = 32
        C_ARB_NUM_TIME_SLOTS = 12
        C_ARB_TIME_SLOT_0 = "000010"
        C_ARB_TIME_SLOT_1 = "010000"
        C_ARB_TIME_SLOT_2 = "000010"
        C_ARB_TIME_SLOT_3 = "010000"
        C_ARB_TIME_SLOT_4 = "000010"
        C_ARB_TIME_SLOT_5 = "010000"
        C_ARB_TIME_SLOT_6 = "000010"
        C_ARB_TIME_SLOT_7 = "010000"
        C_ARB_TIME_SLOT_8 = "000010"
        C_ARB_TIME_SLOT_9 = "010000"
        C_ARB_TIME_SLOT_10 = "000010"
        C_ARB_TIME_SLOT_11 = "010000"
        C_MEM_TRAS = 36000
        C_MEM_TRCD = 13500
        C_MEM_TREFI = 7800000
        C_MEM_TRFC = 160000
        C_MEM_TRP = 13500
        C_MEM_TWR = 15000
        C_MEM_TRTP = 7500
        C_MEM_TWTR = 7500
        C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN"
        C_MEM_TYPE = "DDR3"
        C_MEM_DENSITY = "2Gb"
        C_NUM_DQ_PINS = 16
        C_MEM_BURST_LEN = 8
        C_MEM_CAS_LATENCY = 6
        C_MEM_ADDR_WIDTH = 14
        C_MEM_BANKADDR_WIDTH = 3
        C_MEM_NUM_COL_BITS = 10
        C_MEM_DDR1_2_ODS = "FULL"
        C_MEM_DDR2_RTT = "50OHMS"
        C_MEM_DDR2_DIFF_DQS_EN = "YES"
        C_MEM_DDR2_3_PA_SR = "FULL"
        C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"
        C_MEM_DDR3_CAS_LATENCY = 6
        C_MEM_DDR3_CAS_WR_LATENCY = 5
        C_MEM_DDR3_ODS = "DIV6"
        C_MEM_DDR3_RTT = "DIV4"
        C_MEM_DDR3_AUTO_SR = "ENABLED"
        C_MEM_MOBILE_PA_SR = "FULL"
        C_MEM_MDDR_ODS = "FULL"
        C_MC_CALIB_BYPASS = "NO"
        C_LDQSP_TAP_DELAY_VAL = 0
        C_UDQSP_TAP_DELAY_VAL = 0
        C_LDQSN_TAP_DELAY_VAL = 0
        C_UDQSN_TAP_DELAY_VAL = 0
        C_DQ0_TAP_DELAY_VAL = 0
        C_DQ1_TAP_DELAY_VAL = 0
        C_DQ2_TAP_DELAY_VAL = 0
        C_DQ3_TAP_DELAY_VAL = 0
        C_DQ4_TAP_DELAY_VAL = 0
        C_DQ5_TAP_DELAY_VAL = 0
        C_DQ6_TAP_DELAY_VAL = 0
        C_DQ7_TAP_DELAY_VAL = 0
        C_DQ8_TAP_DELAY_VAL = 0
        C_DQ9_TAP_DELAY_VAL = 0
        C_DQ10_TAP_DELAY_VAL = 0
        C_DQ11_TAP_DELAY_VAL = 0
        C_DQ12_TAP_DELAY_VAL = 0
        C_DQ13_TAP_DELAY_VAL = 0
        C_DQ14_TAP_DELAY_VAL = 0
        C_DQ15_TAP_DELAY_VAL = 0
        C_SKIP_IN_TERM_CAL = 1
        C_SKIP_DYNAMIC_CAL = 0
        C_SIMULATION = "FALSE"
        C_MC_CALIBRATION_MODE = "CALIBRATION"
        C_MC_CALIBRATION_DELAY = "HALF"
        C_CALIB_SOFT_IP = "TRUE"
WARNING:Xst:647 - Input <selfrefresh_enter> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_wr_count> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_rd_data> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_rd_count> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_wr_count> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_rd_data> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_rd_count> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_wr_count> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_rd_data> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_rd_count> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_wr_count> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_rd_data> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_rd_count> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <uo_data> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <status> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_cmd_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_cmd_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_wr_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_wr_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_wr_underrun> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_wr_error> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_rd_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_rd_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_rd_overflow> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p2_rd_error> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_cmd_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_cmd_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_wr_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_wr_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_wr_underrun> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_wr_error> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_rd_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_rd_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_rd_overflow> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p3_rd_error> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_cmd_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_cmd_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_wr_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_wr_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_wr_underrun> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_wr_error> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_rd_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_rd_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_rd_overflow> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p4_rd_error> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_cmd_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_cmd_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_wr_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_wr_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_wr_underrun> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_wr_error> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_rd_full> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_rd_empty> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_rd_overflow> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <p5_rd_error> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <uo_data_valid> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <uo_cmd_ready_in> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <uo_refrsh_flag> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <uo_cal_start> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" line 635: Output port <uo_sdo> of the instance <memc3_mcb_raw_wrapper_inst> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <memc3_wrapper> synthesized.

Synthesizing Unit <mcb_raw_wrapper>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd".
        C_MEMCLK_PERIOD = 3000
        C_PORT_ENABLE = "000011"
        C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN"
        C_ARB_NUM_TIME_SLOTS = 12
        C_ARB_TIME_SLOT_0 = "000000000000000010"
        C_ARB_TIME_SLOT_1 = "000000000000010000"
        C_ARB_TIME_SLOT_2 = "000000000000000010"
        C_ARB_TIME_SLOT_3 = "000000000000010000"
        C_ARB_TIME_SLOT_4 = "000000000000000010"
        C_ARB_TIME_SLOT_5 = "000000000000010000"
        C_ARB_TIME_SLOT_6 = "000000000000000010"
        C_ARB_TIME_SLOT_7 = "000000000000010000"
        C_ARB_TIME_SLOT_8 = "000000000000000010"
        C_ARB_TIME_SLOT_9 = "000000000000010000"
        C_ARB_TIME_SLOT_10 = "000000000000000010"
        C_ARB_TIME_SLOT_11 = "000000000000010000"
        C_PORT_CONFIG = "B64_B32_B32"
        C_MEM_TRAS = 36000
        C_MEM_TRCD = 13500
        C_MEM_TREFI = 7800000
        C_MEM_TRFC = 160000
        C_MEM_TRP = 13500
        C_MEM_TWR = 15000
        C_MEM_TRTP = 7500
        C_MEM_TWTR = 7500
        C_NUM_DQ_PINS = 16
        C_MEM_TYPE = "DDR3"
        C_MEM_DENSITY = "2Gb"
        C_MEM_BURST_LEN = 8
        C_MEM_CAS_LATENCY = 6
        C_MEM_ADDR_WIDTH = 14
        C_MEM_BANKADDR_WIDTH = 3
        C_MEM_NUM_COL_BITS = 10
        C_MEM_DDR3_CAS_LATENCY = 6
        C_MEM_MOBILE_PA_SR = "FULL"
        C_MEM_DDR1_2_ODS = "FULL"
        C_MEM_DDR3_ODS = "DIV6"
        C_MEM_DDR2_RTT = "50OHMS"
        C_MEM_DDR3_RTT = "DIV4"
        C_MEM_MDDR_ODS = "FULL"
        C_MEM_DDR2_DIFF_DQS_EN = "YES"
        C_MEM_DDR2_3_PA_SR = "FULL"
        C_MEM_DDR3_CAS_WR_LATENCY = 5
        C_MEM_DDR3_AUTO_SR = "ENABLED"
        C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"
        C_MEM_DDR3_DYN_WRT_ODT = "OFF"
        C_MEM_TZQINIT_MAXCNT = "1000010000"
        C_MC_CALIB_BYPASS = "NO"
        C_MC_CALIBRATION_RA = "0000000000000000"
        C_MC_CALIBRATION_BA = "000"
        C_CALIB_SOFT_IP = "TRUE"
        C_SKIP_IN_TERM_CAL = 1
        C_SKIP_DYNAMIC_CAL = 0
        C_SKIP_DYN_IN_TERM = 1
        C_SIMULATION = "FALSE"
        LDQSP_TAP_DELAY_VAL = 0
        UDQSP_TAP_DELAY_VAL = 0
        LDQSN_TAP_DELAY_VAL = 0
        UDQSN_TAP_DELAY_VAL = 0
        DQ0_TAP_DELAY_VAL = 0
        DQ1_TAP_DELAY_VAL = 0
        DQ2_TAP_DELAY_VAL = 0
        DQ3_TAP_DELAY_VAL = 0
        DQ4_TAP_DELAY_VAL = 0
        DQ5_TAP_DELAY_VAL = 0
        DQ6_TAP_DELAY_VAL = 0
        DQ7_TAP_DELAY_VAL = 0
        DQ8_TAP_DELAY_VAL = 0
        DQ9_TAP_DELAY_VAL = 0
        DQ10_TAP_DELAY_VAL = 0
        DQ11_TAP_DELAY_VAL = 0
        DQ12_TAP_DELAY_VAL = 0
        DQ13_TAP_DELAY_VAL = 0
        DQ14_TAP_DELAY_VAL = 0
        DQ15_TAP_DELAY_VAL = 0
        C_MC_CALIBRATION_CA = "000000000000"
        C_MC_CALIBRATION_CLK_DIV = 1
        C_MC_CALIBRATION_MODE = "CALIBRATION"
        C_MC_CALIBRATION_DELAY = "HALF"
        C_P0_MASK_SIZE = 8
        C_P0_DATA_PORT_SIZE = 64
        C_P1_MASK_SIZE = 4
        C_P1_DATA_PORT_SIZE = 32
    Set property "MAX_FANOUT = 1" for signal <int_sys_rst>.
    Set property "syn_maxfan = 1" for signal <int_sys_rst>.
WARNING:Xst:647 - Input <p0_cmd_byte_addr<29:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p0_cmd_byte_addr<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p1_cmd_byte_addr<29:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p1_cmd_byte_addr<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_cmd_instr<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_cmd_bl<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_cmd_byte_addr<29:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_wr_mask<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_wr_data<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_cmd_instr<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_cmd_bl<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_cmd_byte_addr<29:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_wr_mask<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_wr_data<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_cmd_instr<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_cmd_bl<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_cmd_byte_addr<29:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_wr_mask<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_wr_data<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_cmd_instr<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_cmd_bl<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_cmd_byte_addr<29:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_wr_mask<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_wr_data<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_addr<4:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_dqcount<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_arb_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_cmd_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_cmd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_wr_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_rd_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_arb_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_cmd_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_cmd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_wr_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_rd_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p3_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_arb_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_cmd_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_cmd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_wr_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_rd_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p4_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_arb_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_cmd_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_cmd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_wr_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_rd_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p5_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <calib_recal> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_read> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_add> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_cs> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_sdi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_broadcast> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_drp_update> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_done_cal> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_cmd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_cmd_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_cmd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_dq_lower_dec> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_dq_lower_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_dq_upper_dec> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_dq_upper_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_udqs_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_udqs_dec> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_ldqs_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui_ldqs_dec> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <p3_wr_count> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_rd_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_rd_count> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_wr_count> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_rd_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_rd_count> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_wr_count> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_rd_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_rd_count> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mig_p2_wr_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mig_p4_wr_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mig_p2_wr_mask> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mig_p4_wr_mask> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_cmd_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_cmd_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_wr_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_wr_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_wr_underrun> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_wr_error> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_rd_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_rd_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_rd_overflow> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p3_rd_error> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_cmd_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_cmd_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_wr_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_wr_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_wr_underrun> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_wr_error> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_rd_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_rd_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_rd_overflow> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p4_rd_error> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_cmd_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_cmd_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_wr_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_wr_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_wr_underrun> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_wr_error> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_rd_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_rd_empty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_rd_overflow> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p5_rd_error> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <normal_operation_window>.
    Found 1-bit register for signal <soft_cal_selfrefresh_req>.
    Found 1-bit register for signal <syn_uiclk_pll_lock>.
    WARNING:Xst:2404 -  FFs/Latches <selfrefresh_enter_r1<0:0>> (without init value) have a constant value of 0 in block <mcb_raw_wrapper>.
    WARNING:Xst:2404 -  FFs/Latches <selfrefresh_enter_r2<0:0>> (without init value) have a constant value of 0 in block <mcb_raw_wrapper>.
    WARNING:Xst:2404 -  FFs/Latches <selfrefresh_enter_r3<0:0>> (without init value) have a constant value of 0 in block <mcb_raw_wrapper>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <mcb_raw_wrapper> synthesized.

Synthesizing Unit <mcb_soft_calibration_top>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd".
        C_MEM_TZQINIT_MAXCNT = "1000010000"
        C_MC_CALIBRATION_MODE = "CALIBRATION"
        SKIP_IN_TERM_CAL = 1
        SKIP_DYNAMIC_CAL = 0
        SKIP_DYN_IN_TERM = 1
        C_SIMULATION = "FALSE"
        C_MEM_TYPE = "DDR3"
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" line 291: Output port <Max_Value> of the instance <mcb_soft_calibration_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" line 291: Output port <ZIO_IODRP_CS> of the instance <mcb_soft_calibration_inst> is unconnected or connected to loadless signal.
WARNING:Xst:2563 - Inout <ZIO_PIN> is never assigned. Tied to value Z.
WARNING:Xst:653 - Signal <ZIO_IODRP_SDO> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ZIO_IN> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <RZQ_IN_R1>.
    Found 1-bit register for signal <RZQ_IN_R2>.
    Found 1-bit tristate buffer for signal <ZIO_PIN> created at line 141
    WARNING:Xst:2404 -  FFs/Latches <ZIO_IN_R1<0:0>> (without init value) have a constant value of 0 in block <mcb_soft_calibration_top>.
    WARNING:Xst:2404 -  FFs/Latches <ZIO_IN_R2<0:0>> (without init value) have a constant value of 0 in block <mcb_soft_calibration_top>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <mcb_soft_calibration_top> synthesized.

Synthesizing Unit <mcb_soft_calibration>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd".
        C_MEM_TZQINIT_MAXCNT = "1000010000"
        SKIP_IN_TERM_CAL = 1
        SKIP_DYNAMIC_CAL = 0
        SKIP_DYN_IN_TERM = 1
        C_MC_CALIBRATION_MODE = "CALIBRATION"
        C_SIMULATION = "FALSE"
        C_MEM_TYPE = "DDR3"
    Set property "syn_preserve = true" for signal <P_Term>.
    Set property "syn_preserve = true" for signal <N_Term>.
    Set property "syn_preserve = true" for signal <P_Term_s>.
    Set property "syn_preserve = true" for signal <N_Term_s>.
    Set property "syn_preserve = true" for signal <P_Term_w>.
    Set property "syn_preserve = true" for signal <N_Term_w>.
    Set property "syn_preserve = true" for signal <P_Term_Prev>.
    Set property "syn_preserve = true" for signal <N_Term_Prev>.
    Set property "syn_preserve = true" for signal <IODRPCTRLR_MEMCELL_ADDR>.
    Set property "syn_preserve = true" for signal <IODRPCTRLR_WRITE_DATA>.
    Set property "syn_preserve = true" for signal <Max_Value_Previous>.
    Set property "syn_preserve = true" for signal <DQS_DELAY_INITIAL>.
    Set property "IOB = FALSE" for signal <DONE_SOFTANDHARD_CAL>.
WARNING:Xst:647 - Input <MCB_UODATA<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MCB_UODATAVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MCB_UOCMDREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MCB_UO_CAL_START> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" line 558: Output port <DRP_BKST> of the instance <iodrp_controller_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" line 576: Output port <read_data> of the instance <iodrp_mcb_controller_inst> is unconnected or connected to loadless signal.
    Register <MCB_UIUDQSINC> equivalent to <MCB_UILDQSINC> has been removed
    Register <MCB_UIUDQSDEC> equivalent to <MCB_UILDQSDEC> has been removed
    Found 1-bit register for signal <Block_Reset>.
    Found 1-bit register for signal <SELFREFRESH_MCB_MODE_R1>.
    Found 1-bit register for signal <SELFREFRESH_MCB_MODE_R2>.
    Found 1-bit register for signal <SELFREFRESH_MCB_MODE_R3>.
    Found 1-bit register for signal <SELFREFRESH_REQ_R1>.
    Found 1-bit register for signal <SELFREFRESH_REQ_R2>.
    Found 1-bit register for signal <SELFREFRESH_REQ_R3>.
    Found 1-bit register for signal <PLL_LOCK_R1>.
    Found 1-bit register for signal <PLL_LOCK_R2>.
    Found 16-bit register for signal <WAIT_200us_COUNTER>.
    Found 10-bit register for signal <RstCounter>.
    Found 1-bit register for signal <Rst_condition1>.
    Found 1-bit register for signal <SELFREFRESH_MCB_REQ>.
    Found 1-bit register for signal <WAIT_SELFREFRESH_EXIT_DQS_CAL>.
    Found 1-bit register for signal <PERFORM_START_DYN_CAL_AFTER_SELFREFRESH>.
    Found 1-bit register for signal <START_DYN_CAL_STATE_R1>.
    Found 1-bit register for signal <PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1>.
    Found 1-bit register for signal <SELFREFRESH_MODE_xilinx11>.
    Found 1-bit register for signal <WaitCountEnable>.
    Found 8-bit register for signal <WaitTimer>.
    Found 1-bit register for signal <WarmEnough>.
    Found 6-bit register for signal <count>.
    Found 1-bit register for signal <MCB_CMD_VALID>.
    Found 5-bit register for signal <MCB_UIADDR_int>.
    Found 1-bit register for signal <MCB_UICMDEN>.
    Found 1-bit register for signal <MCB_UIDONECAL_xilinx7>.
    Found 1-bit register for signal <MCB_USE_BKST>.
    Found 1-bit register for signal <MCB_UIDRPUPDATE>.
    Found 1-bit register for signal <Pre_SYSRST>.
    Found 1-bit register for signal <IODRPCTRLR_CMD_VALID>.
    Found 8-bit register for signal <IODRPCTRLR_MEMCELL_ADDR>.
    Found 8-bit register for signal <IODRPCTRLR_WRITE_DATA>.
    Found 1-bit register for signal <IODRPCTRLR_R_WB>.
    Found 6-bit register for signal <P_Term>.
    Found 7-bit register for signal <N_Term>.
    Found 6-bit register for signal <P_Term_s>.
    Found 7-bit register for signal <N_Term_w>.
    Found 6-bit register for signal <P_Term_w>.
    Found 7-bit register for signal <N_Term_s>.
    Found 6-bit register for signal <P_Term_Prev>.
    Found 7-bit register for signal <N_Term_Prev>.
    Found 2-bit register for signal <Active_IODRP>.
    Found 1-bit register for signal <MCB_UILDQSINC>.
    Found 1-bit register for signal <MCB_UILDQSDEC>.
    Found 1-bit register for signal <counter_en>.
    Found 1-bit register for signal <First_Dyn_Cal_Done>.
    Found 8-bit register for signal <Max_Value_int>.
    Found 8-bit register for signal <Max_Value_Previous>.
    Found 6-bit register for signal <STATE>.
    Found 8-bit register for signal <DQS_DELAY>.
    Found 8-bit register for signal <DQS_DELAY_INITIAL>.
    Found 8-bit register for signal <TARGET_DQS_DELAY>.
    Found 1-bit register for signal <First_In_Term_Done>.
    Found 1-bit register for signal <MCB_UICMD>.
    Found 4-bit register for signal <MCB_UIDQCOUNT>.
    Found 8-bit register for signal <counter_inc>.
    Found 8-bit register for signal <counter_dec>.
    Found 1-bit register for signal <DONE_SOFTANDHARD_CAL>.
    Found 1-bit register for signal <RST_reg>.
INFO:Xst:1799 - State 000010 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 000001 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 000011 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 000100 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 000101 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 000110 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 000111 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 001000 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 001001 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 001010 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 001011 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 001100 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 001101 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 100010 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 010000 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 001110 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 001111 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 010001 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 010010 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 010011 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 010100 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 010101 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 010110 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 010111 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 011000 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 011001 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 011010 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 011011 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 011100 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 011101 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 011110 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 011111 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 100000 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 100001 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 100011 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 100100 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 100101 is never reached in FSM <STATE>.
INFO:Xst:1799 - State 111010 is never reached in FSM <STATE>.
    Found finite state machine <FSM_12> for signal <STATE>.
    -----------------------------------------------------------------------
    | States             | 59                                             |
    | Transitions        | 56                                             |
    | Inputs             | 22                                             |
    | Outputs            | 25                                             |
    | Clock              | UI_CLK (rising_edge)                           |
    | Reset              | RST_reg (positive)                             |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <WAIT_200us_COUNTER[15]_GND_800_o_add_13_OUT> created at line 607.
    Found 10-bit adder for signal <RstCounter[9]_GND_800_o_add_17_OUT> created at line 669.
    Found 8-bit adder for signal <WaitTimer[7]_GND_800_o_add_29_OUT> created at line 895.
    Found 6-bit adder for signal <count[5]_GND_800_o_add_37_OUT> created at line 917.
    Found 6-bit adder for signal <P_Term[5]_GND_800_o_add_50_OUT> created at line 1090.
    Found 7-bit adder for signal <N_Term[6]_GND_800_o_add_81_OUT> created at line 1143.
    Found 8-bit adder for signal <counter_inc[7]_GND_800_o_add_326_OUT> created at line 1655.
    Found 8-bit adder for signal <DQS_DELAY[7]_GND_800_o_add_329_OUT> created at line 1661.
    Found 8-bit adder for signal <counter_dec[7]_GND_800_o_add_339_OUT> created at line 1680.
    Found 8-bit subtractor for signal <Max_Value_Delta_Up> created at line 414.
    Found 8-bit subtractor for signal <Max_Value_Delta_Dn> created at line 416.
    Found 6-bit subtractor for signal <GND_800_o_GND_800_o_sub_68_OUT<5:0>> created at line 1095.
    Found 7-bit subtractor for signal <GND_800_o_GND_800_o_sub_175_OUT<6:0>> created at line 1153.
    Found 8-bit subtractor for signal <GND_800_o_GND_800_o_sub_343_OUT<7:0>> created at line 1686.
    Found 15-bit adder for signal <_n0863> created at line 478.
    Found 15-bit adder for signal <n0736> created at line 478.
    Found 15-bit adder for signal <n0487> created at line 478.
    Found 15-bit adder for signal <_n0872> created at line 478.
    Found 15-bit adder for signal <n0468> created at line 478.
    Found 15-bit adder for signal <n0538> created at line 478.
    Found 15-bit adder for signal <_n0881> created at line 478.
    Found 15-bit adder for signal <n0476[14:0]> created at line 478.
    Found 15-bit adder for signal <n0478> created at line 478.
    Found 10-bit comparator greater for signal <RstCounter[9]_PWR_353_o_LessThan_17_o> created at line 667
    Found 8-bit comparator greater for signal <Dec_Flag> created at line 905
    Found 8-bit comparator greater for signal <Inc_Flag> created at line 906
    Found 6-bit comparator equal for signal <n0161> created at line 1161
    Found 7-bit comparator equal for signal <n0170> created at line 1193
    Found 6-bit comparator greater for signal <count[5]_PWR_353_o_LessThan_302_o> created at line 1598
    Found 8-bit comparator greater for signal <Max_Value_int[7]_Max_Value_Previous[7]_LessThan_308_o> created at line 1631
    Found 8-bit comparator greater for signal <n0250> created at line 1631
    Found 8-bit comparator greater for signal <Max_Value_Previous[7]_Max_Value_int[7]_LessThan_313_o> created at line 1635
    Found 8-bit comparator greater for signal <n0254> created at line 1635
    Found 8-bit comparator greater for signal <DQS_DELAY[7]_DQS_DELAY_UPPER_LIMIT[7]_LessThan_328_o> created at line 1657
    Found 8-bit comparator lessequal for signal <n0268> created at line 1657
    Found 8-bit comparator greater for signal <DQS_DELAY_LOWER_LIMIT[7]_DQS_DELAY[7]_LessThan_341_o> created at line 1682
    Found 8-bit comparator lessequal for signal <n0282> created at line 1682
    WARNING:Xst:2404 -  FFs/Latches <CKE_Train<0:0>> (without init value) have a constant value of 0 in block <mcb_soft_calibration>.
    WARNING:Xst:2404 -  FFs/Latches <MCB_UICMDIN<0:0>> (without init value) have a constant value of 0 in block <mcb_soft_calibration>.
    Summary:
	inferred  22 Adder/Subtractor(s).
	inferred 208 D-type flip-flop(s).
	inferred  14 Comparator(s).
	inferred  43 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mcb_soft_calibration> synthesized.

Synthesizing Unit <iodrp_controller>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd".
    Found 8-bit register for signal <data_reg>.
    Found 1-bit register for signal <rd_not_write_reg>.
    Found 8-bit register for signal <shift_through_reg>.
    Found 3-bit register for signal <bit_cnt>.
    Found 8-bit register for signal <read_data>.
    Found 1-bit register for signal <AddressPhase>.
    Found 1-bit register for signal <DRP_ADD>.
    Found 1-bit register for signal <DRP_CS>.
    Found 1-bit register for signal <DRP_BKST>.
    Found 3-bit register for signal <state>.
    Found 8-bit register for signal <memcell_addr_reg>.
    Found finite state machine <FSM_13> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 4                                              |
    | Outputs            | 8                                              |
    | Clock              | DRP_CLK (rising_edge)                          |
    | Reset              | sync_rst (positive)                            |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <bit_cnt[2]_GND_801_o_add_12_OUT> created at line 238.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  40 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <iodrp_controller> synthesized.

Synthesizing Unit <iodrp_mcb_controller>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd".
    Set property "fsm_encoding = gray" for signal <state>.
    Set property "fsm_encoding = gray" for signal <nextstate>.
WARNING:Xst:647 - Input <drp_ioi_addr<4:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 8-bit register for signal <data_reg>.
    Found 1-bit register for signal <rd_not_write_reg>.
    Found 8-bit register for signal <shift_through_reg<7:0>>.
    Found 3-bit register for signal <bit_cnt>.
    Found 8-bit register for signal <read_data>.
    Found 1-bit register for signal <AddressPhase>.
    Found 1-bit register for signal <DRP_ADD_xilinx0>.
    Found 1-bit register for signal <DRP_CS_xilinx1>.
    Found 1-bit register for signal <MCB_UIREAD>.
    Found 1-bit register for signal <DRP_BKST>.
    Found 4-bit register for signal <state>.
    Found 8-bit register for signal <memcell_addr_reg>.
    Found finite state machine <FSM_14> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 15                                             |
    | Inputs             | 4                                              |
    | Outputs            | 9                                              |
    | Clock              | DRP_CLK (rising_edge)                          |
    | Reset              | sync_rst (positive)                            |
    | Reset type         | synchronous                                    |
    | Reset State        | ready                                          |
    | Power Up State     | ready                                          |
    | Encoding           | gray                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <bit_cnt[2]_GND_803_o_add_13_OUT> created at line 372.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  41 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <iodrp_mcb_controller> synthesized.

Synthesizing Unit <gc_extend_pulse>.
    Related source file is "/home/mcattin/projects/fmc-adc/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd".
        g_width = 5000000
    Found 23-bit register for signal <cntr>.
    Found 1-bit register for signal <extended_int>.
    Found 23-bit subtractor for signal <GND_1732_o_GND_1732_o_sub_2_OUT<22:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  24 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <gc_extend_pulse> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 12
 128x32-bit dual-port RAM                              : 1
 128x32-bit single-port Read Only RAM                  : 1
 128x64-bit dual-port RAM                              : 1
 16x65-bit dual-port RAM                               : 1
 2048x64-bit dual-port RAM                             : 2
 256x32-bit single-port Read Only RAM                  : 1
 32x32-bit dual-port RAM                               : 1
 512x32-bit dual-port RAM                              : 2
 512x64-bit dual-port RAM                              : 1
 64x65-bit dual-port RAM                               : 1
# Adders/Subtractors                                   : 131
 10-bit adder                                          : 8
 10-bit subtractor                                     : 6
 11-bit adder                                          : 2
 11-bit addsub                                         : 1
 11-bit subtractor                                     : 2
 12-bit adder                                          : 1
 14-bit subtractor                                     : 2
 15-bit adder                                          : 9
 16-bit adder                                          : 4
 16-bit subtractor                                     : 4
 17-bit adder                                          : 5
 17-bit addsub                                         : 1
 18-bit adder                                          : 4
 2-bit adder                                           : 1
 2-bit subtractor                                      : 1
 23-bit subtractor                                     : 3
 25-bit adder                                          : 1
 25-bit subtractor                                     : 2
 3-bit adder                                           : 3
 3-bit subtractor                                      : 2
 30-bit adder                                          : 3
 30-bit subtractor                                     : 3
 32-bit adder                                          : 12
 32-bit subtractor                                     : 6
 5-bit adder                                           : 2
 5-bit addsub                                          : 2
 5-bit subtractor                                      : 2
 6-bit adder                                           : 6
 6-bit subtractor                                      : 4
 7-bit adder                                           : 1
 7-bit addsub                                          : 1
 7-bit subtractor                                      : 2
 8-bit adder                                           : 9
 8-bit addsub                                          : 2
 8-bit subtractor                                      : 11
 9-bit adder                                           : 3
# Registers                                            : 1240
 1-bit register                                        : 816
 10-bit register                                       : 35
 11-bit register                                       : 6
 12-bit register                                       : 1
 14-bit register                                       : 2
 15-bit register                                       : 4
 16-bit register                                       : 37
 17-bit register                                       : 6
 18-bit register                                       : 8
 2-bit register                                        : 29
 23-bit register                                       : 3
 25-bit register                                       : 4
 27-bit register                                       : 1
 28-bit register                                       : 1
 3-bit register                                        : 19
 30-bit register                                       : 7
 31-bit register                                       : 1
 32-bit register                                       : 122
 33-bit register                                       : 1
 4-bit register                                        : 12
 5-bit register                                        : 14
 6-bit register                                        : 12
 64-bit register                                       : 14
 65-bit register                                       : 4
 7-bit register                                        : 12
 8-bit register                                        : 62
 9-bit register                                        : 7
# Comparators                                          : 84
 10-bit comparator equal                               : 6
 10-bit comparator greater                             : 1
 10-bit comparator lessequal                           : 6
 11-bit comparator equal                               : 1
 11-bit comparator greater                             : 3
 16-bit comparator equal                               : 3
 16-bit comparator greater                             : 1
 17-bit comparator equal                               : 1
 17-bit comparator lessequal                           : 8
 30-bit comparator greater                             : 2
 32-bit comparator equal                               : 2
 32-bit comparator greater                             : 1
 4-bit comparator equal                                : 2
 5-bit comparator equal                                : 2
 5-bit comparator lessequal                            : 1
 6-bit comparator equal                                : 1
 6-bit comparator greater                              : 1
 7-bit comparator equal                                : 5
 7-bit comparator greater                              : 4
 8-bit comparator equal                                : 13
 8-bit comparator greater                              : 8
 8-bit comparator lessequal                            : 4
 8-bit comparator not equal                            : 2
 9-bit comparator equal                                : 6
# Multiplexers                                         : 1051
 1-bit 128-to-1 multiplexer                            : 2
 1-bit 2-to-1 multiplexer                              : 699
 1-bit 3-to-1 multiplexer                              : 4
 10-bit 2-to-1 multiplexer                             : 5
 11-bit 2-to-1 multiplexer                             : 15
 12-bit 2-to-1 multiplexer                             : 1
 14-bit 2-to-1 multiplexer                             : 4
 16-bit 2-to-1 multiplexer                             : 23
 16-bit 4-to-1 multiplexer                             : 1
 2-bit 2-to-1 multiplexer                              : 10
 23-bit 2-to-1 multiplexer                             : 3
 25-bit 2-to-1 multiplexer                             : 1
 3-bit 2-to-1 multiplexer                              : 8
 30-bit 2-to-1 multiplexer                             : 9
 32-bit 2-to-1 multiplexer                             : 121
 32-bit 3-to-1 multiplexer                             : 1
 32-bit 4-to-1 multiplexer                             : 1
 32-bit 7-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 22
 4-bit 6-to-1 multiplexer                              : 2
 5-bit 2-to-1 multiplexer                              : 37
 6-bit 2-to-1 multiplexer                              : 9
 64-bit 2-to-1 multiplexer                             : 4
 65-bit 2-to-1 multiplexer                             : 3
 7-bit 2-to-1 multiplexer                              : 4
 8-bit 2-to-1 multiplexer                              : 53
 8-bit 8-to-1 multiplexer                              : 2
 9-bit 2-to-1 multiplexer                              : 6
# Logic shifters                                       : 2
 1-bit shifter logical left                            : 2
# Tristates                                            : 8
 1-bit tristate buffer                                 : 8
# FSMs                                                 : 18
# Xors                                                 : 135
 1-bit xor2                                            : 84
 1-bit xor3                                            : 24
 32-bit xor2                                           : 15
 4-bit xor2                                            : 2
 7-bit xor2                                            : 4
 9-bit xor2                                            : 6

=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:2261 - The FF/Latch <rcb_bin_7> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <rcb_gray_7> 
INFO:Xst:2261 - The FF/Latch <wcb_bin_7> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <wcb_gray_7> 
INFO:Xst:2261 - The FF/Latch <rcb_bin_7> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <rcb_gray_7> 
INFO:Xst:2261 - The FF/Latch <wcb_bin_7> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <wcb_gray_7> 
INFO:Xst:2261 - The FF/Latch <rcb_bin_9> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <rcb_gray_9> 
INFO:Xst:2261 - The FF/Latch <wcb_bin_9> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <wcb_gray_9> 
INFO:Xst:2261 - The FF/Latch <rcb_bin_9> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <rcb_gray_9> 
INFO:Xst:2261 - The FF/Latch <wcb_bin_9> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <wcb_gray_9> 
INFO:Xst:2261 - The FF/Latch <addr_fifo_din_30> in Unit <cmp_l2p_dma_master> is equivalent to the following FF/Latch, which will be removed : <addr_fifo_din_31> 
INFO:Xst:2261 - The FF/Latch <l2p_dma_sel_o_0> in Unit <cmp_l2p_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <l2p_dma_sel_o_1> <l2p_dma_sel_o_2> <l2p_dma_sel_o_3> <l2p_dma_stb_t> 
INFO:Xst:2261 - The FF/Latch <rcb_bin_9> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <rcb_gray_9> 
INFO:Xst:2261 - The FF/Latch <wcb_bin_9> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <wcb_gray_9> 
INFO:Xst:2261 - The FF/Latch <p2l_dma_adr_o_30> in Unit <cmp_p2l_dma_master> is equivalent to the following FF/Latch, which will be removed : <p2l_dma_adr_o_31> 
INFO:Xst:2261 - The FF/Latch <p2l_dma_sel_o_0> in Unit <cmp_p2l_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <p2l_dma_sel_o_1> <p2l_dma_sel_o_2> <p2l_dma_sel_o_3> <p2l_dma_stb_t> 
INFO:Xst:2261 - The FF/Latch <fmc_adc_core_trig_cfg_int_trig_sel_swb_delay> in Unit <cmp_fmc_adc_100Ms_csr> is equivalent to the following 2 FFs/Latches, which will be removed : <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay> <fmc_adc_core_trig_cfg_int_trig_thres_swb_delay> 
INFO:Xst:2261 - The FF/Latch <rcb_bin_4> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <rcb_gray_4> 
INFO:Xst:2261 - The FF/Latch <wcb_bin_4> in Unit <U_Inferred_FIFO> is equivalent to the following FF/Latch, which will be removed : <wcb_gray_4> 
INFO:Xst:2261 - The FF/Latch <gain_16> in Unit <l_offset_gain_calibr[0].cmp_offset_gain_calibr> is equivalent to the following FF/Latch, which will be removed : <gain_17> 
INFO:Xst:2261 - The FF/Latch <gain_16> in Unit <l_offset_gain_calibr[1].cmp_offset_gain_calibr> is equivalent to the following FF/Latch, which will be removed : <gain_17> 
INFO:Xst:2261 - The FF/Latch <gain_16> in Unit <l_offset_gain_calibr[2].cmp_offset_gain_calibr> is equivalent to the following FF/Latch, which will be removed : <gain_17> 
INFO:Xst:2261 - The FF/Latch <gain_16> in Unit <l_offset_gain_calibr[3].cmp_offset_gain_calibr> is equivalent to the following FF/Latch, which will be removed : <gain_17> 
INFO:Xst:2261 - The FF/Latch <wb_ddr_adr_o_25> in Unit <cmp_fmc_adc_100Ms_core> is equivalent to the following 6 FFs/Latches, which will be removed : <wb_ddr_adr_o_26> <wb_ddr_adr_o_27> <wb_ddr_adr_o_28> <wb_ddr_adr_o_29> <wb_ddr_adr_o_30> <wb_ddr_adr_o_31> 
INFO:Xst:2261 - The FF/Latch <trig_addr_0> in Unit <cmp_fmc_adc_100Ms_core> is equivalent to the following 6 FFs/Latches, which will be removed : <trig_addr_1> <trig_addr_2> <trig_addr_28> <trig_addr_29> <trig_addr_30> <trig_addr_31> 
INFO:Xst:2261 - The FF/Latch <wb_ddr_cyc_o> in Unit <cmp_fmc_adc_100Ms_core> is equivalent to the following FF/Latch, which will be removed : <wb_ddr_we_o> 
INFO:Xst:2261 - The FF/Latch <ddr_cmd_instr_1> in Unit <cmp_ddr3_ctrl_wb_0> is equivalent to the following 4 FFs/Latches, which will be removed : <ddr_cmd_instr_2> <ddr_cmd_byte_addr_0> <ddr_cmd_byte_addr_1> <ddr_cmd_byte_addr_2> 
INFO:Xst:2261 - The FF/Latch <ddr_wr_mask_0> in Unit <cmp_ddr3_ctrl_wb_0> is equivalent to the following 7 FFs/Latches, which will be removed : <ddr_wr_mask_1> <ddr_wr_mask_2> <ddr_wr_mask_3> <ddr_wr_mask_4> <ddr_wr_mask_5> <ddr_wr_mask_6> <ddr_wr_mask_7> 
INFO:Xst:2261 - The FF/Latch <ddr_cmd_instr_1> in Unit <cmp_ddr3_ctrl_wb_1> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_cmd_instr_2> <ddr_cmd_byte_addr_0> <ddr_cmd_byte_addr_1> 
INFO:Xst:2261 - The FF/Latch <irqs_i_reg_2> in Unit <U_Wrapped_VIC> is equivalent to the following 60 FFs/Latches, which will be removed : <irqs_i_reg_3> <irqs_i_reg_4> <irqs_i_reg_5> <irqs_i_reg_6> <irqs_i_reg_7> <irqs_i_reg_8> <irqs_i_reg_9> <irqs_i_reg_10> <irqs_i_reg_11> <irqs_i_reg_12> <irqs_i_reg_13> <irqs_i_reg_14> <irqs_i_reg_15> <irqs_i_reg_16> <irqs_i_reg_17> <irqs_i_reg_18> <irqs_i_reg_19> <irqs_i_reg_20> <irqs_i_reg_21> <irqs_i_reg_22> <irqs_i_reg_23> <irqs_i_reg_24> <irqs_i_reg_25> <irqs_i_reg_26> <irqs_i_reg_27> <irqs_i_reg_28> <irqs_i_reg_29> <irqs_i_reg_30> <irqs_i_reg_31> <irqs_i_reg_32> <vic_imr_2> <vic_imr_3> <vic_imr_4> <vic_imr_5> <vic_imr_6> <vic_imr_7> <vic_imr_8> <vic_imr_9> <vic_imr_10> <vic_imr_11> <vic_imr_12> <vic_imr_13> <vic_imr_14> <vic_imr_15> <vic_imr_16> <vic_imr_17> <vic_imr_18> <vic_imr_19> <vic_imr_20> <vic_imr_21> <vic_imr_22> <vic_imr_23> <vic_imr_24> <vic_imr_25> <vic_imr_26> <vic_imr_27> <vic_imr_28> <vic_imr_29> <vic_imr_30> <vic_imr_31> 
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_5> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_6> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_7> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_8> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_9> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_10> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_11> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_12> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_13> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_14> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_15> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_16> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_17> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_18> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_19> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_20> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_21> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_22> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_23> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_24> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_25> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_26> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_27> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_28> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_29> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_30> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_31> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_0> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_1> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_2> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_7> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_8> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_9> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_10> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_11> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_12> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_13> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_14> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_15> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_16> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_17> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_18> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_19> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_20> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_21> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_22> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_23> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_24> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_25> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_26> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_27> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_28> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_29> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_30> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_31> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_0> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_1> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_2> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_3> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_start_tag_fine_4> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr_cmd_instr_1> (without init value) has a constant value of 0 in block <cmp_ddr3_ctrl_wb_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_2> (without init value) has a constant value of 0 in block <iodrp_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_4> (without init value) has a constant value of 0 in block <iodrp_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_5> (without init value) has a constant value of 0 in block <iodrp_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_6> (without init value) has a constant value of 0 in block <iodrp_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_7> (without init value) has a constant value of 0 in block <iodrp_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_2> (without init value) has a constant value of 0 in block <iodrp_mcb_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_4> (without init value) has a constant value of 0 in block <iodrp_mcb_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_5> (without init value) has a constant value of 0 in block <iodrp_mcb_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_6> (without init value) has a constant value of 0 in block <iodrp_mcb_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_7> (without init value) has a constant value of 0 in block <iodrp_mcb_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <DRP_BKST> (without init value) has a constant value of 0 in block <iodrp_mcb_controller_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <SELFREFRESH_REQ_R1> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <SELFREFRESH_MCB_REQ> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <WarmEnough> (without init value) has a constant value of 1 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MCB_UICMD> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MCB_UIDQCOUNT_0> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MCB_UIDQCOUNT_1> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MCB_UIDQCOUNT_2> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MCB_UIDQCOUNT_3> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <IODRPCTRLR_MEMCELL_ADDR_2> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <IODRPCTRLR_MEMCELL_ADDR_4> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <IODRPCTRLR_MEMCELL_ADDR_5> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <IODRPCTRLR_MEMCELL_ADDR_6> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <IODRPCTRLR_MEMCELL_ADDR_7> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <Active_IODRP_1> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <soft_cal_selfrefresh_req> (without init value) has a constant value of 0 in block <memc3_mcb_raw_wrapper_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_8> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <irqs_i_reg_2> (without init value) has a constant value of 0 in block <U_Wrapped_VIC>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_3> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_4> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_5> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_6> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_7> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_8> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_9> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_10> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_11> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_12> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_13> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_14> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_15> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_16> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_17> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_18> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_19> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_20> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_21> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_22> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_23> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_24> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_25> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_26> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_27> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_28> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_29> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_30> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_end_tag_fine_31> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr_wr_mask_0> (without init value) has a constant value of 0 in block <cmp_ddr3_ctrl_wb_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr_cmd_instr_1> (without init value) has a constant value of 0 in block <cmp_ddr3_ctrl_wb_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_9> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_10> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_11> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_12> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_13> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_14> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_15> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_16> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_17> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_18> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_19> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_20> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_21> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_22> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_23> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_24> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_25> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_26> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_27> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_28> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_29> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_30> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_31> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_8> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <addr_fifo_din_30> (without init value) has a constant value of 0 in block <cmp_l2p_dma_master>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <p2l_dma_adr_o_30> (without init value) has a constant value of 0 in block <cmp_p2l_dma_master>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_fmc_adc_100Ms_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <gain_16> has a constant value of 0 in block <l_offset_gain_calibr[0].cmp_offset_gain_calibr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_1> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_2> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_3> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_4> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_5> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_6> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_7> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_8> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_9> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_10> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_11> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_12> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_13> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_14> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_15> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <inc_data_int> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_dframe_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_dframe_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_valid_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_valid_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_4> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_5> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_8> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_9> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_10> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_11> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_12> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_13> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_14> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_15> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_16> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_17> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_18> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_19> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_20> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_21> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_22> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_23> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_24> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_25> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_26> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_27> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_28> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_29> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_30> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_31> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_0> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_1> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_2> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_3> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_4> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_5> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_tag_fine_6> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_fmc0_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <gain_16> has a constant value of 0 in block <l_offset_gain_calibr[1].cmp_offset_gain_calibr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <gain_16> has a constant value of 0 in block <l_offset_gain_calibr[2].cmp_offset_gain_calibr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <gain_16> has a constant value of 0 in block <l_offset_gain_calibr[3].cmp_offset_gain_calibr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_addr_0> (without init value) has a constant value of 0 in block <cmp_fmc_adc_100Ms_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_8> (without init value) has a constant value of 0 in block <cmp_timetag_core_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_0> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_1> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_2> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_3> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_4> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_5> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_6> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_7> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_8> (without init value) has a constant value of 0 in block <cmp_timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_fmc_adc_100Ms_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <SELFREFRESH_REQ_R2> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_fmc0_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_timetag_core_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_timetag_core_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <SELFREFRESH_REQ_R3> (without init value) has a constant value of 0 in block <mcb_soft_calibration_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_fmc0_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_timetag_core_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_fmc0_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_timetag_core_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_fmc0_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_timetag_core_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_fmc0_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_timetag_core_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_fmc0_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_timetag_core_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_len_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_len_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <q_o_44> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_45> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_46> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_47> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_48> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_49> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_50> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_51> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_52> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_53> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_54> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_55> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_56> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_57> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_58> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_59> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_60> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_61> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_62> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <wb_adr_t_12> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_13> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_14> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_15> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_16> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_17> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_21> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_22> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <q_o_62> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <q_o_63> of sequential type is unconnected in block <U_Inferred_FIFO>.
WARNING:Xst:2677 - Node <r_master_adr_0> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_1> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_13> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_14> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_15> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_16> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_17> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_18> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_19> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_20> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_21> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_22> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_23> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_24> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_25> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_26> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_27> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_28> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_29> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_30> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <r_master_adr_31> of sequential type is unconnected in block <cmp_xwb_reg>.
WARNING:Xst:2677 - Node <wb_ddr_adr_o_25> of sequential type is unconnected in block <cmp_fmc_adc_100Ms_core>.
WARNING:Xst:2677 - Node <wb_addr_d_25> of sequential type is unconnected in block <cmp_ddr3_ctrl_wb_0>.
WARNING:Xst:2677 - Node <wb_addr_d_26> of sequential type is unconnected in block <cmp_ddr3_ctrl_wb_0>.
WARNING:Xst:2677 - Node <ddr_cmd_byte_addr_28> of sequential type is unconnected in block <cmp_ddr3_ctrl_wb_0>.
WARNING:Xst:2677 - Node <ddr_cmd_byte_addr_29> of sequential type is unconnected in block <cmp_ddr3_ctrl_wb_0>.
WARNING:Xst:2677 - Node <wb_addr_d_26> of sequential type is unconnected in block <cmp_ddr3_ctrl_wb_1>.
WARNING:Xst:2677 - Node <wb_addr_d_27> of sequential type is unconnected in block <cmp_ddr3_ctrl_wb_1>.
WARNING:Xst:2677 - Node <ddr_cmd_byte_addr_28> of sequential type is unconnected in block <cmp_ddr3_ctrl_wb_1>.
WARNING:Xst:2677 - Node <ddr_cmd_byte_addr_29> of sequential type is unconnected in block <cmp_ddr3_ctrl_wb_1>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<5:1>> (without init value) have a constant value of 0 in block <carrier_csr>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:6>> (without init value) have a constant value of 0 in block <dma_controller_wb_slave>.
WARNING:Xst:2404 -  FFs/Latches <addr_fifo_din<31:30>> (without init value) have a constant value of 0 in block <l2p_dma_master>.
WARNING:Xst:2404 -  FFs/Latches <p2l_dma_adr_o<31:30>> (without init value) have a constant value of 0 in block <p2l_dma_master>.
WARNING:Xst:2404 -  FFs/Latches <wb_ddr_adr_o<31:25>> (without init value) have a constant value of 0 in block <fmc_adc_100Ms_core>.
WARNING:Xst:2404 -  FFs/Latches <trig_addr<31:28>> (without init value) have a constant value of 0 in block <fmc_adc_100Ms_core>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<7:6>> (without init value) have a constant value of 0 in block <fmc_adc_100Ms_csr>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<7:1>> (without init value) have a constant value of 0 in block <fmc_adc_eic>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:1>> (without init value) have a constant value of 0 in block <timetag_core_regs>.
WARNING:Xst:2404 -  FFs/Latches <ddr_cmd_instr<2:1>> (without init value) have a constant value of 0 in block <ddr3_ctrl_wb_1>.
WARNING:Xst:2404 -  FFs/Latches <ddr_cmd_instr<2:1>> (without init value) have a constant value of 0 in block <ddr3_ctrl_wb_2>.
WARNING:Xst:2404 -  FFs/Latches <IODRPCTRLR_MEMCELL_ADDR<7:4>> (without init value) have a constant value of 0 in block <mcb_soft_calibration>.
WARNING:Xst:2404 -  FFs/Latches <Active_IODRP<1:1>> (without init value) have a constant value of 0 in block <mcb_soft_calibration>.
WARNING:Xst:2404 -  FFs/Latches <vic_imr<31:2>> (without init value) have a constant value of 0 in block <wb_vic>.
WARNING:Xst:2404 -  FFs/Latches <irqs_i_reg<32:2>> (without init value) have a constant value of 0 in block <wb_vic>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:1>> (without init value) have a constant value of 0 in block <wb_slave_vic>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<6:1>> (without init value) have a constant value of 0 in block <dma_eic>.

Synthesizing (advanced) Unit <ext_pulse_sync>.
The following registers are absorbed into counter <s_pulse_length_cnt>: 1 register on signal <s_pulse_length_cnt>.
The following registers are absorbed into counter <s_monostable_cnt>: 1 register on signal <s_monostable_cnt>.
Unit <ext_pulse_sync> synthesized (advanced).

Synthesizing (advanced) Unit <fmc_adc_100Ms_core>.
The following registers are absorbed into counter <trig_delay_cnt>: 1 register on signal <trig_delay_cnt>.
The following registers are absorbed into counter <shots_cnt>: 1 register on signal <shots_cnt>.
The following registers are absorbed into counter <samples_cnt>: 1 register on signal <samples_cnt>.
The following registers are absorbed into counter <dpram_addra_cnt>: 1 register on signal <dpram_addra_cnt>.
The following registers are absorbed into counter <ram_addr_cnt>: 1 register on signal <ram_addr_cnt>.
Unit <fmc_adc_100Ms_core> synthesized (advanced).

Synthesizing (advanced) Unit <gc_dyn_glitch_filt>.
The following registers are absorbed into counter <filt_cnt>: 1 register on signal <filt_cnt>.
Unit <gc_dyn_glitch_filt> synthesized (advanced).

Synthesizing (advanced) Unit <gc_extend_pulse>.
The following registers are absorbed into counter <cntr>: 1 register on signal <cntr>.
Unit <gc_extend_pulse> synthesized (advanced).

Synthesizing (advanced) Unit <gc_frequency_meter>.
The following registers are absorbed into counter <cntr_gate>: 1 register on signal <cntr_gate>.
The following registers are absorbed into counter <cntr_meas>: 1 register on signal <cntr_meas>.
Unit <gc_frequency_meter> synthesized (advanced).

Synthesizing (advanced) Unit <generic_dpram_dualclock>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <qa_o> <qb_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 2048-word x 64-bit                  |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clka_i>        | rise     |
    |     weA            | connected to signal <wea_i>         | high     |
    |     addrA          | connected to signal <aa_i>          |          |
    |     diA            | connected to signal <da_i>          |          |
    |     doA            | connected to signal <qa_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 2048-word x 64-bit                  |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clkb_i>        | rise     |
    |     weB            | connected to signal <GND>           | high     |
    |     addrB          | connected to signal <ab_i>          |          |
    |     diB            | connected to signal <GND>           |          |
    |     doB            | connected to signal <qb_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <generic_dpram_dualclock> synthesized (advanced).

Synthesizing (advanced) Unit <generic_dpram_sameclock_1>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <qa_o> <qb_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 2048-word x 64-bit                  |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to signal <wea_i>         | high     |
    |     addrA          | connected to signal <aa_i>          |          |
    |     diA            | connected to signal <da_i>          |          |
    |     doA            | connected to signal <qa_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 2048-word x 64-bit                  |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     weB            | connected to signal <GND>           | high     |
    |     addrB          | connected to signal <ab_i>          |          |
    |     diB            | connected to signal <GND>           |          |
    |     doB            | connected to signal <qb_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <generic_dpram_sameclock_1> synthesized (advanced).

Synthesizing (advanced) Unit <generic_dpram_sameclock_2>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <qa_o> <qb_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 64-word x 65-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to signal <wea_i>         | high     |
    |     addrA          | connected to signal <aa_i>          |          |
    |     diA            | connected to signal <da_i>          |          |
    |     doA            | connected to signal <qa_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 64-word x 65-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     weB            | connected to signal <GND>           | high     |
    |     addrB          | connected to signal <ab_i>          |          |
    |     diB            | connected to signal <GND>           |          |
    |     doB            | connected to signal <qb_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <generic_dpram_sameclock_2> synthesized (advanced).

Synthesizing (advanced) Unit <i2c_master_bit_ctrl>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
Unit <i2c_master_bit_ctrl> synthesized (advanced).

Synthesizing (advanced) Unit <inferred_async_fifo_1>.
The following registers are absorbed into counter <wcb_bin>: 1 register on signal <wcb_bin>.
The following registers are absorbed into counter <rcb_bin>: 1 register on signal <rcb_bin>.
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <q_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 128-word x 64-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_wr_i>      | rise     |
    |     weA            | connected to signal <we_int>        | high     |
    |     addrA          | connected to signal <wcb_bin<6:0>>  |          |
    |     diA            | connected to signal <d_i>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 128-word x 64-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_rd_i>      | rise     |
    |     enB            | connected to signal <rd_int>        | high     |
    |     addrB          | connected to signal <rcb_bin<6:0>>  |          |
    |     doB            | connected to signal <q_o>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <inferred_async_fifo_1> synthesized (advanced).

Synthesizing (advanced) Unit <inferred_async_fifo_2>.
The following registers are absorbed into counter <wcb_bin>: 1 register on signal <wcb_bin>.
The following registers are absorbed into counter <rcb_bin>: 1 register on signal <rcb_bin>.
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <q_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 128-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_wr_i>      | rise     |
    |     weA            | connected to signal <we_int>        | high     |
    |     addrA          | connected to signal <wcb_bin<6:0>>  |          |
    |     diA            | connected to signal <d_i>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 128-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_rd_i>      | rise     |
    |     enB            | connected to signal <rd_int>        | high     |
    |     addrB          | connected to signal <rcb_bin<6:0>>  |          |
    |     doB            | connected to signal <q_o>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <inferred_async_fifo_2> synthesized (advanced).

Synthesizing (advanced) Unit <inferred_async_fifo_3>.
The following registers are absorbed into counter <wcb_bin>: 1 register on signal <wcb_bin>.
The following registers are absorbed into counter <rcb_bin>: 1 register on signal <rcb_bin>.
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <q_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 512-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_wr_i>      | rise     |
    |     weA            | connected to signal <we_int>        | high     |
    |     addrA          | connected to signal <wcb_bin<8:0>>  |          |
    |     diA            | connected to signal <d_i>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 512-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_rd_i>      | rise     |
    |     enB            | connected to signal <rd_int>        | high     |
    |     addrB          | connected to signal <rcb_bin<8:0>>  |          |
    |     doB            | connected to signal <q_o>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <inferred_async_fifo_3> synthesized (advanced).

Synthesizing (advanced) Unit <inferred_async_fifo_4>.
The following registers are absorbed into counter <wcb_bin>: 1 register on signal <wcb_bin>.
The following registers are absorbed into counter <rcb_bin>: 1 register on signal <rcb_bin>.
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <q_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 512-word x 64-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_wr_i>      | rise     |
    |     weA            | connected to signal <we_int>        | high     |
    |     addrA          | connected to signal <wcb_bin<8:0>>  |          |
    |     diA            | connected to signal <d_i>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 512-word x 64-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_rd_i>      | rise     |
    |     enB            | connected to signal <rd_int>        | high     |
    |     addrB          | connected to signal <rcb_bin<8:0>>  |          |
    |     doB            | connected to signal <q_o>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <inferred_async_fifo_4> synthesized (advanced).

Synthesizing (advanced) Unit <inferred_async_fifo_5>.
The following registers are absorbed into counter <wcb_bin>: 1 register on signal <wcb_bin>.
The following registers are absorbed into counter <rcb_bin>: 1 register on signal <rcb_bin>.
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <q_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 65-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_wr_i>      | rise     |
    |     weA            | connected to signal <we_int>        | high     |
    |     addrA          | connected to signal <wcb_bin<3:0>>  |          |
    |     diA            | connected to signal <d_i>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 16-word x 65-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_rd_i>      | rise     |
    |     enB            | connected to signal <rd_int>        | high     |
    |     addrB          | connected to signal <rcb_bin<3:0>>  |          |
    |     doB            | connected to signal <q_o>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <inferred_async_fifo_5> synthesized (advanced).

Synthesizing (advanced) Unit <inferred_sync_fifo>.
The following registers are absorbed into counter <rd_ptr>: 1 register on signal <rd_ptr>.
The following registers are absorbed into counter <wr_ptr>: 1 register on signal <wr_ptr>.
The following registers are absorbed into counter <usedw>: 1 register on signal <usedw>.
Unit <inferred_sync_fifo> synthesized (advanced).

Synthesizing (advanced) Unit <iodrp_controller>.
The following registers are absorbed into counter <bit_cnt>: 1 register on signal <bit_cnt>.
Unit <iodrp_controller> synthesized (advanced).

Synthesizing (advanced) Unit <iodrp_mcb_controller>.
The following registers are absorbed into counter <bit_cnt>: 1 register on signal <bit_cnt>.
Unit <iodrp_mcb_controller> synthesized (advanced).

Synthesizing (advanced) Unit <l2p_dma_master>.
The following registers are absorbed into counter <dma_length_cnt>: 1 register on signal <dma_length_cnt>.
The following registers are absorbed into counter <target_addr_cnt>: 1 register on signal <target_addr_cnt>.
The following registers are absorbed into counter <wb_read_cnt>: 1 register on signal <wb_read_cnt>.
The following registers are absorbed into counter <wb_ack_cnt>: 1 register on signal <wb_ack_cnt>.
Unit <l2p_dma_master> synthesized (advanced).

Synthesizing (advanced) Unit <mcb_soft_calibration>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
The following registers are absorbed into counter <WAIT_200us_COUNTER>: 1 register on signal <WAIT_200us_COUNTER>.
The following registers are absorbed into counter <RstCounter>: 1 register on signal <RstCounter>.
The following registers are absorbed into counter <DQS_DELAY>: 1 register on signal <DQS_DELAY>.
The following registers are absorbed into counter <counter_inc>: 1 register on signal <counter_inc>.
The following registers are absorbed into counter <counter_dec>: 1 register on signal <counter_dec>.
The following registers are absorbed into counter <WaitTimer>: 1 register on signal <WaitTimer>.
Unit <mcb_soft_calibration> synthesized (advanced).

Synthesizing (advanced) Unit <monostable>.
The following registers are absorbed into counter <s_monostable_cnt>: 1 register on signal <s_monostable_cnt>.
Unit <monostable> synthesized (advanced).

Synthesizing (advanced) Unit <p2l_dma_master>.
The following registers are absorbed into counter <target_addr_cnt>: 1 register on signal <target_addr_cnt>.
The following registers are absorbed into counter <p2l_data_cnt>: 1 register on signal <p2l_data_cnt>.
The following registers are absorbed into counter <wb_write_cnt>: 1 register on signal <wb_write_cnt>.
The following registers are absorbed into counter <wb_ack_cnt>: 1 register on signal <wb_ack_cnt>.
Unit <p2l_dma_master> synthesized (advanced).

Synthesizing (advanced) Unit <sdb_rom_1>.
INFO:Xst:3226 - The RAM <Mram_rom> will be implemented as a BLOCK RAM, absorbing the following register(s): <adr_reg>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_sys_i>     | rise     |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <slave_i_adr>   |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <sdb_rom_1> synthesized (advanced).

Synthesizing (advanced) Unit <sdb_rom_2>.
INFO:Xst:3226 - The RAM <Mram_rom> will be implemented as a BLOCK RAM, absorbing the following register(s): <adr_reg>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 128-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_sys_i>     | rise     |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <slave_i_adr>   |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <sdb_rom_2> synthesized (advanced).

Synthesizing (advanced) Unit <serdes_1_to_n_clk_pll_s2_diff>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <serdes_1_to_n_clk_pll_s2_diff> synthesized (advanced).

Synthesizing (advanced) Unit <serdes_1_to_n_data_s2_se_1>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <serdes_1_to_n_data_s2_se_1> synthesized (advanced).

Synthesizing (advanced) Unit <serdes_1_to_n_data_s2_se_2>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <serdes_1_to_n_data_s2_se_2> synthesized (advanced).

Synthesizing (advanced) Unit <spec_top_fmc_adc_100Ms>.
The following registers are absorbed into counter <led_pwm_val>: 1 register on signal <led_pwm_val>.
The following registers are absorbed into counter <powerup_reset_cnt>: 1 register on signal <powerup_reset_cnt>.
The following registers are absorbed into counter <led_pwm_cnt>: 1 register on signal <led_pwm_cnt>.
The following registers are absorbed into counter <led_pwm_update_cnt>: 1 register on signal <led_pwm_update_cnt>.
Unit <spec_top_fmc_adc_100Ms> synthesized (advanced).

Synthesizing (advanced) Unit <spi_clgen>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
Unit <spi_clgen> synthesized (advanced).

Synthesizing (advanced) Unit <timetag_core>.
The following registers are absorbed into counter <timetag_coarse_cnt>: 1 register on signal <timetag_coarse_cnt>.
The following registers are absorbed into counter <timetag_seconds_cnt>: 1 register on signal <timetag_seconds_cnt>.
Unit <timetag_core> synthesized (advanced).

Synthesizing (advanced) Unit <wb_vic>.
The following registers are absorbed into counter <timeout_count>: 1 register on signal <timeout_count>.
INFO:Xst:3226 - The RAM <Mram_vector_table> will be implemented as a BLOCK RAM, absorbing the following register(s): <vic_ivt_ram_data_towb> <vic_ivt_ram_data_int>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_sys_i>     | rise     |
    |     weA            | connected to signal <vic_ivt_ram_wr> | high     |
    |     addrA          | connected to signal <vic_ivt_ram_addr_wb> |          |
    |     diA            | connected to signal <vic_ivt_ram_data_fromwb> |          |
    |     doA            | connected to signal <vic_ivt_ram_data_towb> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_sys_i>     | rise     |
    |     addrB          | connected to signal <current_irq>   |          |
    |     doB            | connected to signal <vic_ivt_ram_data_int> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <wb_vic> synthesized (advanced).

Synthesizing (advanced) Unit <wbmaster32>.
The following registers are absorbed into counter <wb_ack_timeout_cnt>: 1 register on signal <wb_ack_timeout_cnt>.
Unit <wbmaster32> synthesized (advanced).
WARNING:Xst:2677 - Node <wr_count_7> of sequential type is unconnected in block <inferred_async_fifo_1>.
WARNING:Xst:2677 - Node <wr_count_7> of sequential type is unconnected in block <inferred_async_fifo_2>.
WARNING:Xst:2677 - Node <wr_count_4> of sequential type is unconnected in block <inferred_async_fifo_5>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 12
 128x32-bit dual-port block RAM                        : 1
 128x32-bit single-port block Read Only RAM            : 1
 128x64-bit dual-port block RAM                        : 1
 16x65-bit dual-port block RAM                         : 1
 2048x64-bit dual-port block RAM                       : 2
 256x32-bit single-port block Read Only RAM            : 1
 32x32-bit dual-port block RAM                         : 1
 512x32-bit dual-port block RAM                        : 2
 512x64-bit dual-port block RAM                        : 1
 64x65-bit dual-port block RAM                         : 1
# Adders/Subtractors                                   : 80
 10-bit adder                                          : 9
 10-bit subtractor                                     : 6
 11-bit adder                                          : 2
 11-bit addsub                                         : 1
 11-bit subtractor                                     : 1
 14-bit subtractor                                     : 2
 16-bit adder                                          : 2
 17-bit adder                                          : 4
 18-bit adder                                          : 4
 3-bit subtractor                                      : 2
 30-bit adder                                          : 1
 30-bit subtractor                                     : 2
 32-bit adder                                          : 3
 32-bit subtractor                                     : 5
 5-bit adder                                           : 2
 5-bit addsub                                          : 2
 5-bit subtractor                                      : 2
 6-bit adder                                           : 3
 6-bit subtractor                                      : 4
 7-bit adder                                           : 1
 7-bit subtractor                                      : 3
 8-bit adder                                           : 7
 8-bit subtractor                                      : 9
 9-bit adder                                           : 3
# Counters                                             : 63
 10-bit up counter                                     : 8
 11-bit down counter                                   : 1
 11-bit up counter                                     : 1
 12-bit up counter                                     : 1
 16-bit down counter                                   : 4
 16-bit up counter                                     : 2
 17-bit up counter                                     : 1
 17-bit updown counter                                 : 1
 2-bit down counter                                    : 1
 2-bit up counter                                      : 1
 23-bit down counter                                   : 3
 25-bit down counter                                   : 2
 25-bit up counter                                     : 1
 3-bit up counter                                      : 3
 30-bit down counter                                   : 1
 30-bit up counter                                     : 2
 32-bit down counter                                   : 1
 32-bit up counter                                     : 9
 5-bit up counter                                      : 2
 6-bit up counter                                      : 3
 7-bit down counter                                    : 1
 7-bit updown counter                                  : 1
 8-bit up counter                                      : 8
 8-bit updown counter                                  : 2
 9-bit up counter                                      : 3
# Registers                                            : 6835
 Flip-Flops                                            : 6835
# Comparators                                          : 84
 10-bit comparator equal                               : 6
 10-bit comparator greater                             : 1
 10-bit comparator lessequal                           : 6
 11-bit comparator equal                               : 1
 11-bit comparator greater                             : 3
 16-bit comparator equal                               : 3
 16-bit comparator greater                             : 1
 17-bit comparator equal                               : 1
 17-bit comparator lessequal                           : 8
 30-bit comparator greater                             : 2
 32-bit comparator equal                               : 2
 32-bit comparator greater                             : 1
 4-bit comparator equal                                : 2
 5-bit comparator equal                                : 2
 5-bit comparator lessequal                            : 1
 6-bit comparator equal                                : 1
 6-bit comparator greater                              : 1
 7-bit comparator equal                                : 5
 7-bit comparator greater                              : 4
 8-bit comparator equal                                : 13
 8-bit comparator greater                              : 8
 8-bit comparator lessequal                            : 4
 8-bit comparator not equal                            : 2
 9-bit comparator equal                                : 6
# Multiplexers                                         : 1530
 1-bit 128-to-1 multiplexer                            : 2
 1-bit 2-to-1 multiplexer                              : 1185
 1-bit 3-to-1 multiplexer                              : 4
 1-bit 7-to-1 multiplexer                              : 32
 1-bit 8-to-1 multiplexer                              : 16
 10-bit 2-to-1 multiplexer                             : 4
 11-bit 2-to-1 multiplexer                             : 13
 14-bit 2-to-1 multiplexer                             : 4
 16-bit 2-to-1 multiplexer                             : 16
 16-bit 4-to-1 multiplexer                             : 1
 2-bit 2-to-1 multiplexer                              : 8
 3-bit 2-to-1 multiplexer                              : 8
 30-bit 2-to-1 multiplexer                             : 6
 32-bit 2-to-1 multiplexer                             : 104
 32-bit 3-to-1 multiplexer                             : 1
 32-bit 4-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 22
 4-bit 6-to-1 multiplexer                              : 2
 5-bit 2-to-1 multiplexer                              : 37
 6-bit 2-to-1 multiplexer                              : 9
 64-bit 2-to-1 multiplexer                             : 3
 65-bit 2-to-1 multiplexer                             : 3
 7-bit 2-to-1 multiplexer                              : 3
 8-bit 2-to-1 multiplexer                              : 45
 9-bit 2-to-1 multiplexer                              : 1
# Logic shifters                                       : 2
 1-bit shifter logical left                            : 2
# FSMs                                                 : 18
# Xors                                                 : 135
 1-bit xor2                                            : 84
 1-bit xor3                                            : 24
 32-bit xor2                                           : 15
 4-bit xor2                                            : 2
 7-bit xor2                                            : 4
 9-bit xor2                                            : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <inc_data_int> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_15> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_14> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_13> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_12> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_11> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_10> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_9> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_8> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_7> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_6> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_5> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_4> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_3> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_2> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_1> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <incdec_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <valid_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <trig_addr_0> (without init value) has a constant value of 0 in block <fmc_adc_100Ms_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_addr_1> (without init value) has a constant value of 0 in block <fmc_adc_100Ms_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_addr_2> (without init value) has a constant value of 0 in block <fmc_adc_100Ms_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <gain_16> has a constant value of 0 in block <offset_gain_s>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <gain_17> has a constant value of 0 in block <offset_gain_s>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <acq_stop_tag_fine_31> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_30> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_29> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_28> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_27> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_26> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_25> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_24> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_23> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_22> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_21> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_20> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_19> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_18> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_17> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_16> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_15> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_14> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_13> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_12> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_11> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_10> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_9> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_8> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_7> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_6> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_5> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_4> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_3> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_2> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_1> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_stop_tag_fine_0> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_31> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_30> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_29> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_28> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_27> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_26> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_25> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_24> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_23> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_22> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_21> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_20> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_19> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_18> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_17> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_16> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_15> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_14> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_13> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_12> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_11> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_10> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_9> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_8> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_7> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_6> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_5> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_4> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_3> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_2> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_1> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_end_tag_fine_0> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_31> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_30> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_29> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_28> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_27> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_26> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_25> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_24> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_23> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_22> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_21> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_20> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_19> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_18> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_17> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_16> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_15> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_14> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_13> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_12> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_11> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_10> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_9> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_8> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_7> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_6> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_5> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_4> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_3> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_2> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_1> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <trig_tag_fine_0> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_31> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_30> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_29> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_28> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_27> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_26> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_25> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_24> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_23> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_22> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_21> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_20> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_19> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_18> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_17> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_16> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_15> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_14> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_13> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_12> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_11> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_10> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_9> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_8> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_7> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_6> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_5> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_4> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_3> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_2> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_1> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <acq_start_tag_fine_0> (without init value) has a constant value of 0 in block <timetag_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr_cmd_byte_addr_0> (without init value) has a constant value of 0 in block <ddr3_ctrl_wb_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_cmd_byte_addr_1> (without init value) has a constant value of 0 in block <ddr3_ctrl_wb_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_cmd_byte_addr_2> (without init value) has a constant value of 0 in block <ddr3_ctrl_wb_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr_cmd_byte_addr_0> (without init value) has a constant value of 0 in block <ddr3_ctrl_wb_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_cmd_byte_addr_1> (without init value) has a constant value of 0 in block <ddr3_ctrl_wb_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <soft_cal_selfrefresh_req> (without init value) has a constant value of 0 in block <mcb_raw_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <MCB_UICMD> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <MCB_UIDQCOUNT_0> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <MCB_UIDQCOUNT_1> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <MCB_UIDQCOUNT_2> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <MCB_UIDQCOUNT_3> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IODRPCTRLR_MEMCELL_ADDR_2> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <DRP_BKST> (without init value) has a constant value of 0 in block <iodrp_controller>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <l2p_dma_sel_o_0> in Unit <l2p_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <l2p_dma_sel_o_1> <l2p_dma_sel_o_2> <l2p_dma_sel_o_3> <l2p_dma_stb_t> 
INFO:Xst:2261 - The FF/Latch <p2l_dma_sel_o_0> in Unit <p2l_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <p2l_dma_sel_o_1> <p2l_dma_sel_o_2> <p2l_dma_sel_o_3> <p2l_dma_stb_t> 
INFO:Xst:2261 - The FF/Latch <wb_ddr_cyc_o> in Unit <fmc_adc_100Ms_core> is equivalent to the following FF/Latch, which will be removed : <wb_ddr_we_o> 
INFO:Xst:2261 - The FF/Latch <fmc_adc_core_trig_cfg_int_trig_sel_swb_delay> in Unit <fmc_adc_100Ms_csr> is equivalent to the following 2 FFs/Latches, which will be removed : <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay> <fmc_adc_core_trig_cfg_int_trig_thres_swb_delay> 
INFO:Xst:2261 - The FF/Latch <dma_stat_int_read_3> in Unit <dma_controller_wb_slave> is equivalent to the following 28 FFs/Latches, which will be removed : <dma_stat_int_read_4> <dma_stat_int_read_5> <dma_stat_int_read_6> <dma_stat_int_read_7> <dma_stat_int_read_8> <dma_stat_int_read_9> <dma_stat_int_read_10> <dma_stat_int_read_11> <dma_stat_int_read_12> <dma_stat_int_read_13> <dma_stat_int_read_14> <dma_stat_int_read_15> <dma_stat_int_read_16> <dma_stat_int_read_17> <dma_stat_int_read_18> <dma_stat_int_read_19> <dma_stat_int_read_20> <dma_stat_int_read_21> <dma_stat_int_read_22> <dma_stat_int_read_23> <dma_stat_int_read_24> <dma_stat_int_read_25> <dma_stat_int_read_26> <dma_stat_int_read_27> <dma_stat_int_read_28> <dma_stat_int_read_29> <dma_stat_int_read_30> <dma_stat_int_read_31> 
INFO:Xst:2261 - The FF/Latch <memcell_addr_reg_2> in Unit <iodrp_controller> is equivalent to the following 4 FFs/Latches, which will be removed : <memcell_addr_reg_4> <memcell_addr_reg_5> <memcell_addr_reg_6> <memcell_addr_reg_7> 
INFO:Xst:2261 - The FF/Latch <memcell_addr_reg_2> in Unit <iodrp_mcb_controller> is equivalent to the following 5 FFs/Latches, which will be removed : <memcell_addr_reg_4> <memcell_addr_reg_5> <memcell_addr_reg_6> <memcell_addr_reg_7> <DRP_BKST> 
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <SELFREFRESH_REQ_R1> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <SELFREFRESH_MCB_REQ> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <WarmEnough> (without init value) has a constant value of 1 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <SELFREFRESH_REQ_R2> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <SELFREFRESH_REQ_R3> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <WAIT_SELFREFRESH_EXIT_DQS_CAL> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <PERFORM_START_DYN_CAL_AFTER_SELFREFRESH> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <WaitCountEnable> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <SELFREFRESH_MCB_MODE_R3> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <START_DYN_CAL_STATE_R1> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_2> (without init value) has a constant value of 0 in block <iodrp_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <memcell_addr_reg_2> (without init value) has a constant value of 0 in block <iodrp_mcb_controller>. This FF/Latch will be trimmed during the optimization process.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/FSM_1> on signal <state[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0010  | 0010
 0011  | 0011
 0100  | 0100
 0101  | 0101
 0110  | 0110
 0111  | 0111
 0001  | 0001
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/FSM_2> on signal <state[1:4]> with user encoding.
Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/FSM_2> on signal <state[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0010  | 0010
 0011  | 0011
 0100  | 0100
 0101  | 0101
 0110  | 0110
 0111  | 0111
 0001  | 0001
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_dma_controller/FSM_5> on signal <dma_ctrl_current_state[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 dma_idle           | 000
 dma_start_transfer | 001
 dma_transfer       | 010
 dma_start_chain    | 011
 dma_chain          | 100
 dma_error          | 101
 dma_abort          | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_wbmaster32/FSM_3> on signal <l2p_read_cpl_current_state[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 l2p_idle   | 00
 l2p_header | 01
 l2p_data   | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_wbmaster32/FSM_4> on signal <wishbone_current_state[1:2]> with user encoding.
--------------------------
 State        | Encoding
--------------------------
 wb_idle      | 00
 wb_read_fifo | 01
 wb_cycle     | 10
 wb_wait_ack  | 11
--------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_l2p_dma_master/FSM_6> on signal <l2p_dma_current_state[1:3]> with user encoding.
---------------------------
 State         | Encoding
---------------------------
 l2p_idle      | 000
 l2p_wait_data | 001
 l2p_header    | 010
 l2p_addr_h    | 011
 l2p_addr_l    | 100
 l2p_data      | 101
 l2p_last_data | 110
 l2p_wait_rdy  | 111
---------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_p2l_dma_master/FSM_7> on signal <p2l_dma_current_state[1:3]> with user encoding.
--------------------------------------
 State                    | Encoding
--------------------------------------
 p2l_idle                 | 000
 p2l_header               | 001
 p2l_addr_h               | 010
 p2l_addr_l               | 011
 p2l_wait_read_completion | 100
--------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_clk_in/FSM_0> on signal <state[1:9]> with one-hot encoding.
--------------------
 State | Encoding
--------------------
 0000  | 000000001
 0001  | 000000010
 0010  | 000000100
 0011  | 000001000
 0100  | 000010000
 0101  | 000100000
 0111  | 001000000
 1001  | 010000000
 0110  | 100000000
--------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/FSM_11> on signal <acq_fsm_current_state[1:3]> with gray encoding.
-----------------------
 State     | Encoding
-----------------------
 idle      | 000
 pre_trig  | 001
 wait_trig | 011
 post_trig | 010
 trig_tag  | 110
 decr_shot | 111
-----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/FSM_9> on signal <c_state[1:3]> with user encoding.
Optimizing FSM <cmp_fmc_adc_mezzanine_0/cmp_fmc_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/FSM_9> on signal <c_state[1:3]> with user encoding.
----------------------
 State    | Encoding
----------------------
 st_idle  | 000
 st_start | 001
 st_read  | 010
 st_write | 011
 st_ack   | 100
 st_stop  | 101
----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/FSM_10> on signal <c_state[1:5]> with user encoding.
Optimizing FSM <cmp_fmc_adc_mezzanine_0/cmp_fmc_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/FSM_10> on signal <c_state[1:5]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00000
 start_a | 00001
 start_b | 00010
 start_c | 00011
 start_d | 00100
 start_e | 00101
 stop_a  | 00110
 stop_b  | 00111
 stop_c  | 01000
 stop_d  | 01001
 rd_a    | 01010
 rd_b    | 01011
 rd_c    | 01100
 rd_d    | 01101
 wr_a    | 01110
 wr_b    | 01111
 wr_c    | 10000
 wr_d    | 10001
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/FSM_12> on signal <STATE[1:5]> with gray encoding.
--------------------
 State  | Encoding
--------------------
 000000 | 00000
 110010 | 00001
 000010 | unreached
 000001 | unreached
 000011 | unreached
 000100 | unreached
 000101 | unreached
 000110 | unreached
 000111 | unreached
 001000 | unreached
 001001 | unreached
 001010 | unreached
 001011 | unreached
 001100 | unreached
 001101 | unreached
 100010 | unreached
 010000 | unreached
 001110 | unreached
 001111 | unreached
 010001 | unreached
 010010 | unreached
 010011 | unreached
 010100 | unreached
 010101 | unreached
 010110 | unreached
 010111 | unreached
 011000 | unreached
 011001 | unreached
 011010 | unreached
 011011 | unreached
 011100 | unreached
 011101 | unreached
 011110 | unreached
 011111 | unreached
 100000 | unreached
 100001 | unreached
 100011 | unreached
 100100 | unreached
 100101 | unreached
 110001 | 00011
 100111 | 00010
 100110 | 00110
 101000 | 00111
 101001 | 00101
 101010 | 00100
 101011 | 01100
 101100 | 01101
 101101 | 01111
 101110 | 01110
 101111 | 01010
 110000 | 01011
 110011 | 01001
 110100 | 01000
 110101 | 11000
 110110 | 11001
 111000 | 11011
 111001 | 11010
 110111 | 11110
 111010 | unreached
--------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/FSM_13> on signal <state[1:8]> with one-hot encoding.
-------------------
 State | Encoding
-------------------
 000   | 00000001
 001   | 00000010
 010   | 00000100
 011   | 00001000
 111   | 00010000
 100   | 00100000
 101   | 01000000
 110   | 10000000
-------------------
Optimizing FSM <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/FSM_14> on signal <state[1:4]> with gray encoding.
-------------------------------
 State             | Encoding
-------------------------------
 ready             | 0000
 decide            | 0001
 addr_phase        | 0011
 addr_to_data_gap  | 0010
 addr_to_data_gap2 | 0111
 addr_to_data_gap3 | 0101
 data_phase        | 0100
 almost_ready      | 0110
 almost_ready2     | 1100
 almost_ready3     | 1101
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_vic/U_Wrapped_VIC/FSM_8> on signal <state[1:3]> with gray encoding.
-------------------------
 State       | Encoding
-------------------------
 wait_irq    | 000
 process_irq | 110
 wait_ack    | 011
 wait_mem    | 001
 wait_idle   | 010
-------------------------
WARNING:Xst:2677 - Node <N_Term_Prev_0> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <N_Term_Prev_1> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <N_Term_Prev_2> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <N_Term_Prev_3> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <N_Term_Prev_4> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <N_Term_Prev_5> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <N_Term_Prev_6> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <P_Term_Prev_0> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <P_Term_Prev_1> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <P_Term_Prev_2> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <P_Term_Prev_3> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <P_Term_Prev_4> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:2677 - Node <P_Term_Prev_5> of sequential type is unconnected in block <mcb_soft_calibration>.
WARNING:Xst:1710 - FF/Latch <rddata_reg_31> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_30> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_29> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_28> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_27> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_26> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_25> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_23> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_22> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_21> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_20> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_19> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_18> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_17> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_15> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_14> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_13> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_12> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_11> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_10> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_9> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_7> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_6> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_5> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_4> (without init value) has a constant value of 0 in block <carrier_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rddata_reg_31> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_30> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_29> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_28> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_27> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_26> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_25> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_23> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_22> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_21> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_20> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_19> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_18> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_17> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_16> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_15> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_14> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_13> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_12> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_11> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_10> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_9> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_7> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_6> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_5> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_4> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_3> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_2> (without init value) has a constant value of 0 in block <fmc_adc_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <DQS_DELAY_INITIAL_7> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <TARGET_DQS_DELAY_7> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IODRPCTRLR_WRITE_DATA_7> (without init value) has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <swi_mask_2> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_3> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_4> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_5> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_6> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_7> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_8> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_9> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_10> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_11> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_12> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_13> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_14> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_15> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_16> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_17> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_18> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_19> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_20> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_21> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_22> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_23> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_24> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_25> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_26> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_27> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_28> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_29> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_30> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:2677 - Node <swi_mask_31> of sequential type is unconnected in block <wb_vic>.
WARNING:Xst:1710 - FF/Latch <rddata_reg_31> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_30> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_29> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_28> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_27> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_26> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_25> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_23> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_22> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_21> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_20> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_19> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_18> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_17> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_16> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_15> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_14> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_13> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_12> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_11> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_10> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_9> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_7> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_6> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_5> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_4> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_3> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_2> (without init value) has a constant value of 0 in block <dma_eic>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:1901 - Instance cmp_serdes_clk_pll in unit cmp_serdes_clk_pll of type PLL_BASE has been replaced by PLL_ADV
INFO:Xst:1901 - Instance U_BUFG_CLK1 in unit memc3_infrastructure of type BUFGCE has been replaced by BUFGMUX
INFO:Xst:1901 - Instance cmp_sys_clk_pll in unit cmp_sys_clk_pll of type PLL_BASE has been replaced by PLL_ADV
INFO:Xst:2261 - The FF/Latch <wb_sel_t_0> in Unit <wbmaster32> is equivalent to the following 3 FFs/Latches, which will be removed : <wb_sel_t_1> <wb_sel_t_2> <wb_sel_t_3> 
INFO:Xst:2261 - The FF/Latch <fmc_adc_core_trig_cfg_int_trig_sel_swb> in Unit <fmc_adc_100Ms_csr> is equivalent to the following 2 FFs/Latches, which will be removed : <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb> <fmc_adc_core_trig_cfg_int_trig_thres_swb> 
INFO:Xst:2261 - The FF/Latch <fmc_adc_core_trig_cfg_int_trig_sel_swb_s0> in Unit <fmc_adc_100Ms_csr> is equivalent to the following 2 FFs/Latches, which will be removed : <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s0> <fmc_adc_core_trig_cfg_int_trig_thres_swb_s0> 
INFO:Xst:2261 - The FF/Latch <rcb_gray_4> in Unit <inferred_async_fifo_5> is equivalent to the following FF/Latch, which will be removed : <rcb_bin_4> 
INFO:Xst:2261 - The FF/Latch <wcb_gray_4> in Unit <inferred_async_fifo_5> is equivalent to the following FF/Latch, which will be removed : <wcb_bin_4> 
INFO:Xst:2261 - The FF/Latch <data_offset_16> in Unit <offset_gain_s> is equivalent to the following FF/Latch, which will be removed : <data_offset_17> 
INFO:Xst:2261 - The FF/Latch <MCB_UIADDR_int_2> in Unit <mcb_soft_calibration> is equivalent to the following 2 FFs/Latches, which will be removed : <MCB_UIADDR_int_3> <MCB_UIADDR_int_4> 
INFO:Xst:2261 - The FF/Latch <fmc_adc_core_trig_cfg_int_trig_sel_swb_s1> in Unit <fmc_adc_100Ms_csr> is equivalent to the following 2 FFs/Latches, which will be removed : <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s1> <fmc_adc_core_trig_cfg_int_trig_thres_swb_s1> 
INFO:Xst:2261 - The FF/Latch <fmc_adc_core_trig_cfg_int_trig_sel_swb_s2> in Unit <fmc_adc_100Ms_csr> is equivalent to the following 2 FFs/Latches, which will be removed : <fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s2> <fmc_adc_core_trig_cfg_int_trig_thres_swb_s2> 
INFO:Xst:2261 - The FF/Latch <current_irq_1> in Unit <wb_vic> is equivalent to the following 3 FFs/Latches, which will be removed : <current_irq_2> <current_irq_3> <current_irq_4> 

Optimizing unit <serdes_n_to_1_s2_se_1> ...

Optimizing unit <adc_serdes> ...

Optimizing unit <spec_top_fmc_adc_100Ms> ...

Optimizing unit <carrier_csr> ...

Optimizing unit <gn4124_core> ...

Optimizing unit <p2l_des> ...

Optimizing unit <serdes_1_to_n_data_s2_se_1> ...

Optimizing unit <serdes_1_to_n_data_s2_se_2> ...

Optimizing unit <dma_controller> ...

Optimizing unit <dma_controller_wb_slave> ...

Optimizing unit <wbmaster32> ...

Optimizing unit <inferred_async_fifo_1> ...

Optimizing unit <inferred_async_fifo_2> ...

Optimizing unit <l2p_dma_master> ...

Optimizing unit <inferred_async_fifo_3> ...

Optimizing unit <p2l_dma_master> ...

Optimizing unit <inferred_async_fifo_4> ...

Optimizing unit <serdes_1_to_n_clk_pll_s2_diff> ...

Optimizing unit <pulse_synchronizer> ...

Optimizing unit <p2l_decode32> ...

Optimizing unit <l2p_arbiter> ...

Optimizing unit <xwb_register_link> ...

Optimizing unit <fmc_adc_100Ms_core> ...

Optimizing unit <fmc_adc_100Ms_csr> ...

Optimizing unit <gc_frequency_meter> ...

Optimizing unit <gc_pulse_synchronizer> ...

Optimizing unit <inferred_async_fifo_5> ...

Optimizing unit <inferred_sync_fifo> ...

Optimizing unit <gc_dyn_glitch_filt> ...

Optimizing unit <offset_gain_s> ...

Optimizing unit <ext_pulse_sync> ...

Optimizing unit <xwb_crossbar_2> ...

Optimizing unit <i2c_master_top> ...

Optimizing unit <i2c_master_byte_ctrl> ...

Optimizing unit <i2c_master_bit_ctrl> ...

Optimizing unit <spi_top> ...

Optimizing unit <spi_shift> ...

Optimizing unit <spi_clgen> ...

Optimizing unit <wb_onewire_master> ...

Optimizing unit <sockit_owm> ...

Optimizing unit <fmc_adc_eic> ...

Optimizing unit <wbgen2_eic> ...

Optimizing unit <timetag_core> ...

Optimizing unit <timetag_core_regs> ...

Optimizing unit <xwb_crossbar_1> ...

Optimizing unit <ddr3_ctrl_wb_1> ...

Optimizing unit <ddr3_ctrl_wb_2> ...

Optimizing unit <mcb_soft_calibration> ...
WARNING:Xst:1293 - FF/Latch <N_Term_s_1> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_s_2> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_s_3> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_s_4> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_s_5> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_s_6> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_0> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_1> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_2> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_3> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_4> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_5> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_6> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_0> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_1> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_2> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_3> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_4> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_5> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_w_0> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_w_1> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_w_2> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_w_3> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_w_4> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_w_5> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_w_6> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_w_0> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_w_1> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_w_2> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_w_3> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_w_4> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_w_5> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <N_Term_s_0> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_s_5> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_s_4> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_s_3> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_s_2> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_s_1> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <P_Term_s_0> has a constant value of 0 in block <mcb_soft_calibration>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <iodrp_controller> ...

Optimizing unit <iodrp_mcb_controller> ...

Optimizing unit <memc3_infrastructure> ...

Optimizing unit <gc_extend_pulse> ...

Optimizing unit <wb_vic> ...

Optimizing unit <wb_slave_vic> ...

Optimizing unit <dma_eic> ...
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/data_reg_7> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_controller_inst/data_reg_7> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_0> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_1> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_2> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_3> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_4> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_5> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_6> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_7> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/ce_data_0> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/inc_data_int> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/ce_data_inta> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_1> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/ce_data_0> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/inc_data_int> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/ce_data_inta> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_1> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/RZQ_IN_R1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/RZQ_IN_R2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_sint> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_15> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_14> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_13> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_12> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_11> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_10> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_9> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_8> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/cal_data_sint> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/cal_data_sint> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_len_o_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_len_o_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_load_o> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_31> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_30> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_27> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_25> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_24> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_23> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_22> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_21> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_20> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_19> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_18> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_17> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_16> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_15> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_14> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_13> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_12> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_11> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_10> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_9> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_8> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_31> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_30> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_27> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_25> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_24> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_23> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_22> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_21> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_20> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_19> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_18> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_17> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_16> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_15> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_14> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_13> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_12> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_11> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_10> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_9> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_8> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_30> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_27> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_25> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_24> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_23> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_22> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_21> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_20> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_19> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_18> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_17> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_16> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_15> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_14> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_13> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_12> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/almost_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/almost_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/almost_empty_int> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_count_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_count_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_count_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_count_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_count_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_count_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_count_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rd_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/wr_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/almost_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/almost_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/almost_empty_int> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_count_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_count_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_count_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_count_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_count_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_count_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_count_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rd_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/wr_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_31> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_30> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_27> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/almost_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/almost_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/almost_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/almost_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/almost_empty_int> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_9> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_8> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/wr_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/wr_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/wr_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/rd_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/wr_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/almost_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/almost_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/almost_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/almost_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/almost_empty_int> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_9> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_8> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/wr_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/wr_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/wr_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/rd_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/U_Inferred_FIFO/wr_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_27> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/almost_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/almost_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/almost_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/almost_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/almost_empty_int> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_9> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_8> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/wr_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/wr_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/wr_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/rd_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/wr_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/l_dma_irq_sync[1].cmp_dma_irq_sync/s_gotit_sync_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/l_dma_irq_sync[1].cmp_dma_irq_sync/s_gotit_sync_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/l_dma_irq_sync[1].cmp_dma_irq_sync/s_gotit_sync_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/l_dma_irq_sync[1].cmp_dma_irq_sync/s_gotit_toggle> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/l_dma_irq_sync[0].cmp_dma_irq_sync/s_gotit_sync_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/l_dma_irq_sync[0].cmp_dma_irq_sync/s_gotit_sync_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/l_dma_irq_sync[0].cmp_dma_irq_sync/s_gotit_sync_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/l_dma_irq_sync[0].cmp_dma_irq_sync/s_gotit_toggle> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_last> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_stat_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_stat_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_9> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_8> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_31> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_30> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_27> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_25> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_24> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_23> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_22> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_21> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_20> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_19> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_18> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_17> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_16> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_15> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_14> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_13> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_slave_int> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_slave_err> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_slave_rty> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/almost_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/almost_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/almost_empty_int> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/rd_count_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/rd_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/rd_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/rd_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/rd_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wr_count_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wr_count_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wr_count_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wr_count_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/almost_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/rd_full_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wr_empty_x> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/almost_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/rd_full_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/wr_empty_xm> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/almost_full_int> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_sdb_crossbar/crossbar/virtual_ERR> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/U_Wrapped_I2C/Wrapped_I2C/wb_inta_o> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_i2c/U_Wrapped_I2C/Wrapped_I2C/wb_inta_o> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/wb_int_o> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_ack_o> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_addr_d_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_addr_d_25> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_63> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_62> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_61> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_60> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_59> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_58> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_57> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_56> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_55> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_54> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_53> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_52> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_51> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_50> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_49> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_48> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_47> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_46> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_45> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_44> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_43> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_42> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_41> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_40> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_39> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_38> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_37> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_36> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_35> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_34> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_33> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_32> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_31> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_30> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_27> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_25> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_24> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_23> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_22> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_21> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_20> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_19> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_18> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_17> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_16> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_15> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_14> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_13> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_12> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_11> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_10> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_9> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_8> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_29> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_28> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_addr_d_27> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_addr_d_26> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/read_data_7> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/read_data_6> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/read_data_5> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/read_data_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/read_data_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/read_data_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/read_data_1> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/iodrp_mcb_controller_inst/read_data_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_4> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_3> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_2> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_0> of sequential type is unconnected in block <spec_top_fmc_adc_100Ms>.
WARNING:Xst:1293 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd3> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd2> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/rst_data> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/state_FSM_FFd3> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/state_FSM_FFd2> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/rst_data> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/state_FSM_FFd3> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/state_FSM_FFd2> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/rst_data> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_acq_led_monostable/s_monostable_cnt_24> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_led_monostable/s_monostable_cnt_24> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_monostable_cnt_1> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_monostable_cnt_0> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_trig_sync/s_pulse_length_cnt_1> has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIDRPUPDATE> has a constant value of 1 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_vic/U_Wrapped_VIC/current_irq_1> (without init value) has a constant value of 0 in block <spec_top_fmc_adc_100Ms>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_0> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_0> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_0> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_1> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_1> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_1> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_2> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_2> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_2> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_3> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_3> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_3> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_4> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_4> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_4> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/state_FSM_FFd4> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/state_FSM_FFd4> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_5> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_5> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_5> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_6> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_6> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_6> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_7> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_7> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_7> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_8> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/counter_8> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/counter_8> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/cal_data_master> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/cal_data_master> 
INFO:Xst:2261 - The FF/Latch <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_sel_3> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_sel_2> <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_sel_1> <cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_sel_0> 
INFO:Xst:2261 - The FF/Latch <cmp_fmc_adc_mezzanine_0/cmp_fmc0_eic/ack_sreg> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_fmc_adc_mezzanine_0/cmp_fmc0_eic/ack_in_progress> 
INFO:Xst:2261 - The FF/Latch <cmp_vic/U_Wrapped_VIC/U_wb_controller/ack_sreg> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_vic/U_Wrapped_VIC/U_wb_controller/ack_in_progress> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/enable> <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/enable> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state_FSM_FFd2> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_gn4124_core/cmp_p2l_dma_master/pdm_arb_dframe_o> 
INFO:Xst:2261 - The FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/IODRPCTRLR_MEMCELL_ADDR_1> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_CMD_VALID> 
INFO:Xst:2261 - The FF/Latch <cmp_carrier_csr/ack_in_progress> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_carrier_csr/ack_sreg> 
INFO:Xst:2261 - The FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_d> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_d> 
INFO:Xst:2261 - The FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_d> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_en> 
INFO:Xst:2261 - The FF/Latch <cmp_dma_eic/ack_sreg> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_dma_eic/ack_in_progress> 
INFO:Xst:2261 - The FF/Latch <cmp_gn4124_core/cmp_clk_in/cal_clk> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_gn4124_core/cmp_clk_in/state_FSM_FFd7> 
INFO:Xst:2261 - The FF/Latch <cmp_fmc_adc_mezzanine_0/cmp_timetag_core/cmp_timetag_core_regs/ack_sreg> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_fmc_adc_mezzanine_0/cmp_timetag_core/cmp_timetag_core_regs/ack_in_progress> 
INFO:Xst:2261 - The FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_3> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_2> <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_1> <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_0> 
INFO:Xst:2261 - The FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIADDR_int_2> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/MCB_UIADDR_int_0> 

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/rst_n> in Unit <spec_top_fmc_adc_100Ms> is equivalent to the following FF/Latch, which will be removed : <cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/rst_n> 
Found area constraint ratio of 100 (+ 5) on block spec_top_fmc_adc_100Ms, actual ratio is 43.
FlipFlop cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_11 has been replicated 1 time(s)
FlipFlop cmp_fmc_adc_mezzanine_0/cmp_sdb_crossbar/crossbar/matrix_old_0_3 has been replicated 1 time(s)
FlipFlop cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_2 has been replicated 1 time(s)
FlipFlop cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_3 has been replicated 1 time(s)
FlipFlop cmp_fmc_adc_mezzanine_0/cmp_xwb_reg/r_master_adr_4 has been replicated 1 time(s)

Final Macro Processing ...

Processing Unit <spec_top_fmc_adc_100Ms> :
	Found 2-bit shift register for signal <cmp_gn4124_core/l_dma_irq_sync[1].cmp_dma_irq_sync/s_input_sync_1>.
	Found 2-bit shift register for signal <cmp_gn4124_core/l_dma_irq_sync[0].cmp_dma_irq_sync/s_input_sync_1>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_63>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_62>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_61>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_60>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_59>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_58>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_57>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_56>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_55>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_54>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_53>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_52>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_51>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_50>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_49>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_48>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_47>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_46>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_45>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_44>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_43>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_42>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_41>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_40>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_39>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_38>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_37>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_36>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_35>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_34>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_33>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_32>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_31>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_30>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_29>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_28>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_27>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_26>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_25>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_24>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_23>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_22>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_21>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_20>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_19>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_18>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_17>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_16>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_15>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_14>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_13>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_12>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_11>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_10>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_9>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_8>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_7>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_6>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_5>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_4>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_3>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_2>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_1>.
	Found 4-bit shift register for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d_3_0>.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <cmp_fmc_adc_mezzanine_0/spi_din_t_3> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/bitslip_sreg_1> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <spec_top_fmc_adc_100Ms> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 6691
 Flip-Flops                                            : 6691
# Shift Registers                                      : 66
 2-bit shift register                                  : 2
 4-bit shift register                                  : 64

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : spec_top_fmc_adc_100Ms.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 9569
#      GND                         : 1
#      INV                         : 335
#      LUT1                        : 394
#      LUT2                        : 768
#      LUT3                        : 1019
#      LUT4                        : 895
#      LUT5                        : 990
#      LUT6                        : 2181
#      MULT_AND                    : 14
#      MUXCY                       : 1490
#      MUXF7                       : 51
#      VCC                         : 1
#      XORCY                       : 1430
# FlipFlops/Latches                : 6824
#      FD                          : 299
#      FDC                         : 1050
#      FDCE                        : 3872
#      FDE                         : 313
#      FDP                         : 67
#      FDPE                        : 55
#      FDR                         : 680
#      FDRE                        : 484
#      FDS                         : 4
# RAMS                             : 30
#      RAMB16BWER                  : 23
#      RAMB8BWER                   : 7
# Shift Registers                  : 66
#      SRLC16E                     : 66
# Clock Buffers                    : 7
#      BUFG                        : 6
#      BUFGMUX                     : 1
# IO Buffers                       : 174
#      BUFIO2                      : 2
#      IBUF                        : 31
#      IBUFDS                      : 13
#      IBUFG                       : 1
#      IOBUF                       : 23
#      IOBUFDS                     : 2
#      OBUF                        : 74
#      OBUFDS                      : 1
#      OBUFT                       : 26
#      OBUFTDS                     : 1
# DSPs                             : 4
#      DSP48A1                     : 4
# Others                           : 160
#      BUFIO2FB                    : 2
#      BUFPLL                      : 2
#      BUFPLL_MCB                  : 1
#      IODELAY2                    : 20
#      IODRP2                      : 1
#      IODRP2_MCB                  : 22
#      ISERDES2                    : 38
#      MCB                         : 1
#      OSERDES2                    : 65
#      PLL_ADV                     : 4
#      PULLDOWN                    : 2
#      PULLUP                      : 2

Device utilization summary:
---------------------------

Selected Device : 6slx45tfgg484-3 


Slice Logic Utilization: 
 Number of Slice Registers:            6824  out of  54576    12%  
 Number of Slice LUTs:                 6648  out of  27288    24%  
    Number used as Logic:              6582  out of  27288    24%  
    Number used as Memory:               66  out of   6408     1%  
       Number used as SRL:               66

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   9706
   Number with an unused Flip Flop:    2882  out of   9706    29%  
   Number with an unused LUT:          3058  out of   9706    31%  
   Number of fully used LUT-FF pairs:  3766  out of   9706    38%  
   Number of unique control sets:       258

IO Utilization: 
 Number of IOs:                         195
 Number of bonded IOBs:                 189  out of    296    63%  

Specific Feature Utilization:
 Number of Block RAM/FIFO:               27  out of    116    23%  
    Number using Block RAM only:         27
 Number of BUFG/BUFGCTRLs:                7  out of     16    43%  
 Number of DSP48A1s:                      4  out of     58     6%  
 Number of PLL_ADVs:                      4  out of      4   100%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
---------------------------------------------------------------------------------------------------------------------+------------------------+-------+
Clock Signal                                                                                                         | Clock buffer(FF name)  | Load  |
---------------------------------------------------------------------------------------------------------------------+------------------------+-------+
cmp_sys_clk_pll/CLKOUT0                                                                                              | BUFG                   | 3566  |
cmp_gn4124_core/cmp_clk_in/ddly_s                                                                                    | PLL_ADV:CLKOUT2        | 2266  |
cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1                                            | BUFG                   | 878   |
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in| BUFGMUX                | 197   |
cmp_sys_clk_pll/CLKOUT2                                                                                              | PLL_ADV:CLKOUT2        | 26    |
---------------------------------------------------------------------------------------------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 9.408ns (Maximum Frequency: 106.291MHz)
   Minimum input arrival time before clock: 4.523ns
   Maximum output required time after clock: 6.782ns
   Maximum combinational path delay: 4.832ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'cmp_sys_clk_pll/CLKOUT0'
  Clock period: 8.716ns (frequency: 114.732MHz)
  Total number of paths / destination ports: 392533 / 9191
-------------------------------------------------------------------------
Delay:               8.716ns (Levels of Logic = 9)
  Source:            cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_9 (FF)
  Destination:       cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_0 (FF)
  Source Clock:      cmp_sys_clk_pll/CLKOUT0 rising
  Destination Clock: cmp_sys_clk_pll/CLKOUT0 rising

  Data Path: cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_9 to cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            15   0.447   1.086  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_9 (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/ctrl_9)
     LUT2:I0->O            2   0.203   0.617  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_cnt[7]_cnt[7]_mux_7_OUT_rs_cy<0>11 (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_cnt[7]_cnt[7]_mux_7_OUT_rs_cy<0>)
     LUT6:I5->O            1   0.205   0.580  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_B51 (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_B<4>)
     LUT6:I5->O            1   0.205   0.000  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_lut<4> (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_lut<4>)
     MUXCY:S->O            1   0.172   0.000  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<4> (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_cy<4>)
     XORCY:CI->O         130   0.180   2.320  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos_rs_Madd_xor<5> (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos<5>)
     LUT6:I0->O            1   0.203   0.000  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_3 (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_3)
     MUXF7:I1->O           7   0.140   0.774  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/Mmux_rx_bit_pos[6]_data[127]_Mux_20_o_2_f7 (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_bit_pos[6]_data[127]_Mux_20_o)
     LUT5:I4->O           19   0.205   1.072  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk1 (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/rx_clk_mmx_out)
     LUT6:I5->O            1   0.205   0.000  cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_0_rstpot (cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_0_rstpot)
     FDC:D                     0.102          cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/data_0
    ----------------------------------------
    Total                      8.716ns (2.267ns logic, 6.449ns route)
                                       (26.0% logic, 74.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cmp_gn4124_core/cmp_clk_in/ddly_s'
  Clock period: 6.733ns (frequency: 148.512MHz)
  Total number of paths / destination ports: 31731 / 5962
-------------------------------------------------------------------------
Delay:               6.733ns (Levels of Logic = 6)
  Source:            cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/wcb_bin_1 (FF)
  Destination:       cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/full_int (FF)
  Source Clock:      cmp_gn4124_core/cmp_clk_in/ddly_s rising +90
  Destination Clock: cmp_gn4124_core/cmp_clk_in/ddly_s rising +90

  Data Path: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/wcb_bin_1 to cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/full_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            14   0.447   1.186  cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/wcb_bin_1 (cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/wcb_bin_1)
     LUT5:I2->O            8   0.205   1.031  cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mxor_wcb_gray_next<8:0>_5_xo<0>11 (cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mxor_wcb_gray_next<8:0>_5_xo<0>1)
     LUT5:I2->O            1   0.205   0.827  cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full18111 (cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full1811)
     LUT6:I2->O            3   0.203   0.651  cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full183 (cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full18)
     LUT5:I4->O            1   0.205   0.684  cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full12 (cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full11)
     LUT6:I4->O            1   0.203   0.580  cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full13 (cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full12)
     LUT6:I5->O            1   0.205   0.000  cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/Mmux_going_full15 (cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/going_full)
     FDC:D                     0.102          cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/full_int
    ----------------------------------------
    Total                      6.733ns (1.775ns logic, 4.958ns route)
                                       (26.4% logic, 73.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1'
  Clock period: 9.408ns (frequency: 106.291MHz)
  Total number of paths / destination ports: 52763 / 1048
-------------------------------------------------------------------------
Delay:               9.408ns (Levels of Logic = 1)
  Source:            cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_16 (FF)
  Destination:       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_16 (FF)
  Source Clock:      cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1 rising
  Destination Clock: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1 rising

  Data Path: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_16 to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/product_16
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.447   0.616  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_16 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/data_offset_16)
     DSP48A1:B16               4.300          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr[3].cmp_offset_gain_calibr/cmp_multiplier/st.DSP48E_3
    ----------------------------------------
    Total                      5.363ns (4.747ns logic, 0.616ns route)
                                       (88.5% logic, 11.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in'
  Clock period: 7.400ns (frequency: 135.140MHz)
  Total number of paths / destination ports: 10344 / 473
-------------------------------------------------------------------------
Delay:               7.400ns (Levels of Logic = 8)
  Source:            cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_0 (FF)
  Destination:       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5 (FF)
  Source Clock:      cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in rising
  Destination Clock: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in rising

  Data Path: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_0 to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   0.447   0.981  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_0 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/TARGET_DQS_DELAY_0)
     LUT6:I0->O            1   0.203   0.580  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag3 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag1)
     LUT3:I2->O            1   0.205   0.580  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag11)
     LUT5:I4->O            2   0.205   0.617  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag12 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag2)
     LUT4:I3->O            5   0.205   0.715  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag21 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Inc_Flag)
     LUT5:I4->O            1   0.205   0.580  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In1 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In1)
     LUT6:I5->O            1   0.205   0.580  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In2 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In2)
     LUT6:I5->O            1   0.205   0.580  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In3 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In3)
     LUT3:I2->O            1   0.205   0.000  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In7 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5-In)
     FDR:D                     0.102          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/STATE_FSM_FFd5
    ----------------------------------------
    Total                      7.400ns (2.187ns logic, 5.213ns route)
                                       (29.6% logic, 70.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cmp_sys_clk_pll/CLKOUT2'
  Clock period: 0.357ns (frequency: 2803.525MHz)
  Total number of paths / destination ports: 49 / 49
-------------------------------------------------------------------------
Delay:               2.854ns (Levels of Logic = 1)
  Source:            cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/syn_clk0_powerup_pll_locked (FF)
  Destination:       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/rst0_sync_r_24 (FF)
  Source Clock:      cmp_sys_clk_pll/CLKOUT2 rising 0.1X
  Destination Clock: cmp_sys_clk_pll/CLKOUT2 rising 0.1X

  Data Path: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/syn_clk0_powerup_pll_locked to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/rst0_sync_r_24
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.447   0.580  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/syn_clk0_powerup_pll_locked (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/syn_clk0_powerup_pll_locked)
     LUT3:I2->O           25   0.205   1.192  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/rst_tmp1 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/rst_tmp)
     FDP:PRE                   0.430          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/rst0_sync_r_0
    ----------------------------------------
    Total                      2.854ns (1.082ns logic, 1.772ns route)
                                       (37.9% logic, 62.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cmp_sys_clk_pll/CLKOUT0'
  Total number of paths / destination ports: 431 / 126
-------------------------------------------------------------------------
Offset:              4.523ns (Levels of Logic = 5)
  Source:            cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/bufpll_inst:LOCK (PAD)
  Destination:       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/rddata_reg_3 (FF)
  Destination Clock: cmp_sys_clk_pll/CLKOUT0 rising

  Data Path: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/bufpll_inst:LOCK to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/rddata_reg_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BUFPLL:LOCK            5   0.000   1.079  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/bufpll_inst (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/locked_out)
     LUT6:I0->O            1   0.203   0.580  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT1175 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT1174)
     LUT6:I5->O            1   0.205   0.580  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT1178 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT1177)
     LUT6:I5->O            1   0.205   0.580  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT11711 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT11710)
     LUT6:I5->O            1   0.205   0.580  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT11714 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT11713)
     LUT4:I3->O            1   0.205   0.000  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/Mmux_rddata_reg[31]_rddata_reg[31]_mux_123_OUT11718 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/rddata_reg[31]_rddata_reg[31]_mux_123_OUT<3>)
     FDCE:D                    0.102          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/rddata_reg_3
    ----------------------------------------
    Total                      4.523ns (1.125ns logic, 3.398ns route)
                                       (24.9% logic, 75.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cmp_gn4124_core/cmp_clk_in/ddly_s'
  Total number of paths / destination ports: 62 / 62
-------------------------------------------------------------------------
Offset:              2.447ns (Levels of Logic = 1)
  Source:            cmp_gn4124_core/cmp_clk_in/rx_bufpll_inst:LOCK (PAD)
  Destination:       cmp_gn4124_core/cmp_clk_in/state_FSM_FFd5 (FF)
  Destination Clock: cmp_gn4124_core/cmp_clk_in/ddly_s rising +90

  Data Path: cmp_gn4124_core/cmp_clk_in/rx_bufpll_inst:LOCK to cmp_gn4124_core/cmp_clk_in/state_FSM_FFd5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BUFPLL:LOCK            2   0.000   0.721  cmp_gn4124_core/cmp_clk_in/rx_bufpll_inst (cmp_gn4124_core/cmp_clk_in/rx_bufplllckd)
     LUT2:I0->O           20   0.203   1.092  cmp_gn4124_core/cmp_clk_in/not_rx_bufpll_lckd1 (cmp_gn4124_core/cmp_clk_in/not_rx_bufpll_lckd)
     FDP:PRE                   0.430          cmp_gn4124_core/cmp_clk_in/busyd
    ----------------------------------------
    Total                      2.447ns (0.633ns logic, 1.813ns route)
                                       (25.9% logic, 74.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1'
  Total number of paths / destination ports: 1783 / 616
-------------------------------------------------------------------------
Offset:              3.664ns (Levels of Logic = 1)
  Source:            cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/bufpll_inst:LOCK (PAD)
  Destination:       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay_cnt_31 (FF)
  Destination Clock: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1 rising

  Data Path: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/bufpll_inst:LOCK to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay_cnt_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BUFPLL:LOCK            5   0.000   0.943  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/bufpll_inst (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/locked_out)
     LUT3:I0->O          491   0.205   2.086  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_rst_n_inv431 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/rst_n_i_inv)
     FDC:CLR                   0.430          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/full_int
    ----------------------------------------
    Total                      3.664ns (0.635ns logic, 3.029ns route)
                                       (17.3% logic, 82.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in'
  Total number of paths / destination ports: 80 / 78
-------------------------------------------------------------------------
Offset:              4.158ns (Levels of Logic = 2)
  Source:            cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/BUFPLL_MCB_INST:LOCK (PAD)
  Destination:       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg (FF)
  Destination Clock: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in rising

  Data Path: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/BUFPLL_MCB_INST:LOCK to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BUFPLL_MCB:LOCK        8   0.000   0.907  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/BUFPLL_MCB_INST (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock)
     LUT6:I4->O           78   0.203   1.837  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst)
     LUT2:I0->O            1   0.203   0.579  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/non_violating_rst1 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/non_violating_rst)
     FDP:PRE                   0.430          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/RST_reg
    ----------------------------------------
    Total                      4.158ns (0.836ns logic, 3.322ns route)
                                       (20.1% logic, 79.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cmp_sys_clk_pll/CLKOUT2'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.124ns (Levels of Logic = 0)
  Source:            cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/BUFPLL_MCB_INST:LOCK (PAD)
  Destination:       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/syn_clk0_powerup_pll_locked (FF)
  Destination Clock: cmp_sys_clk_pll/CLKOUT2 rising 0.1X

  Data Path: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/BUFPLL_MCB_INST:LOCK to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/syn_clk0_powerup_pll_locked
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BUFPLL_MCB:LOCK        8   0.000   0.802  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/BUFPLL_MCB_INST (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock)
     FDCE:CE                   0.322          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/syn_clk0_powerup_pll_locked
    ----------------------------------------
    Total                      1.124ns (0.322ns logic, 0.802ns route)
                                       (28.7% logic, 71.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cmp_sys_clk_pll/CLKOUT0'
  Total number of paths / destination ports: 373 / 288
-------------------------------------------------------------------------
Offset:              6.782ns (Levels of Logic = 2)
  Source:            cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 (RAM)
  Destination:       aux_leds_o<1> (PAD)
  Source Clock:      cmp_sys_clk_pll/CLKOUT0 rising

  Data Path: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 to aux_leds_o<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB8BWER:CLKBRDCLK->DOBDO12   28   1.850   1.579  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/U_Inferred_FIFO/Mram_mem2 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout<64>)
     LUT6:I1->O            1   0.203   0.579  aux_leds_o<1>1 (aux_leds_o_1_OBUF)
     OBUF:I->O                 2.571          aux_leds_o_1_OBUF (aux_leds_o<1>)
    ----------------------------------------
    Total                      6.782ns (4.624ns logic, 2.158ns route)
                                       (68.2% logic, 31.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cmp_gn4124_core/cmp_clk_in/ddly_s'
  Total number of paths / destination ports: 96 / 96
-------------------------------------------------------------------------
Offset:              4.510ns (Levels of Logic = 1)
  Source:            cmp_gn4124_core/rst_reg (FF)
  Destination:       cmp_gn4124_core/cmp_l2p_ser/cmp_dframe_out/loop0[0].loop3.oserdes_m:RST (PAD)
  Source Clock:      cmp_gn4124_core/cmp_clk_in/ddly_s rising +90

  Data Path: cmp_gn4124_core/rst_reg to cmp_gn4124_core/cmp_l2p_ser/cmp_dframe_out/loop0[0].loop3.oserdes_m:RST
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            26   0.447   1.206  cmp_gn4124_core/rst_reg (cmp_gn4124_core/rst_reg)
     INV:I->O           2853   0.206   2.651  cmp_gn4124_core/cmp_l2p_ser/rst1_INV_0 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rst_n_i_inv)
    OSERDES2:RST               0.000          cmp_gn4124_core/cmp_l2p_ser/cmp_clk_out/loop0[0].loop3.oserdes_m
    ----------------------------------------
    Total                      4.510ns (0.653ns logic, 3.857ns route)
                                       (14.5% logic, 85.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in'
  Total number of paths / destination ports: 161 / 65
-------------------------------------------------------------------------
Offset:              3.486ns (Levels of Logic = 2)
  Source:            cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/normal_operation_window (FF)
  Destination:       cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/IODRP2_RZQ:T (PAD)
  Source Clock:      cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in rising

  Data Path: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/normal_operation_window to cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/IODRP2_RZQ:T
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.447   0.898  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/normal_operation_window (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/normal_operation_window)
     LUT6:I2->O           78   0.203   1.732  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst1 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/int_sys_rst)
     INV:I->O              0   0.206   0.000  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/RZQ_ZIO_ODATAIN1_INV_0 (cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/RZQ_ZIO_ODATAIN)
    IODRP2:ODATAIN             0.000          cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/IODRP2_RZQ
    ----------------------------------------
    Total                      3.486ns (0.856ns logic, 2.630ns route)
                                       (24.6% logic, 75.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1'
  Total number of paths / destination ports: 36 / 18
-------------------------------------------------------------------------
Offset:              2.383ns (Levels of Logic = 1)
  Source:            cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip (FF)
  Destination:       cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave:BITSLIP (PAD)
  Source Clock:      cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1 rising

  Data Path: cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip to cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[8].iserdes2_slave:BITSLIP
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.447   0.684  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip)
     LUT2:I0->O           18   0.203   1.049  cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_bitslip1 (cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_bitslip)
    ISERDES2:BITSLIP           0.000          cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/pins[0].iserdes2_master
    ----------------------------------------
    Total                      2.383ns (0.650ns logic, 1.733ns route)
                                       (27.3% logic, 72.7% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1007 / 945
-------------------------------------------------------------------------
Delay:               4.832ns (Levels of Logic = 2)
  Source:            cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0:P1WREMPTY (PAD)
  Destination:       aux_leds_o<2> (PAD)

  Data Path: cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0:P1WREMPTY to aux_leds_o<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    MCB:P1WREMPTY         29   0.000   1.478  cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (ddr_wr_fifo_empty)
     LUT4:I1->O            1   0.205   0.579  aux_leds_o<2>1 (aux_leds_o_2_OBUF)
     OBUF:I->O                 2.571          aux_leds_o_2_OBUF (aux_leds_o<2>)
    ----------------------------------------
    Total                      4.832ns (2.776ns logic, 2.056ns route)
                                       (57.4% logic, 42.6% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in
---------------------------------------------------------------------------------------------------------------------+---------+---------+---------+---------+
                                                                                                                     | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                                                                                                         |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------------------------------------------------------------------------------------------------+---------+---------+---------+---------+
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in|    7.400|         |         |         |
cmp_sys_clk_pll/CLKOUT0                                                                                              |    6.134|         |         |         |
---------------------------------------------------------------------------------------------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1
-------------------------------------------------------------------------+---------+---------+---------+---------+
                                                                         | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                                                             |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-------------------------------------------------------------------------+---------+---------+---------+---------+
cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1|    9.408|         |         |         |
cmp_sys_clk_pll/CLKOUT0                                                  |    8.288|         |         |         |
-------------------------------------------------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock cmp_gn4124_core/cmp_clk_in/ddly_s
---------------------------------+---------+---------+---------+---------+
                                 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                     |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------------+---------+---------+---------+---------+
cmp_gn4124_core/cmp_clk_in/ddly_s|    6.733|         |         |         |
cmp_sys_clk_pll/CLKOUT0          |    5.221|         |         |         |
---------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock cmp_sys_clk_pll/CLKOUT0
---------------------------------------------------------------------------------------------------------------------+---------+---------+---------+---------+
                                                                                                                     | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                                                                                                         |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------------------------------------------------------------------------------------------------+---------+---------+---------+---------+
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/mcb_drp_clk_bufg_in|    1.334|         |         |         |
cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_serdes_clk_pll/CLKOUT1                                            |    3.923|         |         |         |
cmp_gn4124_core/cmp_clk_in/ddly_s                                                                                    |    4.940|         |         |         |
cmp_sys_clk_pll/CLKOUT0                                                                                              |    8.716|         |         |         |
---------------------------------------------------------------------------------------------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock cmp_sys_clk_pll/CLKOUT2
-----------------------+---------+---------+---------+---------+
                       | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock           |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------------+---------+---------+---------+---------+
cmp_sys_clk_pll/CLKOUT0|    5.619|         |         |         |
cmp_sys_clk_pll/CLKOUT2|    2.854|         |         |         |
-----------------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 84.00 secs
Total CPU time to Xst completion: 81.85 secs
 
--> 


Total memory usage is 243140 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings : 1650 (   0 filtered)
Number of infos    :  363 (   0 filtered)

