peripheral {
  name = "FMC ADC 100MS/s core registers";
  description = "Wishbone slave for FMC ADC 100MS/s core";
  hdl_entity = "fmc_adc_100Ms_csr";

  prefix = "fmc_adc_core";

  reg {
    name = "Control register";
    prefix = "ctl";

    field {
      name = "State machine commands (ignore on read)";
      description = "1: ACQ_START (start acquisition, only when FSM is idle)\n2: ACQ_STOP (stop acquisition, anytime)";
      prefix = "fsm_cmd";
      type = PASS_THROUGH;
      size = 2;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "FMC Si750 output enable";
      prefix = "fmc_clk_oe";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "Offset DACs clear (active low)";
      prefix = "offset_dac_clr_n";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "Manual serdes bitslip (ignore on read)";
      prefix = "man_bitslip";
      type = MONOSTABLE;
      clock = "fs_clk_i"
    };

    field {
      name = "Enable test data";
      description = "Write the address counter value instead of ADC data to DDR";
      prefix = "test_data_en";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "Manual TRIG LED";
      description = "Manual control of the front panel TRIG LED";
      prefix = "trig_led";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "Manual ACQ LED";
      description = "Manual control of the front panel ACQ LED";
      prefix = "acq_led";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 24;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Status register";
    prefix = "sta";

    field {
      name = "State machine status";
      description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: TRIG_TAG\n6: DECR_SHOT\n7: illegal";
      prefix = "fsm";
      type = SLV;
      size = 3;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "SerDes PLL status";
      description = "Sampling clock recovery PLL.\n0: not locked\n1: locked";
      prefix = "serdes_pll";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "SerDes synchronization status";
      description = "0: bitslip in progress\n1: serdes synchronized";
      prefix = "serdes_synced";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "Acquisition configuration status";
      description = "0: Unauthorised acquisition configuration (will prevent acquisition to start)\n1: Valid acquisition configuration\n- Shot number > 0\n- Post-trigger sample > 0";
      prefix = "acq_cfg";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 26;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
]]
  };

  reg {
    name = "Trigger configuration";
    prefix = "trig_cfg";

    field {
      name = "Hardware trigger selection";
      description = "0: internal (data threshold)\n1: external (front panel trigger input)";
      prefix = "hw_trig_sel";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };

    field {
      name = "Hardware trigger polarity";
      description = "0: positive edge/slope\n1: negative edge/slope";
      prefix = "hw_trig_pol";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };

    field {
      name = "Hardware trigger enable";
      description = "0: disable\n1: enable";
      prefix = "hw_trig_en";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };

    field {
      name = "Software trigger enable";
      description = "0: disable\n1: enable";
      prefix = "sw_trig_en";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };

    field {
      name = "Channel selection for internal trigger";
      description = "00: channel 1\n01: channel 2\n10: channel 3\n11: channel 4";
      prefix = "int_trig_sel";
      type = SLV;
      size = 2;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };

    field {
      name = "Enable internal trigger test mode";
      description = "Test mode:\n  ch1 = Channel 1 input(analogue)\n ch2 = Channel input over threshold (digital)\n  ch3 = Channel input over threshold filtered (digital)\n  ch4 = Trigger (digital)";
      prefix = "int_trig_test_en";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };

    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "Internal trigger threshold glitch filter";
      description = "Configures the internal trigger threshold glitch filter length.";
      prefix = "int_trig_thres_filt";
      type = SLV;
      size = 8;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };

    field {
      name = "Threshold for internal trigger";
      description = "Treated as binary two's complement and compared to raw ADC data.";
      prefix = "int_trig_thres";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };
  };

  reg {
    name = "Trigger delay";
    prefix = "trig_dly";

    field {
      name = "Trigger delay value";
      description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
  };

  reg {
    name = "Software trigger";
    description = "Writing (anything) to this register generates a software trigger.";

    prefix = "sw_trig";
    field {
      name = "Software trigger (ignore on read)";
      type = PASS_THROUGH;
      size = 32;
      clock = "fs_clk_i";
    };
   };

  reg {
    name = "Number of shots";
    prefix = "shots";

    field {
      name = "Number of shots";
      description = "Number of shots required in multi-shot mode, set to one for single-shot mode.";
      prefix = "nb";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Remaining shots counter";
    prefix = "shots_cnt";

    field {
      name = "Remaining shots counter";
      description = "Counts the number of remaining shots to acquire.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Trigger address register";
    prefix = "trig_pos";

    field {
      name = "Trigger address";
      description = "Trigger address in DDR memory.\nOnly used in single-shot mode.";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
  };

  reg {
    name = "Sampling clock frequency";
    prefix = "fs_freq";

    field {
      name = "Sampling clock frequency";
      description = "ADC sampling clock frequency in Hz";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "fs_clk_i";
    };
  };

  reg {
    name = "Sample rate";
    prefix = "sr";

    field {
      name = "Sample rate decimation";
      description = "Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).";
      prefix = "deci";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
    };
  };

  reg {
    name = "Pre-trigger samples";
    prefix = "pre_samples";

    field {
      name = "Pre-trigger samples";
      description = "Number of requested pre-trigger samples (>1).";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
  };

  reg {
    name = "Post-trigger samples";
    prefix = "post_samples";

    field {
      name = "Post-trigger samples";
      description = "Number of requested post-trigger samples (>1).";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
  };

  reg {
    name = "Samples counter";
    prefix = "samples_cnt";

    field {
      name = "Samples counter";
      description = "Counts the number of samples.\n It is reset on START and then counts the number of pre-trigger + post-trigger samples";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
  };

  reg {
    name = "Channel 1 control register";
    prefix = "ch1_ctl";

    field {
      name = "Solid state relays control for channel 1";
      description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
      prefix = "ssr";
      type = SLV;
      size = 7;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 25;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 1 status register";
    prefix = "ch1_sta";

    field {
      name = "Channel 1 current ADC value";
      description = "Current ADC raw value. The format is binary two's complement.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "fs_clk_i";
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
]]
  };

  reg {
    name = "Channel 1 gain calibration register";
    prefix = "ch1_gain";

    field {
      name = "Gain calibration for channel 1";
      description = "Gain applied to all data coming from the ADC.\nFixed point format:\nBit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 1 offset calibration register";
    prefix = "ch1_offset";

    field {
      name = "Offset calibration for channel 1";
      description = "Offset applied to all data coming from the ADC. The format is binary two's complement.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 1 saturation register";
    prefix = "ch1_sat";

    field {
      name = "Saturation value for channel 1";
      description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
      prefix = "val";
      type = SLV;
      size = 15;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 17;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 2 control register";
    prefix = "ch2_ctl";

    field {
      name = "Solid state relays control for channel 2";
      description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
      prefix = "ssr";
      type = SLV;
      size = 7;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 25;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 2 status register";
    prefix = "ch2_sta";

    field {
      name = "Channel 2 current ACD value";
      description = "Current ADC raw value. The format is binary two's complement.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "fs_clk_i";
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
]]
  };

  reg {
    name = "Channel 2 gain calibration register";
    prefix = "ch2_gain";

    field {
      name = "Gain calibration for channel 2";
      description = "Gain applied to all data coming from the ADC.\nFixed point format:\nBit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 2 offset calibration register";
    prefix = "ch2_offset";

    field {
      name = "Offset calibration for channel 2";
      description = "Offset applied to all data coming from the ADC. The format is binary two's complement.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 2 saturation register";
    prefix = "ch2_sat";

    field {
      name = "Saturation value for channel 2";
      description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
      prefix = "val";
      type = SLV;
      size = 15;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 17;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 3 control register";
    prefix = "ch3_ctl";

    field {
      name = "Solid state relays control for channel 3";
      description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
      prefix = "ssr";
      type = SLV;
      size = 7;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 25;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 3 status register";
    prefix = "ch3_sta";

    field {
      name = "Channel 3 current ADC value";
      description = "Current ADC raw value. The format is binary two's complement.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "fs_clk_i";
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
]]
  };

  reg {
    name = "Channel 3 gain calibration register";
    prefix = "ch3_gain";

    field {
      name = "Gain calibration for channel 3";
      description = "Gain applied to all data coming from the ADC.\nFixed point format:\nBit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 3 offset calibration register";
    prefix = "ch3_offset";

    field {
      name = "Offset calibration for channel 3";
      description = "Offset applied to all data coming from the ADC. The format is binary two's complement.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 3 saturation register";
    prefix = "ch3_sat";

    field {
      name = "Saturation value for channel 3";
      description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
      prefix = "val";
      type = SLV;
      size = 15;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 17;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 4 control register";
    prefix = "ch4_ctl";

    field {
      name = "Solid state relays control for channel 4";
      description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
      prefix = "ssr";
      type = SLV;
      size = 7;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 25;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 4 status register";
    prefix = "ch4_sta";

    field {
      name = "Channel 4 current ADC value";
      description = "Current ADC raw value. The format is binary two's complement.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "fs_clk_i";
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
]]
  };

  reg {
    name = "Channel 4 gain calibration register";
    prefix = "ch4_gain";

    field {
      name = "Gain calibration for channel 4";
      description = "Gain applied to all data coming from the ADC.\nFixed point format:\nBit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 4 offset calibration register";
    prefix = "ch4_offset";

    field {
      name = "Offset calibration for channel 4";
      description = "Offset applied to all data coming from the ADC. The format is binary two's complement.";
      prefix = "val";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 16;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

  reg {
    name = "Channel 4 saturation register";
    prefix = "ch4_sat";

    field {
      name = "Saturation value for channel 4";
      description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
      prefix = "val";
      type = SLV;
      size = 15;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
--[[
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 17;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
]]
  };

};
