peripheral {
  name = "IRQ controller registers";
  description = "Wishbone slave for registers related to IRQ controller";
  hdl_entity = "irq_controller_regs";

  prefix = "irq_ctrl";

  reg {
    name = "Multiple interrupt register";
    description = "Multiple interrupts occurs before irq source is read.\nWrite '1' to clear a bit.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
    prefix = "multi_irq";

    field {
      name = "Multiple interrupt";
      type = SLV;
      size = 32;
      load = LOAD_EXT;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
    };
  };

  reg {
    name = "Interrupt sources register ";
    description = "Indicates the interrupt source.\nWrite '1' to clear a bit.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
    prefix = "src";

    field {
      name = "Interrupt sources";
      type = SLV;
      load = LOAD_EXT;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
    };
  };

  reg {
    name = "Interrupt enable mask register";
    description = "Bit mask to independently enable interrupt sources.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
    prefix = "en_mask";

    field {
      name = "Interrupt enable mask";
      type = SLV;
      size = 32;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
  };

};
