peripheral {
  name = "Carrier control and status registers";
  description = "Wishbone slave for control and status registers related to the FMC carrier";
  hdl_entity = "carrier_csr";

  prefix = "carrier_csr";

  reg {
    name = "Carrier type and PCB version";
    prefix = "carrier";

    field {
      name = "PCB revision";
      description = "Binary coded PCB layout revision.";
      prefix = "pcb_rev";
      type = SLV;
      size = 4;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "Reserved register";
      description = "Ignore on read, write with 0's.";
      prefix = "reserved";
      type = SLV;
      size = 12;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "Carrier type";
      description = "Carrier type identifier";
      prefix = "type";
      type = SLV;
      size = 16;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
  };

  reg {
    name = "Bitstream type";
    prefix = "bitstream_type";

    field {
      name = "Bitstream type";
      description = "Bitstream (firmware) type, unsigned 32-bit number.";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
  };

  reg {
    name = "Bitstream date";
    prefix = "bitstream_date";

    field {
      name = "Bitstream date";
      description = "Bitstream generation date, unsigned 32-bit UTC time.";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
  };

  reg {
    name = "Status";
    prefix = "stat";

    field {
      name = "FMC presence";
      description = "0: FMC slot is populated\n1: FMC slot is not populated.";
      prefix = "fmc_pres";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "GN4142 core P2L PLL status";
      description = "0: not locked\n1: locked.";
      prefix = "p2l_pll_lck";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "System clock PLL status";
      description = "0: not locked\n1: locked.";
      prefix = "sys_pll_lck";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "DDR3 calibration status";
      description = "0: not done\n1: done.";
      prefix = "ddr3_cal_done";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };

    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's.";
      prefix = "reserved";
      type = SLV;
      size = 28;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };
  };

  reg {
    name = "Control";
    prefix = "ctrl";

    field {
      name = "Green LED";
      description = "Front panel green LED control";
      prefix = "led_green";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "Red LED";
      description = "Front panel red LED control";
      prefix = "led_red";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "DAC clear";
      description = "Active low clear signal for VCXO DACs";
      prefix = "dac_clr_n";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
      size = 29;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
  };

--  ram {
--    name = "Release tag";
--    description = "256-byte ASCII area for text generated by versionning tool";
--    prefix = "rel_tag";
--    size = 64;
--    width = 32;
--    access_bus = READ_ONLY;
--    access_dev = WRITE_ONLY;
--    };

};
