carrier_csr

Carrier control and status registers

Wishbone slave for control and status registers related to the FMC carrier

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Carrier type and PCB version
3.2. Bitstream type
3.3. Bitstream date
3.4. Status
3.5. Control

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Carrier type and PCB version carrier_csr_carrier CARRIER
0x1 REG Bitstream type carrier_csr_bitstream_type BITSTREAM_TYPE
0x2 REG Bitstream date carrier_csr_bitstream_date BITSTREAM_DATE
0x3 REG Status carrier_csr_stat STAT
0x4 REG Control carrier_csr_ctrl CTRL

2. HDL symbol

rst_n_i Carrier type and PCB version:
wb_clk_i carrier_csr_carrier_pcb_rev_i[3:0]
wb_addr_i[2:0] carrier_csr_carrier_dummy_i[11:0]
wb_data_i[31:0] carrier_csr_carrier_type_i[15:0]
wb_data_o[31:0]  
wb_cyc_i Bitstream type:
wb_sel_i[3:0] carrier_csr_bitstream_type_i[31:0]
wb_stb_i  
wb_we_i Bitstream date:
wb_ack_o carrier_csr_bitstream_date_i[31:0]
 
Status:
carrier_csr_stat_fmc_pres_i
carrier_csr_stat_p2l_pll_lck_i
carrier_csr_stat_sys_pll_lck_i
carrier_csr_stat_ddr3_cal_done_i
 
Control:
carrier_csr_ctrl_led_green_o
carrier_csr_ctrl_led_red_o
carrier_csr_ctrl_dac_clr_n_o

3. Register description

3.1. Carrier type and PCB version

HW prefix: carrier_csr_carrier
HW address: 0x0
C prefix: CARRIER
C offset: 0x0
31 30 29 28 27 26 25 24
TYPE[15:8]
23 22 21 20 19 18 17 16
TYPE[7:0]
15 14 13 12 11 10 9 8
DUMMY[11:4]
7 6 5 4 3 2 1 0
DUMMY[3:0] PCB_REV[3:0]

3.2. Bitstream type

HW prefix: carrier_csr_bitstream_type
HW address: 0x1
C prefix: BITSTREAM_TYPE
C offset: 0x4
31 30 29 28 27 26 25 24
BITSTREAM_TYPE[31:24]
23 22 21 20 19 18 17 16
BITSTREAM_TYPE[23:16]
15 14 13 12 11 10 9 8
BITSTREAM_TYPE[15:8]
7 6 5 4 3 2 1 0
BITSTREAM_TYPE[7:0]

3.3. Bitstream date

HW prefix: carrier_csr_bitstream_date
HW address: 0x2
C prefix: BITSTREAM_DATE
C offset: 0x8
31 30 29 28 27 26 25 24
BITSTREAM_DATE[31:24]
23 22 21 20 19 18 17 16
BITSTREAM_DATE[23:16]
15 14 13 12 11 10 9 8
BITSTREAM_DATE[15:8]
7 6 5 4 3 2 1 0
BITSTREAM_DATE[7:0]

3.4. Status

HW prefix: carrier_csr_stat
HW address: 0x3
C prefix: STAT
C offset: 0xc
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - DDR3_CAL_DONE SYS_PLL_LCK P2L_PLL_LCK FMC_PRES

3.5. Control

HW prefix: carrier_csr_ctrl
HW address: 0x4
C prefix: CTRL
C offset: 0x10
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - DAC_CLR_N LED_RED LED_GREEN