Skip to content

F
FMC ADC 100M 14b 4cha - Gateware
Commit 053bd549 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

update and tighten top-level constraints

parent c220d570
Hide whitespace changes
Inline Side-by-side
Showing with 66 additions and 47 deletions
general-cores @ 28cd7560
Subproject commit 67d353adecea74d6a29e21919ff714da94fd8c76
Subproject commit 28cd756047ce9f85cf7c134367c7439f1189114d
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @ 053bd549
......@@ -395,26 +395,29 @@ INST "cmp_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FAL
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_ref;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_ref;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "cmp_xwrc_board_spec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "adc_dco_n_i" TNM_NET = adc_dco_n_i;
NET "adc_dco_p_i" TNM_NET = adc_dco;
NET "adc_dco_n_i" TNM_NET = adc_dco;
TIMESPEC TS_adc_dco_n_i = PERIOD "adc_dco_n_i" 2.5 ns HIGH 50%;
TIMESPEC TS_adc_dco = PERIOD "adc_dco" 2.5 ns HIGH 50%;
NET "gn_p2l_clk_p_i" TNM_NET = "p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
TIMESPEC TS_p2l_clk = PERIOD "p2l_clk" 5 ns HIGH 50%;
......@@ -460,49 +463,54 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk_333m;
NET "clk_ddr_333m" TNM_NET = ddr_clk;
NET "cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank_clk;
NET "cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
TIMEGRP "ddr_clk" = "ddr_clk_333m" "ddr_bank_clk";
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMEGRP "adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "adc_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
NET "*/gc_sync_register_in[*]" TNM = "sync_reg";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
#TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMEGRP "adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "adc_sync_reg" 10ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X30Y2;
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @ 053bd549
......@@ -592,29 +592,33 @@ INST "gen_fmc_mezzanine[*].*/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FA
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_ref;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_ref;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "cmp_xwrc_board_svec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "adc_dco_n_i[0]" TNM_NET = adc0_dco_n_i;
NET "adc_dco_p_i[0]" TNM_NET = adc0_dco;
NET "adc_dco_n_i[0]" TNM_NET = adc0_dco;
TIMESPEC TS_adc0_dco_n_i = PERIOD "adc0_dco_n_i" 2.5 ns HIGH 50%;
TIMESPEC TS_adc0_dco = PERIOD "adc0_dco" 2.5 ns HIGH 50%;
NET "adc_dco_n_i[1]" TNM_NET = adc1_dco_n_i;
NET "adc_dco_p_i[1]" TNM_NET = adc1_dco;
NET "adc_dco_n_i[1]" TNM_NET = adc1_dco;
TIMESPEC TS_adc1_dco_n_i = PERIOD "adc1_dco_n_i" 2.5 ns HIGH 50%;
TIMESPEC TS_adc1_dco = PERIOD "adc1_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
......@@ -654,19 +658,18 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk_333m;
NET "clk_ddr_333m" TNM_NET = ddr_clk;
NET "cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
NET "gen_ddr_ctrl[0].*/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank4_clk;
NET "gen_ddr_ctrl[1].*/*/memc5_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank5_clk;
NET "gen_ddr_ctrl[?].*/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "gen_ddr_ctrl[?].*/*/memc4_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
TIMEGRP "ddr_clk" = "ddr_clk_333m" "ddr_bank4_clk" "ddr_bank5_clk";
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
......@@ -677,25 +680,33 @@ TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk";
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
#TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk";
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 10ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0 ns;
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment