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FMC ADC 100M 14b 4cha - Gateware
Commit 07e7b7de authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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hdl: work in progress for WRPC integration

parent 549db126
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doc/manual/spec/carrier_csr.tex
View file @ 07e7b7de
......@@ -92,18 +92,12 @@ Red LED
@code{DAC_CLR_N}
@tab @code{0} @tab
DAC clear
@item @code{3}
@tab R/W @tab
@code{WRABBIT_EN}
@tab @code{0} @tab
White Rabbit enable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{led_green} @tab Manual control of the front panel green LED (unused in the fmc-adc application)
@item @code{led_red} @tab Manual control of the front panel red LED (unused in the fmc-adc application)
@item @code{dac_clr_n} @tab Active low clear signal for VCXO DACs
@item @code{wrabbit_en} @tab Enable White Rabbit features
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
......
doc/manual/svec/carrier_csr.tex
View file @ 07e7b7de
......@@ -88,16 +88,10 @@ DDR3 bank 5 calibration status
@code{FP_LEDS_MAN}
@tab @code{0} @tab
Front panel LED manual control
@item @code{16}
@tab R/W @tab
@code{WRABBIT_EN}
@tab @code{0} @tab
White Rabbit enable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@item @code{wrabbit_en} @tab Enable White Rabbit features
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
......
vme64x-core @ fa34d06e
Subproject commit b2fc3ce76485404f831d15f7ce31fdde08e234d5
Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
hdl/spec/rtl/carrier_csr.vhd
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jun 16 16:45:19 2016
-- Created : Mon Feb 26 15:24:45 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -40,27 +40,16 @@ architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_wrabbit_en_int : std_logic ;
signal carrier_csr_rst_fmc0_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -72,7 +61,6 @@ begin
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_wrabbit_en_int <= '0';
carrier_csr_rst_fmc0_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -136,12 +124,11 @@ begin
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_wrabbit_en_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(3) <= carrier_csr_ctrl_wrabbit_en_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -236,8 +223,6 @@ begin
regs_o.ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
regs_o.ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- White Rabbit enable
regs_o.ctrl_wrabbit_en_o <= carrier_csr_ctrl_wrabbit_en_int;
-- State of the reset line
regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
rwaddr_reg <= wb_adr_i;
......
hdl/spec/rtl/carrier_csr_wbgen2_pkg.vhd
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jun 16 16:45:19 2016
-- Created : Mon Feb 26 15:24:45 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -45,7 +45,6 @@ package carrier_csr_wbgen2_pkg is
ctrl_led_green_o : std_logic;
ctrl_led_red_o : std_logic;
ctrl_dac_clr_n_o : std_logic;
ctrl_wrabbit_en_o : std_logic;
rst_fmc0_o : std_logic;
end record;
......@@ -53,7 +52,6 @@ package carrier_csr_wbgen2_pkg is
ctrl_led_green_o => '0',
ctrl_led_red_o => '0',
ctrl_dac_clr_n_o => '0',
ctrl_wrabbit_en_o => '0',
rst_fmc0_o => '0'
);
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
......@@ -74,10 +72,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 07e7b7de
......@@ -602,10 +602,10 @@ INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
NET "ddr_clk_buf" TNM_NET = ddr_clk;
NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
#NET "ddr_clk_buf" TNM_NET = ddr_clk;
#NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
TIMESPEC TS_sys_to_drr_cross = FROM "sys_clk_62_5" TO "ddr_clk" 16ns DATAPATHONLY;
#TIMESPEC TS_sys_to_drr_cross = FROM "sys_clk_62_5" TO "ddr_clk" 16ns DATAPATHONLY;
#===============================================================================
# False Path
......
hdl/spec/wb_gen/carrier_csr.h
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Thu Jun 16 16:45:19 2016
* Created : Mon Feb 26 15:24:45 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -80,9 +80,6 @@
/* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: White Rabbit enable in reg: Control */
#define CARRIER_CSR_CTRL_WRABBIT_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */
......
hdl/spec/wb_gen/carrier_csr.htm
View file @ 07e7b7de
......@@ -390,23 +390,6 @@ carrier_csr_ctrl_dac_clr_n_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_wrabbit_en_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1229,8 +1212,8 @@ CTRL
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
WRABBIT_EN
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DAC_CLR_N
......@@ -1256,10 +1239,6 @@ LED_RED
DAC_CLR_N
</b>[<i>read/write</i>]: DAC clear
<br>Active low clear signal for VCXO DACs
<li><b>
WRABBIT_EN
</b>[<i>read/write</i>]: White Rabbit enable
<br>Enable White Rabbit features
</ul>
<a name="RST"></a>
<h3><a name="sect_3_4">3.4. Reset Register</a></h3>
......
hdl/spec/wb_gen/carrier_csr.wb
View file @ 07e7b7de
......@@ -112,15 +112,6 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "White Rabbit enable";
description = "Enable White Rabbit features";
prefix = "wrabbit_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
hdl/svec/rtl/carrier_csr.vhd
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jun 16 17:11:57 2016
-- Created : Fri Feb 23 15:39:10 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -38,28 +38,17 @@ end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal carrier_csr_ctrl_wrabbit_en_int : std_logic ;
signal carrier_csr_rst_fmc0_int : std_logic ;
signal carrier_csr_rst_fmc1_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -69,7 +58,6 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_ctrl_wrabbit_en_int <= '0';
carrier_csr_rst_fmc0_int <= '0';
carrier_csr_rst_fmc1_int <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -132,10 +120,9 @@ begin
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
carrier_csr_ctrl_wrabbit_en_int <= wrdata_reg(16);
end if;
rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
rddata_reg(16) <= carrier_csr_ctrl_wrabbit_en_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
......@@ -215,8 +202,6 @@ begin
-- DDR3 bank 5 calibration status
-- Front panel LED manual control
regs_o.ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- White Rabbit enable
regs_o.ctrl_wrabbit_en_o <= carrier_csr_ctrl_wrabbit_en_int;
-- State of the FMC 1 reset line
regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
-- State of the FMC 2 reset line
......
hdl/svec/rtl/carrier_csr_wbgen2_pkg.vhd
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jun 16 17:11:57 2016
-- Created : Fri Feb 23 15:39:10 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -45,14 +45,12 @@ package carrier_csr_wbgen2_pkg is
type t_carrier_csr_out_registers is record
ctrl_fp_leds_man_o : std_logic_vector(15 downto 0);
ctrl_wrabbit_en_o : std_logic;
rst_fmc0_o : std_logic;
rst_fmc1_o : std_logic;
end record;
constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
ctrl_fp_leds_man_o => (others => '0'),
ctrl_wrabbit_en_o => '0',
rst_fmc0_o => '0',
rst_fmc1_o => '0'
);
......@@ -74,10 +72,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ 07e7b7de
This diff is collapsed.
hdl/svec/svec_top_fmc_adc_100Ms.ucf
View file @ 07e7b7de
......@@ -24,14 +24,14 @@ NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[7]" LOC = R7;
NET "vme_irq_n_o[6]" LOC = AH2;
NET "vme_irq_n_o[5]" LOC = AF2;
NET "vme_irq_n_o[4]" LOC = N9;
NET "vme_irq_n_o[3]" LOC = N10;
NET "vme_irq_n_o[2]" LOC = AH4;
NET "vme_irq_n_o[1]" LOC = AG4;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
......@@ -125,14 +125,14 @@ NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
......@@ -429,6 +429,12 @@ NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
......@@ -437,21 +443,18 @@ NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_b" LOC = Y26;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_b" LOC = W24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
......@@ -948,24 +951,26 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
#NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
#TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# ADC
NET "adc0_dco_n_i" TNM_NET = adc0_dco_n_i;
TIMESPEC TS_adc0_dco_n_i = PERIOD "adc0_dco_n_i" 2 ns HIGH 50%;
NET "adc1_dco_n_i" TNM_NET = adc1_dco_n_i;
TIMESPEC TS_adc1_dco_n_i = PERIOD "adc1_dco_n_i" 2 ns HIGH 50%;
TIMESPEC TS_adc0_dco_n_i = PERIOD "adc0_dco_n_i" 2.5 ns HIGH 50%;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
#TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# external 10MHz clock input
NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
NET "clk_125m_pllref" TNM_NET = clk_125m_pllref;
NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
TIMESPEC TS_crossdomain_01 = FROM "clk_125m_pllref" TO "sys_clk_62_5" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_02 = FROM "sys_clk_62_5" TO "clk_125m_pllref" 4ns DATAPATHONLY;
NET "clk_ddr_333m_buf" TNM_NET = clk_ddr_333m;
NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
TIMESPEC TS_crossdomain_01 = FROM "clk_sys_62m5" TO "clk_ddr_333m" 4ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
#===============================================================================
# False Path
......@@ -990,5 +995,5 @@ NET "cmp_powerup_reset/master_rstn" TIG;
# Async reset inputs to reset synchroniser
NET "rst_n_i" TIG;
NET "sys_clk_pll_locked" TIG;
#NET "sys_clk_pll_locked" TIG;
NET "vme_sysreset_n_i" TIG;
hdl/svec/syn/Manifest.py
View file @ 07e7b7de
......@@ -16,12 +16,14 @@ modules = {
"local" : [
"../rtl",
"../../adc/rtl",
"../../ip_cores/wr-cores/board/svec",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
......
hdl/svec/wb_gen/carrier_csr.h
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Thu Jun 16 17:11:57 2016
* Created : Fri Feb 23 15:39:10 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -80,9 +80,6 @@
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: White Rabbit enable in reg: Control */
#define CARRIER_CSR_CTRL_WRABBIT_EN WBGEN2_GEN_MASK(16, 1)
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
......
hdl/svec/wb_gen/carrier_csr.htm
View file @ 07e7b7de
......@@ -373,23 +373,6 @@ carrier_csr_ctrl_fp_leds_man_o[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_wrabbit_en_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1134,8 +1117,8 @@ CTRL
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
WRABBIT_EN
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -1252,10 +1235,6 @@ FP_LEDS_MAN[7:0]
FP_LEDS_MAN
</b>[<i>read/write</i>]: Front panel LED manual control
<br>Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange
<li><b>
WRABBIT_EN
</b>[<i>read/write</i>]: White Rabbit enable
<br>Enable White Rabbit features
</ul>
<a name="RST"></a>
<h3><a name="sect_3_4">3.4. Reset Register</a></h3>
......
hdl/svec/wb_gen/carrier_csr.wb
View file @ 07e7b7de
......@@ -104,15 +104,6 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "White Rabbit enable";
description = "Enable White Rabbit features";
prefix = "wrabbit_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
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