Commit 08c8d3ae authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Add a software reset register to reset the mezzanine related cores.

parent ee8954d0
......@@ -13,6 +13,10 @@ Status
REG @tab
@code{ctrl} @tab
Control
@item @code{0xc} @tab
REG @tab
@code{rst} @tab
Reset Register
@end multitable
@regsection @code{carrier} - Carrier type and PCB version
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -107,3 +111,23 @@ Reserved
@item @code{dac_clr_n} @tab Active low clear signal for VCXO DACs
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{FMC0}
@tab @code{0} @tab
State of the reset line
@item @code{20...1}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fmc0} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue Jul 23 16:04:41 2013
-- Created : Thu Jul 25 15:15:09 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -50,7 +50,11 @@ entity carrier_csr is
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0)
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Port for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o : out std_logic_vector(19 downto 0)
);
end carrier_csr;
......@@ -60,6 +64,8 @@ signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_csr_rst_fmc0_int : std_logic ;
signal carrier_csr_rst_reserved_int : std_logic_vector(19 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -91,6 +97,8 @@ begin
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_csr_rst_fmc0_int <= '0';
carrier_csr_rst_reserved_int <= "00000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -134,6 +142,26 @@ begin
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_int <= wrdata_reg(0);
carrier_csr_rst_reserved_int <= wrdata_reg(20 downto 1);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_int;
rddata_reg(20 downto 1) <= carrier_csr_rst_reserved_int;
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -163,6 +191,10 @@ begin
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
-- State of the reset line
carrier_csr_rst_fmc0_o <= carrier_csr_rst_fmc0_int;
-- Reserved
carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
......@@ -122,7 +122,7 @@ entity spec_top_fmc_adc_100Ms is
DDR3_RZQ : inout std_logic;
-- FMC slot
adc0_ext_trigger_p_i : in std_logic; -- External trigger
adc0_ext_trigger_p_i : in std_logic; -- External trigger
adc0_ext_trigger_n_i : in std_logic;
adc0_dco_p_i : in std_logic; -- ADC data clock
......@@ -152,16 +152,16 @@ entity spec_top_fmc_adc_100Ms is
adc0_gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
adc0_gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable
adc0_si570_scl_b : inout std_logic; -- I2C bus clock (Si570)
adc0_si570_sda_b : inout std_logic; -- I2C bus data (Si570)
adc0_si570_scl_b : inout std_logic; -- I2C bus clock (Si570)
adc0_si570_sda_b : inout std_logic; -- I2C bus data (Si570)
adc0_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
-- FMC slot management
fmc0_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
fmc0_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
fmc0_sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
fmc0_sys_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
fmc0_sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
fmc0_sys_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
);
end spec_top_fmc_adc_100Ms;
......@@ -195,7 +195,9 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_ctrl_led_green_o : out std_logic;
carrier_csr_ctrl_led_red_o : out std_logic;
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0)
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_csr_rst_fmc0_o : out std_logic;
carrier_csr_rst_reserved_o : out std_logic_vector(19 downto 0)
);
end component carrier_csr;
......@@ -369,9 +371,11 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal l_clk : std_logic;
-- Reset
signal rst : std_logic;
signal sys_rst : std_logic;
signal sys_rst_n : std_logic;
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sw_rst_fmc0 : std_logic;
signal sys_rst_n : std_logic;
signal fmc0_rst_n : std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
......@@ -444,8 +448,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal spi_ss_t : std_logic_vector(7 downto 0);
-- Carrier 1-wire
signal carrier_owr_en : std_logic_vector(0 downto 0);
signal carrier_owr_i : std_logic_vector(0 downto 0);
signal carrier_owr_en : std_logic_vector(0 downto 0);
signal carrier_owr_i : std_logic_vector(0 downto 0);
-- Time-tagging core
signal trigger_p : std_logic;
......@@ -540,8 +544,27 @@ begin
------------------------------------------------------------------------------
-- System reset
------------------------------------------------------------------------------
sys_rst_n <= L_RST_N and sys_clk_pll_locked;
sys_rst <= not(sys_rst_n);
p_powerup_reset : process(sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if(L_RST_N = '0') then
powerup_rst_n <= '0';
elsif sys_clk_pll_locked = '1' then
if(powerup_reset_cnt = "11111111") then
powerup_rst_n <= '1';
else
powerup_rst_n <= '0';
powerup_reset_cnt <= powerup_reset_cnt + 1;
end if;
else
powerup_rst_n <= '0';
powerup_reset_cnt <= "00000000";
end if;
end if;
end process;
sys_rst_n <= powerup_rst_n;
fmc0_rst_n <= powerup_rst_n and sw_rst_fmc0;
------------------------------------------------------------------------------
-- GN4124 interface
......@@ -711,7 +734,9 @@ begin
carrier_csr_ctrl_led_green_o => led_green,
carrier_csr_ctrl_led_red_o => led_red,
carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_ctrl_reserved_o => open
carrier_csr_ctrl_reserved_o => open,
carrier_csr_rst_fmc0_o => sw_rst_fmc0,
carrier_csr_rst_reserved_o => open
);
-- Unused wishbone signals
......@@ -730,7 +755,7 @@ begin
cmp_timetag_core : timetag_core
port map(
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
rst_n_i => fmc0_rst_n,
trigger_p_i => trigger_p,
acq_start_p_i => acq_start_p,
......@@ -845,11 +870,11 @@ begin
cmp_fmc_adc_mezzanine_0 : fmc_adc_mezzanine
generic map(
g_multishot_ram_size => 2048,
g_carrier_type => "SPEC"
g_carrier_type => "SPEC"
)
port map(
sys_clk_i => sys_clk_125,
sys_rst_n_i => sys_rst_n,
sys_rst_n_i => fmc0_rst_n,
wb_csr_adr_i => cnx_master_out(c_SLAVE_FMC_ADC).adr,
wb_csr_dat_i => cnx_master_out(c_SLAVE_FMC_ADC).dat,
......@@ -938,7 +963,7 @@ begin
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => ddr_clk,
rst_n_i => sys_rst_n,
rst_n_i => fmc0_rst_n,
status_o => ddr3_status,
......
......@@ -653,3 +653,8 @@ NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/mem
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
# Reset
NET "powerup_rst_n" TIG;
NET "cmp_carrier_csr/carrier_csr_rst_fmc0_int" TIG;
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......@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 23 14:38:49 2013
Mapped Date : Fri Jul 26 12:17:39 2013
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,846 out of 54,576 12%
Number used as Flip Flops: 6,846
Number of Slice Registers: 6,876 out of 54,576 12%
Number used as Flip Flops: 6,876
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,642 out of 27,288 20%
Number used as logic: 5,124 out of 27,288 18%
Number using O6 output only: 3,295
Number using O5 output only: 280
Number using O5 and O6: 1,549
Number of Slice LUTs: 5,588 out of 27,288 20%
Number used as logic: 5,147 out of 27,288 18%
Number using O6 output only: 3,316
Number using O5 output only: 286
Number using O5 and O6: 1,545
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 516
Number with same-slice register load: 504
Number with same-slice carry load: 12
Number used exclusively as route-thrus: 439
Number with same-slice register load: 426
Number with same-slice carry load: 13
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,407 out of 6,822 35%
Nummber of MUXCYs used: 1,456 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,587
Number with an unused Flip Flop: 1,744 out of 7,587 22%
Number with an unused LUT: 1,945 out of 7,587 25%
Number of fully used LUT-FF pairs: 3,898 out of 7,587 51%
Number of unique control sets: 261
Number of occupied Slices: 2,403 out of 6,822 35%
Nummber of MUXCYs used: 1,464 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,655
Number with an unused Flip Flop: 1,695 out of 7,655 22%
Number with an unused LUT: 2,067 out of 7,655 27%
Number of fully used LUT-FF pairs: 3,893 out of 7,655 50%
Number of unique control sets: 265
Number of slice register sites lost
to control set restrictions: 680 out of 54,576 1%
to control set restrictions: 682 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.77
Average Fanout of Non-Clock Nets: 3.76
Peak Memory Usage: 410 MB
Total REAL time to MAP completion: 4 mins 41 secs
Total CPU time to MAP completion (all processors): 4 mins 41 secs
Peak Memory Usage: 404 MB
Total REAL time to MAP completion: 4 mins 29 secs
Total CPU time to MAP completion (all processors): 4 mins 29 secs
Table of Contents
-----------------
......@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N838,
N840,
N862,
N864,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Tue Jul 23 16:04:41 2013
* Created : Thu Jul 25 15:15:09 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -88,6 +88,17 @@
#define CARRIER_CSR_CTRL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define CARRIER_CSR_CTRL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reserved in reg: Reset Register */
#define CARRIER_CSR_RST_RESERVED_MASK WBGEN2_GEN_MASK(1, 20)
#define CARRIER_CSR_RST_RESERVED_SHIFT 1
#define CARRIER_CSR_RST_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 1, 20)
#define CARRIER_CSR_RST_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 1, 20)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
......@@ -95,6 +106,8 @@ PACKED struct CARRIER_CSR_WB {
uint32_t STAT;
/* [0x8]: REG Control */
uint32_t CTRL;
/* [0xc]: REG Reset Register */
uint32_t RST;
};
#endif
......@@ -37,6 +37,7 @@
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Carrier type and PCB version</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Status</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Control</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Reset Register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -107,6 +108,23 @@ carrier_csr_ctrl
CTRL
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#RST">Reset Register</a>
</td>
<td class="td_code">
carrier_csr_rst
</td>
<td class="td_code">
RST
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
......@@ -400,6 +418,74 @@ carrier_csr_ctrl_reserved_o[28:0]
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Reset Register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_reserved_o[19:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -1213,6 +1299,271 @@ RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="RST"></a>
<h3><a name="sect_3_4">3.4. Reset Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_rst
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
RST
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<p>
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
RESERVED[19:15]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[14:7]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0
</td>
<td >
</td>
<td >