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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
12fdd4ab
Commit
12fdd4ab
authored
Nov 05, 2018
by
Dimitris Lampridis
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hdl: fix typo in SVEC DDR resets
parent
94b9d12f
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svec_ref_fmc_adc_100Ms.vhd
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
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hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @
12fdd4ab
...
...
@@ -673,7 +673,7 @@ begin
synced_o
=>
sw_rst_ddr1_sync
);
ddr0_rst_n
<=
rst_ddr_333m_n
and
(
not
sw_rst_ddr0_sync
);
ddr1_rst_n
<=
rst_ddr_333m_n
and
(
not
sw_rst_ddr
0
_sync
);
ddr1_rst_n
<=
rst_ddr_333m_n
and
(
not
sw_rst_ddr
1
_sync
);
------------------------------------------------------------------------------
-- VME interface
...
...
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