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FMC ADC 100M 14b 4cha - Gateware
Commit 13354443 authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: Spec firmware release 2.0

parent e8ce11fd
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Showing with 906 additions and 991 deletions
hdl/spec/rtl/sdb_meta_pkg.vhd
View file @ 13354443
......@@ -53,14 +53,14 @@ package sdb_meta_pkg is
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-320
syn_commit_id => "d8644900e0d9b8544a5e20da9d0567dd",
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "dce448c21e7f9426dd5b39d1ef1d0496",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130328",
syn_date => x"20130729",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
......@@ -69,8 +69,8 @@ package sdb_meta_pkg is
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130328", -- yyyymmdd
version => x"00020000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130729", -- yyyymmdd
name => "spec_fmcadc100m14b "));
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
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hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
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hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
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hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ 13354443
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Jul 26 12:17:39 2013
Mapped Date : Mon Jul 29 10:58:04 2013
Design Summary
--------------
......@@ -23,7 +23,7 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,588 out of 27,288 20%
Number of Slice LUTs: 5,566 out of 27,288 20%
Number used as logic: 5,147 out of 27,288 18%
Number using O6 output only: 3,316
Number using O5 output only: 286
......@@ -36,18 +36,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 439
Number with same-slice register load: 426
Number used exclusively as route-thrus: 417
Number with same-slice register load: 404
Number with same-slice carry load: 13
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,403 out of 6,822 35%
Number of occupied Slices: 2,422 out of 6,822 35%
Nummber of MUXCYs used: 1,464 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,655
Number with an unused Flip Flop: 1,695 out of 7,655 22%
Number with an unused LUT: 2,067 out of 7,655 27%
Number of fully used LUT-FF pairs: 3,893 out of 7,655 50%
Number of LUT Flip Flop pairs used: 7,669
Number with an unused Flip Flop: 1,694 out of 7,669 22%
Number with an unused LUT: 2,103 out of 7,669 27%
Number of fully used LUT-FF pairs: 3,872 out of 7,669 50%
Number of unique control sets: 265
Number of slice register sites lost
to control set restrictions: 682 out of 54,576 1%
......@@ -102,9 +102,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.76
Peak Memory Usage: 404 MB
Total REAL time to MAP completion: 4 mins 29 secs
Total CPU time to MAP completion (all processors): 4 mins 29 secs
Peak Memory Usage: 411 MB
Total REAL time to MAP completion: 4 mins 42 secs
Total CPU time to MAP completion (all processors): 4 mins 42 secs
Table of Contents
-----------------
......
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