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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
19d130b1
Commit
19d130b1
authored
Nov 29, 2018
by
Dimitris Lampridis
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hdl: major rework of SPEC reference design
parent
4adc0ef9
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5 changed files
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920 additions
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1445 deletions
+920
-1445
gn4124-core
hdl/ip_cores/gn4124-core
+1
-1
wr-cores
hdl/ip_cores/wr-cores
+1
-1
spec_ref_fmc_adc_100Ms_wr.ucf
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
+444
-589
syn_extra_steps.tcl
hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
+6
-0
spec_ref_fmc_adc_100Ms.vhd
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+468
-854
No files found.
gn4124-core
@
10cd74b0
Subproject commit
5066970c44f5031e2c74e55ba54bf0e9ee3dc82f
Subproject commit
10cd74b06a094c5b6c1a566676785e1814001404
wr-cores
@
0eaae143
Subproject commit
8ed042d82021206f5fda2081e98d358467fd15f2
Subproject commit
0eaae14384e368a940935d073ae9b03aa2b4e44c
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @
19d130b1
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hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
View file @
19d130b1
...
...
@@ -14,13 +14,19 @@ xilinx::project open $project_file
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set
"Enable Multi-Threading"
"2"
-process
"Map"
xilinx::project set
"Enable Multi-Threading"
"4"
-process
"Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set
"Register Balancing"
"Yes"
xilinx::project set
"Register Duplication Map"
"On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only
)
" "
Normal
"
xilinx::project save
xilinx::project close
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
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19d130b1
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