[hdl] Timing closure tweaks

both SPEC and SVEC designs easily meet timing now. Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

[hdl] Timing closure tweaks
both SPEC and SVEC designs easily meet timing now. Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
1d987a38 · Dimitris Lampridis · 4e6378bd · 28dad208 · a96c8849 · 266a209c
Commit 1d987a38 authored Mar 05, 2020 by Dimitris Lampridis
6 changed files
--- a/ddr3-sp6-core @ 28dad208
+++ b/ddr3-sp6-core @ 28dad208
-Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
+Subproject commit 28dad2087c8df45056179796c9337c149e3cec03
--- a/general-cores @ a96c8849
+++ b/general-cores @ a96c8849
-Subproject commit 75d51c0b92015b48b176374f9a387b2d25fa8198
+Subproject commit a96c884969da8540c0ea81d6c46aaff722a064ae
--- a/spec @ 266a209c
+++ b/spec @ 266a209c
-Subproject commit 4feaba679fc13458a35066c9a5bfe9b31cb853cd
+Subproject commit 266a209cb945e7946c99ec01bace6990d08688bc
--- a/hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
+++ b/hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
@@ -120,6 +120,8 @@ INST "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0"       RLOC_ORIGIN = X30Y2
 #----------------------------------------
 INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out"   IOB = FALSE;
 INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out"     IOB = FALSE;
+INST "cmp_fmc_adc_mezzanine/cmp_fmc_i2c/U_Wrapped_I2C/*"               IOB = FALSE;
+INST "cmp_fmc_adc_mezzanine/cmp_fmc_onewire/*"                         IOB = FALSE;

 #----------------------------------------
 # Clocks

--- a/hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
+++ b/hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
@@ -27,7 +27,7 @@ xilinx::project set "Register Duplication Map" "On"
 #xilinx::project set "Placer Extra Effort Map" "Normal"
 #xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"

-xilinx::project set "Keep Hierarchy" "Yes"
+#xilinx::project set "Keep Hierarchy" "Yes"

 xilinx::project save


--- a/hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
+++ b/hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
@@ -176,6 +176,8 @@ INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0"       RLOC_ORIGIN = X69Y
 #----------------------------------------
 INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out"   IOB = FALSE;
 INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
+INST "gen_fmc_mezzanine[*].*/cmp_fmc_i2c/U_Wrapped_I2C/*"             IOB = FALSE;
+INST "gen_fmc_mezzanine[*].*/cmp_fmc_onewire/*"                       IOB = FALSE;

 #----------------------------------------
 # Clocks