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FMC ADC 100M 14b 4cha - Gateware
Commit 2213467d authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: introduce extra read-only register to allow retrieval of multi-shot memory depth

parent 025f3f63
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doc/manual/fmc_adc_100Ms_csr.tex
View file @ 2213467d
......@@ -133,6 +133,10 @@ Channel 4 offset calibration register
REG @tab
@code{ch4_sat} @tab
Channel 4 saturation register
@item @code{0x84} @tab
REG @tab
@code{multi_depth} @tab
Multi-shot sample depth register
@end multitable
@regsection @code{ctl} - Control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -659,3 +663,16 @@ Saturation value for channel 4
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{multi_depth} - Multi-shot sample depth register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{MULTI_DEPTH}
@tab @code{X} @tab
Multi-shot sample depth
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{multi_depth} @tab Maximum sample depth allowed in multi-shot acquisition mode
@end multitable
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 2213467d
......@@ -211,8 +211,8 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_ch4_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0)
);
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_multi_depth_i : in std_logic_vector(31 downto 0));
end component fmc_adc_100Ms_csr;
component ext_pulse_sync
......@@ -268,6 +268,11 @@ architecture rtl of fmc_adc_100Ms_core is
------------------------------------------------------------------------------
constant c_dpram_depth : integer := f_log2_size(g_multishot_ram_size);
-- Calculate the maximum number of available samples per multishot trigger
-- Note: we subtract 2 for the timetag
constant c_MULTISHOT_SAMPLE_DEPTH : std_logic_vector(31 downto 0) :=
std_logic_vector(to_unsigned(g_multishot_ram_size - 2, 32));
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
......@@ -782,7 +787,8 @@ begin
fmc_adc_core_ch4_sta_val_i => serdes_out_data(63 downto 48),
fmc_adc_core_ch4_gain_val_o => gain_calibr(63 downto 48),
fmc_adc_core_ch4_offset_val_o => offset_calibr(63 downto 48),
fmc_adc_core_ch4_sat_val_o => sat_val(59 downto 45)
fmc_adc_core_ch4_sat_val_o => sat_val(59 downto 45),
fmc_adc_core_multi_depth_i => c_MULTISHOT_SAMPLE_DEPTH
);
------------------------------------------------------------------------------
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ 2213467d
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri Mar 21 08:14:07 2014
-- Created : Thu Mar 17 13:38:44 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -129,7 +129,9 @@ entity fmc_adc_100Ms_csr is
-- Port for std_logic_vector field: 'Offset calibration for channel 4' in reg: 'Channel 4 offset calibration register'
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 4' in reg: 'Channel 4 saturation register'
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0)
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Multi-shot sample depth' in reg: 'Multi-shot sample depth register'
fmc_adc_core_multi_depth_i : in std_logic_vector(31 downto 0)
);
end fmc_adc_100Ms_csr;
......@@ -1148,6 +1150,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_multi_depth_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -1518,6 +1526,7 @@ begin
fmc_adc_core_ch4_offset_val_o <= fmc_adc_core_ch4_offset_val_int;
-- Saturation value for channel 4
fmc_adc_core_ch4_sat_val_o <= fmc_adc_core_ch4_sat_val_int;
-- Multi-shot sample depth
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ 2213467d
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Fri Mar 21 08:14:07 2014
* Created : Thu Mar 17 13:38:44 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -310,6 +310,8 @@
#define FMC_ADC_CORE_CH4_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH4_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Multi-shot sample depth register */
PACKED struct FMC_ADC_CORE_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
......@@ -377,6 +379,8 @@ PACKED struct FMC_ADC_CORE_WB {
uint32_t CH4_OFFSET;
/* [0x80]: REG Channel 4 saturation register */
uint32_t CH4_SAT;
/* [0x84]: REG Multi-shot sample depth register */
uint32_t MULTI_DEPTH;
};
#endif
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ 2213467d
......@@ -67,6 +67,7 @@
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">Channel 4 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">Channel 4 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">Channel 4 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">Multi-shot sample depth register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -647,6 +648,23 @@ fmc_adc_core_ch4_sat
CH4_SAT
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x21
</td>
<td >
REG
</td>
<td >
<A href="#MULTI_DEPTH">Multi-shot sample depth register</a>
</td>
<td class="td_code">
fmc_adc_core_multi_depth
</td>
<td class="td_code">
MULTI_DEPTH
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
......@@ -2640,6 +2658,57 @@ fmc_adc_core_ch4_sat_val_o[14:0]
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Multi-shot sample depth register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_multi_depth_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
......@@ -11224,6 +11293,264 @@ VAL
</b>[<i>read/write</i>]: Saturation value for channel 4
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
</ul>
<a name="MULTI_DEPTH"></a>
<h3><a name="sect_3_34">3.34. Multi-shot sample depth register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_multi_depth
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x21
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
MULTI_DEPTH
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x84
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
MULTI_DEPTH[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
MULTI_DEPTH[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
MULTI_DEPTH[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
MULTI_DEPTH[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
MULTI_DEPTH
</b>[<i>read-only</i>]: Multi-shot sample depth
<br>Maximum sample depth allowed in multi-shot acquisition mode
</ul>
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ 2213467d
......@@ -922,4 +922,18 @@ peripheral {
]]
};
reg {
name = "Multi-shot sample depth register";
prefix = "multi_depth";
field {
name = "Multi-shot sample depth";
description = "Maximum sample depth allowed in multi-shot acquisition mode";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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