Commit 2357ceda authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Fix bug in wb_ddr_fifo valid signal generation.

Was using the wrong fifo empty signal to generate the valid signal.
parent 057f2413
......@@ -1363,7 +1363,7 @@ begin
if rising_edge(sys_clk_i) then
wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
if (sync_fifo_empty = '1') then
if (wb_ddr_fifo_empty = '1') then
wb_ddr_fifo_valid <= '0';
end if;
end if;
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