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FMC ADC 100M 14b 4cha - Gateware
Commit 2756acdd authored by Matthieu Cattin's avatar Matthieu Cattin
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sim: Add random data acquisition to simulation to test interrupts.

parent aa40d03f
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Showing with 143 additions and 21 deletions
hdl/svec/sim/testbench/Makefile
View file @ 2756acdd
......@@ -56,8 +56,7 @@ VHDL_SRC := ../../../ip_cores/adc_sync_fifo.vhd \
../../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd \
../../rtl/bicolor_led_ctrl_pkg.vhd \
../../rtl/carrier_csr.vhd \
../../rtl/irq_controller.vhd \
../../rtl/irq_controller_regs.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../rtl/bicolor_led_ctrl.vhd \
../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../adc/rtl/fmc_adc_mezzanine_pkg.vhd \
......@@ -118,7 +117,7 @@ VHDL_SRC := ../../../ip_cores/adc_sync_fifo.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
......@@ -139,7 +138,7 @@ VHDL_SRC := ../../../ip_cores/adc_sync_fifo.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../rtl/irq_controller.vhd \
../../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
../../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
../../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd \
......@@ -188,8 +187,7 @@ work/utils_pkg/.utils_pkg_vhd \
work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd \
work/bicolor_led_ctrl_pkg/.bicolor_led_ctrl_pkg_vhd \
work/carrier_csr/.carrier_csr_vhd \
work/irq_controller/.irq_controller_vhd \
work/irq_controller_regs/.irq_controller_regs_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/bicolor_led_ctrl/.bicolor_led_ctrl_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd \
......@@ -250,7 +248,7 @@ work/simple_uart_wb/.simple_uart_wb_vhd \
work/wb_simple_uart/.wb_simple_uart_vhd \
work/xwb_simple_uart/.xwb_simple_uart_vhd \
work/vic_prio_enc/.vic_prio_enc_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/wb_vic/.wb_vic_vhd \
work/xwb_vic/.xwb_vic_vhd \
work/wb_spi/.wb_spi_vhd \
......@@ -271,7 +269,7 @@ work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
work/wbgen2_eic/.wbgen2_eic_vhd \
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/irq_controller/.irq_controller_vhd \
work/ddr3_ctrl/.ddr3_ctrl_vhd \
work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd \
work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd \
......@@ -464,12 +462,7 @@ work/carrier_csr/.carrier_csr_vhd: ../../rtl/carrier_csr.vhd
@mkdir -p $(dir $@) && touch $@
work/irq_controller/.irq_controller_vhd: ../../rtl/irq_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/irq_controller_regs/.irq_controller_regs_vhd: ../../rtl/irq_controller_regs.vhd
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -899,11 +892,14 @@ work/vic_prio_enc/.vic_prio_enc_vhd: ../../../ip_cores/general-cores/modules/wis
@mkdir -p $(dir $@) && touch $@
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
work/wb_slave_vic/.wb_slave_vic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg
work/wb_vic/.wb_vic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -1070,12 +1066,12 @@ work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../../ip_cores/general-cores/mod
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg
work/wb_slave_vic/.wb_slave_vic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
work/irq_controller/.irq_controller_vhd: ../../rtl/irq_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic: \
work/irq_controller/.irq_controller: \
work/wbgen2_pkg/.wbgen2_pkg
work/ddr3_ctrl/.ddr3_ctrl_vhd: ../../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd
......
hdl/svec/sim/testbench/fmc.svh
View file @ 2756acdd
......@@ -2,7 +2,7 @@
`define DECLARE_FMC(__nb) \
logic adc``__nb``_ext_trigger_p; \
logic adc``__nb``_ext_trigger_n; \
logic adc``__nb``_dco_p; \
logic adc``__nb``_dco_p = 'b0; \
logic adc``__nb``_dco_n; \
logic adc``__nb``_fr_p; \
logic adc``__nb``_fr_n; \
......@@ -66,4 +66,6 @@
.adc``__nb``_one_wire_b(adc``__nb``_one_wire), \
.fmc``__nb``_prsnt_m2c_n_i(fmc``__nb``_prsnt_m2c_n), \
.fmc``__nb``_scl_b(fmc``__nb``_scl), \
.fmc``__nb``_sda_b(fmc``__nb``_sda),
\ No newline at end of file
.fmc``__nb``_sda_b(fmc``__nb``_sda),
hdl/svec/sim/testbench/main.sv
View file @ 2756acdd
......@@ -32,6 +32,39 @@ module main;
wire carrier_sda;
wire carrier_one_wire;
logic [7:0] adc_frame = 'h0F;
always #1250ps adc0_dco_p <= ~adc0_dco_p;
typedef struct {
rand bit [15:0] data;
} adc_channel_t;
adc_channel_t adc0_channels[4];
int i, j;
always begin
for(i=0; i<8; i++)
begin
@(posedge adc0_dco_p);
#625ps;
for(j=0; j<4; j++)
begin
std::randomize(adc0_channels);
//$display("FMC0: ch%d=0x%x\n", j, adc0_channels[j].data);
adc0_outa_p[j] = adc0_channels[j].data[2*i+1];
adc0_outb_p[j] = adc0_channels[j].data[2*i];
end
adc0_fr_p = adc_frame[i];
end // for (i=0; i<8; i++)
end
assign adc0_dco_n = ~adc0_dco_p;
assign adc0_fr_n = ~adc0_fr_p;
assign adc0_outa_n = ~adc0_outa_p;
assign adc0_outb_n = ~adc0_outb_p;
svec_top_fmc_adc_100Ms
#(
.g_SIMULATION("TRUE"),
......@@ -89,6 +122,36 @@ module main;
init_vme64x_core(acc);
// Enable all interrupts
$display("Enable all interrupts\n");
acc.write('h1304, 'hF, A32|SINGLE|D32);
acc.read('h1308, d, A32|SINGLE|D32);
$display("Interrupt mask = 0x%x\n",d);
// Trigger setup (sw trigger)
$display("Trigger setup\n");
acc.write('h5308, 'h8, A32|SINGLE|D32);
// Acquisition setup
$display("Acquisition setup\n");
acc.write('h5320, 'h1, A32|SINGLE|D32); // 1 pre-trigger samples
acc.write('h5324, 'hA, A32|SINGLE|D32); // 10 post-trigger samples
acc.write('h5314, 'h1, A32|SINGLE|D32); // 1 shot
// Make sure no acquisition is running
acc.write('h5300, 'h2, A32|SINGLE|D32); // Send STOP command
// Start acquisition
$display("Start acquisition\n");
acc.write('h5300, 'h1, A32|SINGLE|D32); // Send START command
// Sw trigger
#1us
$display("Software trigger\n");
acc.write('h5310, 'hFF, A32|SINGLE|D32);
/*
acc.write('h2200, 'h0, A32|SINGLE|D32);
for(i=0; i<5; i++)
begin
......@@ -110,6 +173,7 @@ module main;
acc.read('h2100, d, A32|SINGLE|D32);
$display("Read %d: 0x%x\n", i, d);
end
*/
end
......
hdl/svec/sim/testbench/svec.do
View file @ 2756acdd
......@@ -5,10 +5,10 @@ set NumericStdNoWarnings 1
#view wave
#view transcript
do wave.do
do wave_interrupt.do
radix -hexadecimal
run 40 us
run 50 us
hdl/svec/sim/testbench/wave_interrupt.do 0 → 100644
View file @ 2756acdd
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/sys_clk_62_5
add wave -noupdate /main/DUT/sys_clk_125
add wave -noupdate /main/DUT/sys_rst_n
add wave -noupdate -divider {wb vme}
add wave -noupdate /main/DUT/cnx_slave_in(0).cyc
add wave -noupdate /main/DUT/cnx_slave_in(0).stb
add wave -noupdate /main/DUT/cnx_slave_in(0).we
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_in(0).adr
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_in(0).dat
add wave -noupdate /main/DUT/cnx_slave_out(0).ack
add wave -noupdate /main/DUT/cnx_slave_out(0).stall
add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_out(0).dat
add wave -noupdate -divider Interrupt
add wave -noupdate /main/DUT/trig_p(0)
add wave -noupdate /main/DUT/acq_end_irq_p(0)
add wave -noupdate /main/DUT/irq_to_vme
add wave -noupdate /main/DUT/irq_to_vme_t
add wave -noupdate /main/DUT/irq_to_vme_sync
add wave -noupdate -expand /main/DUT/vme_irq_n_o
add wave -noupdate -divider {fmc 0}
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate /main/adc0_dco_n
add wave -noupdate /main/adc0_dco_p
add wave -noupdate /main/adc0_fr_n
add wave -noupdate /main/adc0_fr_p
add wave -noupdate /main/adc0_outa_n
add wave -noupdate /main/adc0_outa_p
add wave -noupdate /main/adc0_outb_n
add wave -noupdate /main/adc0_outb_p
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fsm_cmd
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_start
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_stop
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_trig
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/pre_trig_cnt
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/pre_trig_done
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/post_trig_cnt
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/post_trig_done
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {30800835 ps} 0}
configure wave -namecolwidth 557
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {30305454 ps} {31619616 ps}
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