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FMC ADC 100M 14b 4cha - Gateware
Commit 30f491e1 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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hdl: code cleanup

parent 07e7b7de
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Showing with 7 additions and 22 deletions
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 30f491e1
......@@ -191,7 +191,6 @@ architecture rtl of fmc_adc_100Ms_core is
-- Reset
signal sys_rst : std_logic;
signal fs_rst : std_logic;
signal fs_rst_n : std_logic;
-- Clocks and PLL
......@@ -401,7 +400,6 @@ begin
------------------------------------------------------------------------------
sys_rst <= not(sys_rst_n_i);
fs_rst_n <= sys_rst_n_i and locked_out;
fs_rst <= not(fs_rst_n);
------------------------------------------------------------------------------
-- ADC data clock buffer
......
hdl/adc/rtl/offset_gain_s.vhd
View file @ 30f491e1
......@@ -87,7 +87,6 @@ architecture rtl of offset_gain_s is
-- Signals declaration
------------------------------------------------------------------------------
signal rst : std_logic := '0';
signal data_in_d : std_logic_vector(15 downto 0) := (others => '0');
signal data_offset : std_logic_vector(17 downto 0) := (others => '0');
signal gain : std_logic_vector(17 downto 0) := (others => '0');
signal product_t : std_logic_vector(35 downto 0) := (others => '0');
......@@ -113,9 +112,7 @@ begin
if rst_n_i = '0' then
data_offset <= (others => '0');
gain <= (others => '0');
data_in_d <= (others => '0');
else
data_in_d <= data_i;
-- propagate sign for signed offset_i
data_offset <= std_logic_vector(signed(data_i(15) & data_i(15) & data_i) +
signed(offset_i(15) & offset_i(15) & offset_i));
......
hdl/adc/rtl/timetag_core/rtl/timetag_core_regs.vhd
View file @ 30f491e1
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Thu Jun 23 11:13:24 2016
-- Created : Fri Feb 23 15:43:42 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......@@ -43,22 +43,12 @@ signal timetag_core_time_trig_coarse_int : std_logic_vector(27 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......
hdl/adc/rtl/timetag_core/rtl/timetag_core_regs_wbgen2_pkg.vhd
View file @ 30f491e1
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Thu Jun 23 11:13:24 2016
-- Created : Fri Feb 23 15:43:42 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......@@ -98,10 +98,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
hdl/adc/rtl/timetag_core/wb_gen/timetag_core_regs.h
View file @ 30f491e1
......@@ -3,7 +3,7 @@
* File : timetag_core_regs.h
* Author : auto-generated by wbgen2 from timetag_core_regs.wb
* Created : Thu Jun 23 11:13:24 2016
* Created : Fri Feb 23 15:43:42 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......
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