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FMC ADC 100M 14b 4cha - Gateware
Commit 3bf751db authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] rename undersampling to downsampling 

Fixes https://www.ohwr.org/project/fmc-adc-100m14b4cha/issues/3.
parent bb2303fc
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Showing with 38 additions and 38 deletions
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 3bf751db
......@@ -222,10 +222,10 @@ architecture rtl of fmc_adc_100Ms_core is
signal trig_storage_clear : std_logic;
signal trig_src_vector : std_logic_vector(7 downto 0);
-- Under-sampling
signal undersample_factor : std_logic_vector(31 downto 0) := (others => '0');
signal undersample_cnt : unsigned(31 downto 0);
signal undersample_en : std_logic;
-- Down-sampling
signal downsample_factor : std_logic_vector(31 downto 0) := (others => '0');
signal downsample_cnt : unsigned(31 downto 0);
signal downsample_en : std_logic;
-- Sync FIFO (from fs_clk to sys_clk_i)
signal sync_fifo_din : std_logic_vector(72 downto 0);
......@@ -590,7 +590,7 @@ begin
data_i => csr_regout.trig_en_alt_time,
synced_o => alt_time_trig_en);
cmp_undersample_sync : gc_sync_word_wr
cmp_downsample_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 32)
......@@ -599,8 +599,8 @@ begin
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => csr_regout.undersample,
data_o => undersample_factor);
data_i => csr_regout.downsample,
data_o => downsample_factor);
cmp_ch_sta_sync : gc_sync_word_wr
generic map (
......@@ -957,29 +957,29 @@ begin
trig <= f_reduce_or (trig_src_vector);
------------------------------------------------------------------------------
-- Under-sampling and trigger alignment
-- When under-sampling is enabled, if the trigger occurs between two
-- Down-sampling and trigger alignment
-- When down-sampling is enabled, if the trigger occurs between two
-- samples it will be realigned to the next sample
------------------------------------------------------------------------------
p_undersample_cnt : process (fs_clk)
p_downsample_cnt : process (fs_clk)
begin
if rising_edge(fs_clk) then
if fs_rst_n = '0' then
undersample_cnt <= to_unsigned(1, undersample_cnt'length);
undersample_en <= '0';
downsample_cnt <= to_unsigned(1, downsample_cnt'length);
downsample_en <= '0';
else
if undersample_cnt = to_unsigned(0, undersample_cnt'length) then
if undersample_factor /= X"00000000" then
undersample_cnt <= unsigned(undersample_factor) - 1;
if downsample_cnt = to_unsigned(0, downsample_cnt'length) then
if downsample_factor /= X"00000000" then
downsample_cnt <= unsigned(downsample_factor) - 1;
end if;
undersample_en <= '1';
downsample_en <= '1';
else
undersample_cnt <= undersample_cnt - 1;
undersample_en <= '0';
downsample_cnt <= downsample_cnt - 1;
downsample_en <= '0';
end if;
end if;
end if;
end process p_undersample_cnt;
end process p_downsample_cnt;
p_trig_align : process (fs_clk)
begin
......@@ -989,7 +989,7 @@ begin
else
if trig = '1' then
trig_align <= trig_src_vector & trig;
elsif undersample_en = '1' then
elsif downsample_en = '1' then
trig_align <= (others => '0');
end if;
end if;
......@@ -1032,7 +1032,7 @@ begin
sync_fifo_din(63 downto 0) <= data_calibr_out_d3;
-- FIFO control
sync_fifo_wr <= undersample_en and serdes_synced and (not sync_fifo_full);
sync_fifo_wr <= downsample_en and serdes_synced and (not sync_fifo_full);
sync_fifo_rd <= not sync_fifo_empty;
sync_fifo_valid <= not sync_fifo_empty;
......
hdl/rtl/fmc_adc_100Ms_csr.cheby
View file @ 3bf751db
......@@ -377,13 +377,13 @@ memory-map:
comment: |
ADC sampling clock frequency in Hz
- reg:
name: undersample
name: downsample
address: 0x0000002c
width: 32
access: rw
description: Undersampling ratio
description: Downsampling ratio
comment: |
Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio)
Downsampling ratio. Takes one sample every N samples and discards the others (N = downsampling ratio)
- reg:
name: pre_samples
address: 0x00000030
......
hdl/rtl/fmc_adc_100Ms_csr.vhd
View file @ 3bf751db
......@@ -40,7 +40,7 @@ package fmc_adc_100ms_csr_pkg is
sw_trig_wr : std_logic;
shots_nbr : std_logic_vector(15 downto 0);
shots_remain : std_logic_vector(15 downto 0);
undersample : std_logic_vector(31 downto 0);
downsample : std_logic_vector(31 downto 0);
pre_samples : std_logic_vector(31 downto 0);
post_samples : std_logic_vector(31 downto 0);
ch1_ctl_ssr : std_logic_vector(6 downto 0);
......@@ -155,7 +155,7 @@ architecture syn of fmc_adc_100ms_csr is
signal trig_pol_ch4_reg : std_logic;
signal ext_trig_dly_reg : std_logic_vector(31 downto 0);
signal shots_nbr_reg : std_logic_vector(15 downto 0);
signal undersample_reg : std_logic_vector(31 downto 0);
signal downsample_reg : std_logic_vector(31 downto 0);
signal pre_samples_reg : std_logic_vector(31 downto 0);
signal post_samples_reg : std_logic_vector(31 downto 0);
signal ch1_ctl_ssr_reg : std_logic_vector(6 downto 0);
......@@ -247,7 +247,7 @@ begin
fmc_adc_100ms_csr_o.trig_pol_ch4 <= trig_pol_ch4_reg;
fmc_adc_100ms_csr_o.ext_trig_dly <= ext_trig_dly_reg;
fmc_adc_100ms_csr_o.shots_nbr <= shots_nbr_reg;
fmc_adc_100ms_csr_o.undersample <= undersample_reg;
fmc_adc_100ms_csr_o.downsample <= downsample_reg;
fmc_adc_100ms_csr_o.pre_samples <= pre_samples_reg;
fmc_adc_100ms_csr_o.post_samples <= post_samples_reg;
fmc_adc_100ms_csr_o.ch1_ctl_ssr <= ch1_ctl_ssr_reg;
......@@ -311,7 +311,7 @@ begin
ext_trig_dly_reg <= "00000000000000000000000000000000";
fmc_adc_100ms_csr_o.sw_trig_wr <= '0';
shots_nbr_reg <= "0000000000000000";
undersample_reg <= "00000000000000000000000000000000";
downsample_reg <= "00000000000000000000000000000000";
pre_samples_reg <= "00000000000000000000000000000000";
post_samples_reg <= "00000000000000000000000000000000";
ch1_ctl_ssr_reg <= "0000000";
......@@ -420,9 +420,9 @@ begin
when "0001010" =>
-- Register fs_freq
when "0001011" =>
-- Register undersample
-- Register downsample
if wr_int = '1' then
undersample_reg <= wb_i.dat;
downsample_reg <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "0001100" =>
......@@ -667,8 +667,8 @@ begin
reg_rdat_int <= fmc_adc_100ms_csr_i.fs_freq;
rd_ack1_int <= rd_int;
when "0001011" =>
-- undersample
reg_rdat_int <= undersample_reg;
-- downsample
reg_rdat_int <= downsample_reg;
rd_ack1_int <= rd_int;
when "0001100" =>
-- pre_samples
......@@ -844,7 +844,7 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0001011" =>
-- undersample
-- downsample
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0001100" =>
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ 3bf751db
......@@ -88,7 +88,7 @@
`define ADDR_FMC_ADC_100MS_CSR_MULTI_DEPTH 'h20
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POS 'h24
`define ADDR_FMC_ADC_100MS_CSR_FS_FREQ 'h28
`define ADDR_FMC_ADC_100MS_CSR_UNDERSAMPLE 'h2c
`define ADDR_FMC_ADC_100MS_CSR_DOWNSAMPLE 'h2c
`define ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES 'h30
`define ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES 'h34
`define ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT 'h38
......
software/include/hw/fmc_adc_100Ms_csr.h
View file @ 3bf751db
......@@ -77,8 +77,8 @@
/* Sampling clock frequency */
#define FMC_ADC_100MS_CSR_FS_FREQ 0x28UL
/* Undersampling ratio */
#define FMC_ADC_100MS_CSR_UNDERSAMPLE 0x2cUL
/* Downsampling ratio */
#define FMC_ADC_100MS_CSR_DOWNSAMPLE 0x2cUL
/* Pre-trigger samples */
#define FMC_ADC_100MS_CSR_PRE_SAMPLES 0x30UL
......@@ -251,8 +251,8 @@ struct fmc_adc_100ms_csr {
/* [0x28]: REG (ro) Sampling clock frequency */
uint32_t fs_freq;
/* [0x2c]: REG (rw) Undersampling ratio */
uint32_t undersample;
/* [0x2c]: REG (rw) Downsampling ratio */
uint32_t downsample;
/* [0x30]: REG (rw) Pre-trigger samples */
uint32_t pre_samples;
......
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