Commit 3c4e2201 authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Make mezzanine reset inactive by default on the spec.

parent b536d7b4
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd -- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb -- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Dec 11 11:55:04 2013 -- Created : Tue Jan 14 11:45:49 2014
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...@@ -51,8 +51,10 @@ entity carrier_csr is ...@@ -51,8 +51,10 @@ entity carrier_csr is
carrier_csr_ctrl_dac_clr_n_o : out std_logic; carrier_csr_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control' -- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0); carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Port for BIT field: 'State of the reset line' in reg: 'Reset Register' -- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic; carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register' -- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0) carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0)
); );
...@@ -64,7 +66,6 @@ signal carrier_csr_ctrl_led_green_int : std_logic ; ...@@ -64,7 +66,6 @@ signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ; signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ; signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0); signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_csr_rst_fmc0_n_int : std_logic ;
signal carrier_csr_rst_reserved_int : std_logic_vector(30 downto 0); signal carrier_csr_rst_reserved_int : std_logic_vector(30 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
...@@ -97,7 +98,7 @@ begin ...@@ -97,7 +98,7 @@ begin
carrier_csr_ctrl_led_red_int <= '0'; carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0'; carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000"; carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_csr_rst_fmc0_n_int <= '0'; carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_reserved_int <= "0000000000000000000000000000000"; carrier_csr_rst_reserved_int <= "0000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
...@@ -105,8 +106,10 @@ begin ...@@ -105,8 +106,10 @@ begin
ack_sreg(9) <= '0'; ack_sreg(9) <= '0';
if (ack_in_progress = '1') then if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then if (ack_sreg(0) = '1') then
carrier_csr_rst_fmc0_n_load_o <= '0';
ack_in_progress <= '0'; ack_in_progress <= '0';
else else
carrier_csr_rst_fmc0_n_load_o <= '0';
end if; end if;
else else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
...@@ -144,10 +147,10 @@ begin ...@@ -144,10 +147,10 @@ begin
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11" => when "11" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_int <= wrdata_reg(0); carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_reserved_int <= wrdata_reg(31 downto 1); carrier_csr_rst_reserved_int <= wrdata_reg(31 downto 1);
end if; end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_int; rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(31 downto 1) <= carrier_csr_rst_reserved_int; rddata_reg(31 downto 1) <= carrier_csr_rst_reserved_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
...@@ -181,7 +184,7 @@ begin ...@@ -181,7 +184,7 @@ begin
-- Reserved -- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int; carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
-- State of the reset line -- State of the reset line
carrier_csr_rst_fmc0_n_o <= carrier_csr_rst_fmc0_n_int; carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- Reserved -- Reserved
carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int; carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int;
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
......
...@@ -197,6 +197,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -197,6 +197,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_ctrl_dac_clr_n_o : out std_logic; carrier_csr_ctrl_dac_clr_n_o : out std_logic;
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0); carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_csr_rst_fmc0_n_o : out std_logic; carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0) carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0)
); );
end component carrier_csr; end component carrier_csr;
...@@ -349,7 +351,10 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -349,7 +351,10 @@ architecture rtl of spec_top_fmc_adc_100Ms is
-- Reset -- Reset
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000"; signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0'; signal powerup_rst_n : std_logic := '0';
signal sw_rst_fmc0_n : std_logic; signal sw_rst_fmc0_n : std_logic := '1';
signal sw_rst_fmc0_n_o : std_logic;
signal sw_rst_fmc0_n_i : std_logic;
signal sw_rst_fmc0_n_load : std_logic;
signal sys_rst_n : std_logic; signal sys_rst_n : std_logic;
signal fmc0_rst_n : std_logic; signal fmc0_rst_n : std_logic;
...@@ -705,7 +710,9 @@ begin ...@@ -705,7 +710,9 @@ begin
carrier_csr_ctrl_led_red_o => led_red, carrier_csr_ctrl_led_red_o => led_red,
carrier_csr_ctrl_dac_clr_n_o => open, carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_ctrl_reserved_o => open, carrier_csr_ctrl_reserved_o => open,
carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n, carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o,
carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i,
carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load,
carrier_csr_rst_reserved_o => open carrier_csr_rst_reserved_o => open
); );
...@@ -719,6 +726,20 @@ begin ...@@ -719,6 +726,20 @@ begin
led_red_o <= led_red; led_red_o <= led_red;
led_green_o <= led_green; led_green_o <= led_green;
-- external software reset register (to assign a non-zero default value)
p_sw_rst_fmc0: process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
sw_rst_fmc0_n <= '1';
elsif sw_rst_fmc0_n_load = '1' then
sw_rst_fmc0_n <= sw_rst_fmc0_n_o;
end if;
end if;
end process p_sw_rst_fmc0;
sw_rst_fmc0_n_i <= sw_rst_fmc0_n;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC) -- Vectored interrupt controller (VIC)
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
......
...@@ -656,5 +656,5 @@ NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/mem ...@@ -656,5 +656,5 @@ NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/mem
# Reset # Reset
NET "powerup_rst_n" TIG; NET "powerup_rst_n" TIG;
NET "cmp_carrier_csr/carrier_csr_rst_fmc0_n_int" TIG; NET "sw_rst_fmc0_n" TIG;
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : carrier_csr.h * File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb * Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Wed Dec 11 11:55:04 2013 * Created : Tue Jan 14 11:45:49 2014
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
...@@ -478,6 +478,40 @@ carrier_csr_rst_fmc0_n_o ...@@ -478,6 +478,40 @@ carrier_csr_rst_fmc0_n_o
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_n_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_fmc0_n_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
carrier_csr_rst_reserved_o[30:0] carrier_csr_rst_reserved_o[30:0]
...@@ -1558,7 +1592,7 @@ FMC0_N ...@@ -1558,7 +1592,7 @@ FMC0_N
<li><b> <li><b>
FMC0_N FMC0_N
</b>[<i>read/write</i>]: State of the reset line </b>[<i>read/write</i>]: State of the reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation <br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
<li><b> <li><b>
RESERVED RESERVED
</b>[<i>read/write</i>]: Reserved </b>[<i>read/write</i>]: Reserved
......
...@@ -141,12 +141,13 @@ peripheral { ...@@ -141,12 +141,13 @@ peripheral {
field { field {
name = "State of the reset line"; name = "State of the reset line";
description = "write 0: FMC is held in reset\ description = "write 0: FMC is held in reset\
write 1: Normal FMC operation"; write 1: Normal FMC operation (default)";
type = BIT; type = BIT;
load = LOAD_EXT;
size = 1; size = 1;
prefix = "fmc0_n"; prefix = "fmc0_n";
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_WRITE;
}; };
field { field {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment