Commit 426788b5 authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl/sim: sanitized and updated SVEC simulation. Tested with ModelSIM 10.2a, works.

parent 2e05f2a2
hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs
hdl/*/sim/transcript
hdl/*/sim/vsim.wlf
hdl/*/sim/Makefile
hdl/*/sim/modelsim.ini
hdl/*/sim/work/
hdl/*/sim/*/transcript
hdl/*/sim/*/vsim.wlf
hdl/*/sim/*/Makefile
hdl/*/sim/*/modelsim.ini
hdl/*/sim/*/work/
hdl/*/testbench/top/transcript
hdl/*/testbench/top/vsim.wlf
hdl/*/testbench/top/Makefile
......
......@@ -559,7 +559,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
......
This diff is collapsed.
sim_tool="modelsim"
top_module="main"
action = "simulation"
target = "xilinx"
vlog_opt="+incdir+../vme64x_bfm +incdir+../2048Mb_ddr3"
syn_device = "xc6slx150t"
include_dirs=["../vme64x_bfm", "../2048Mb_ddr3", "../../../ip_cores/general-cores/sim"]
files = [ "main.sv",
"../../../ip_cores/adc_sync_fifo.vhd",
......@@ -21,3 +23,5 @@ modules = { "local" : [ "../../rtl",
"git://ohwr.org/hdl-core-lib/vme64x-core.git::master"]}
fetchto="../../../ip_cores"
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
......@@ -117,7 +117,9 @@ module main;
int i, result;
CBusAccessor_VME64x acc = new(VME.master);
CBusAccessor_VME64x acc;
acc = new(VME.master);
#20us;
......
vsim -novopt -t 1ps main
log -r /*
#log -r /*
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
#view wave
#view transcript
#do wave_interrupt.do
do wave_ddr.do
do wave_interrupt.do
#do wave_ddr.do
#do wave.do
radix -hexadecimal
run 50 us
......
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