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FMC ADC 100M 14b 4cha - Gateware
Commit 49ea11d3 authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: gennum hang solved -> Synthesis with master branch of general-cores library. 

no_coregen branch generic_fifo is buggy, not outputing the last written data
from time to time.
Was causing the gennum core to hang (waiting forever on the last data).
parent 25910c1a
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Showing with 3819 additions and 1698 deletions
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 49ea11d3
......@@ -323,85 +323,88 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-19T16:51:55" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="494C936A59B24A26716C2B8E1771F2A1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-05T13:56:04" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="354EEA7886BD17F3531E42B45056CD84" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<libraries>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
<files>
<file xil_pn:name="../spec_top_fmc_adc_100Ms.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../ip_cores/adc_sync_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../ip_cores/adc_sync_fifo.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../ip_cores/multishot_dpram.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../ip_cores/multishot_dpram.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../ip_cores/wb_ddr_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../ip_cores/wb_ddr_fifo.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../ip_cores/adc_serdes.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../ip_cores/adc_serdes.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../ip_cores/monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/utils/utils_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../ip_cores/utils/utils_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/utc_core_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../rtl/utc_core_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/utc_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../rtl/utc_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/irq_controller_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../rtl/irq_controller_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/irq_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../rtl/irq_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
......@@ -425,318 +428,662 @@
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="../spec_top_fmc_adc_100Ms.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
</files>
<bindings/>
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
View file @ 49ea11d3
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Fri Nov 30 14:48:11 2012
pcbe15575:: Tue Mar 05 14:03:31 2013
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
......@@ -22,16 +22,16 @@ Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 6,576 out of 54,576 12%
Number used as Flip Flops: 6,576
Number of Slice Registers: 6,805 out of 54,576 12%
Number used as Flip Flops: 6,805
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,403 out of 27,288 19%
Number used as logic: 5,150 out of 27,288 18%
Number using O6 output only: 3,289
Number using O5 output only: 360
Number using O5 and O6: 1,501
Number of Slice LUTs: 5,656 out of 27,288 20%
Number used as logic: 5,168 out of 27,288 18%
Number using O6 output only: 3,262
Number using O5 output only: 280
Number using O5 and O6: 1,626
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -40,18 +40,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 251
Number with same-slice register load: 230
Number with same-slice carry load: 21
Number used exclusively as route-thrus: 486
Number with same-slice register load: 475
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,516 out of 6,822 36%
Nummber of MUXCYs used: 1,384 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,794
Number with an unused Flip Flop: 1,901 out of 7,794 24%
Number with an unused LUT: 2,391 out of 7,794 30%
Number of fully used LUT-FF pairs: 3,502 out of 7,794 44%
Number of occupied Slices: 2,412 out of 6,822 35%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,602
Number with an unused Flip Flop: 1,775 out of 7,602 23%
Number with an unused LUT: 1,946 out of 7,602 25%
Number of fully used LUT-FF pairs: 3,881 out of 7,602 51%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -109,42 +109,41 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting initial Timing Analysis. REAL time: 17 secs
Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal aux_buttons_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TX_ERROR_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 44589 unrouted; REAL time: 16 secs
Phase 1 : 45008 unrouted; REAL time: 19 secs
Phase 2 : 34630 unrouted; REAL time: 20 secs
Phase 2 : 34718 unrouted; REAL time: 24 secs
Phase 3 : 14274 unrouted; REAL time: 48 secs
Phase 3 : 14220 unrouted; REAL time: 48 secs
Phase 4 : 14347 unrouted; (Setup:51, Hold:112, Component Switching Limit:0) REAL time: 54 secs
Phase 4 : 14410 unrouted; (Setup:0, Hold:8355, Component Switching Limit:0) REAL time: 53 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:131, Hold:112, Component Switching Limit:0) REAL time: 1 mins 40 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:7430, Component Switching Limit:0) REAL time: 1 mins 34 secs
Phase 6 : 0 unrouted; (Setup:131, Hold:112, Component Switching Limit:0) REAL time: 1 mins 41 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7430, Component Switching Limit:0) REAL time: 1 mins 34 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:112, Component Switching Limit:0) REAL time: 2 mins 6 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7430, Component Switching Limit:0) REAL time: 1 mins 34 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:112, Component Switching Limit:0) REAL time: 2 mins 6 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7430, Component Switching Limit:0) REAL time: 1 mins 34 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 7 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 34 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 10 secs
Total REAL time to Router completion: 2 mins 10 secs
Total CPU time to Router completion: 2 mins 18 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 37 secs
Total REAL time to Router completion: 1 mins 37 secs
Total CPU time to Router completion: 1 mins 37 secs
Partition Implementation Status
-------------------------------
......@@ -162,19 +161,19 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_100Ms_co | | | | | |
| re/fs_clk | BUFGMUX_X2Y4| No | 162 | 0.248 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 652 | 0.187 | 1.398 |
| clk | BUFGMUX_X2Y12| No | 630 | 0.185 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_mcb_d | | | | | |
| rp_clk | BUFGMUX_X3Y13| No | 82 | 0.072 | 1.285 |
| rp_clk | BUFGMUX_X3Y13| No | 80 | 0.052 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y2| No | 1352 | 0.065 | 1.276 |
| sys_clk_125 | BUFGMUX_X2Y2| No | 1326 | 0.066 | 1.277 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_100Ms_co | | | | | |
| re/fs_clk | BUFGMUX_X2Y4| No | 161 | 0.255 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -290,23 +289,18 @@ Asterisk (*) preceding a constraint indicates it was not met.
k_2x_180" TS_SYS_CLK5 / 2 PHASE 0 | | | | |
.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.035ns| 4.965ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.125ns| | 0| 0
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.041ns| 7.959ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.279ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.064ns| 4.936ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.183ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.039ns| 7.961ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.263ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc_dco_n_i = PERIOD TIMEGRP "adc_dco_ | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_100Ms_core_fs_clk_buf = PE | SETUP | 0.329ns| 7.671ns| 0| 0
RIOD TIMEGRP "cmp_fmc_adc_100Ms_c | HOLD | 0.381ns| | 0| 0
ore_fs_clk_buf" TS_adc_dco_n_i / 0.25 HIG | | | | |
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_ | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
buf" TS_clk20_vcxo_i / 16.6666667 | | | | |
......@@ -314,6 +308,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
----------------------------------------------------------------------------------------------------------
TS_SYS_CLK5 = PERIOD TIMEGRP "SYS_CLK5" 3 | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_100Ms_core_fs_clk_buf = PE | SETUP | 0.537ns| 7.463ns| 0| 0
RIOD TIMEGRP "cmp_fmc_adc_100Ms_c | HOLD | 0.405ns| | 0| 0
ore_fs_clk_buf" TS_adc_dco_n_i / 0.25 HIG | | | | |
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
= PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
......@@ -340,8 +339,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 5.651ns| 6.348ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.393ns| | 0| 0
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 5.099ns| 6.900ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.291ns| | 0| 0
nfrastructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr | | | | |
_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank | | | | |
......@@ -402,12 +401,12 @@ Derived Constraints for TS_p2l_clkn
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.965ns| 0| 0| 0| 30220|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.965ns| 0| 0| 0| 30220|
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.936ns| 0| 0| 0| 29035|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.936ns| 0| 0| 0| 29035|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.965ns| N/A| 0| 0| 30220| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.936ns| N/A| 0| 0| 29035| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -417,10 +416,10 @@ Derived Constraints for TS_clk20_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 403095|
| TS_sys_clk_125_buf | 8.000ns| 7.961ns| N/A| 0| 0| 392695| 0|
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 402700|
| TS_sys_clk_125_buf | 8.000ns| 7.959ns| N/A| 0| 0| 392300| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 10400|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 6.348ns| N/A| 0| 0| 10400| 0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 6.900ns| N/A| 0| 0| 10400| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_mcb_drp_clk_buf| | | | | | | |
......@@ -462,8 +461,8 @@ Derived Constraints for TS_adc_dco_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_dco_n_i | 2.000ns| 1.636ns| 1.918ns| 0| 0| 0| 18373|
| TS_cmp_fmc_adc_100Ms_core_fs_c| 8.000ns| 7.671ns| N/A| 0| 0| 18373| 0|
|TS_adc_dco_n_i | 2.000ns| 1.636ns| 1.866ns| 0| 0| 0| 18373|
| TS_cmp_fmc_adc_100Ms_core_fs_c| 8.000ns| 7.463ns| N/A| 0| 0| 18373| 0|
| lk_buf | | | | | | | |
| TS_cmp_fmc_adc_100Ms_core_serd| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| es_clk | | | | | | | |
......@@ -481,19 +480,19 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 2 mins 13 secs
Total CPU time to PAR completion: 2 mins 21 secs
Total REAL time to PAR completion: 1 mins 40 secs
Total CPU time to PAR completion: 1 mins 41 secs
Peak Memory Usage: 351 MB
Peak Memory Usage: 341 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 9
Number of warning messages: 8
Number of info messages: 1
Writing design to file spec_top_fmc_adc_100Ms.ncd
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
View file @ 49ea11d3
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
View file @ 49ea11d3
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ 49ea11d3
......@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Nov 30 14:43:16 2012
Mapped Date : Tue Mar 5 13:58:38 2013
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,576 out of 54,576 12%
Number used as Flip Flops: 6,576
Number of Slice Registers: 6,805 out of 54,576 12%
Number used as Flip Flops: 6,805
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,403 out of 27,288 19%
Number used as logic: 5,150 out of 27,288 18%
Number using O6 output only: 3,289
Number using O5 output only: 360
Number using O5 and O6: 1,501
Number of Slice LUTs: 5,656 out of 27,288 20%
Number used as logic: 5,168 out of 27,288 18%
Number using O6 output only: 3,262
Number using O5 output only: 280
Number using O5 and O6: 1,626
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 251
Number with same-slice register load: 230
Number with same-slice carry load: 21
Number used exclusively as route-thrus: 486
Number with same-slice register load: 475
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,516 out of 6,822 36%
Nummber of MUXCYs used: 1,384 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,794
Number with an unused Flip Flop: 1,901 out of 7,794 24%
Number with an unused LUT: 2,391 out of 7,794 30%
Number of fully used LUT-FF pairs: 3,502 out of 7,794 44%
Number of unique control sets: 235
Number of occupied Slices: 2,412 out of 6,822 35%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,602
Number with an unused Flip Flop: 1,775 out of 7,602 23%
Number with an unused LUT: 1,946 out of 7,602 25%
Number of fully used LUT-FF pairs: 3,881 out of 7,602 51%
Number of unique control sets: 260
Number of slice register sites lost
to control set restrictions: 542 out of 54,576 1%
to control set restrictions: 673 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.78
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 415 MB
Total REAL time to MAP completion: 4 mins 49 secs
Total CPU time to MAP completion (all processors): 4 mins 53 secs
Peak Memory Usage: 418 MB
Total REAL time to MAP completion: 4 mins 46 secs
Total CPU time to MAP completion (all processors): 4 mins 46 secs
Table of Contents
-----------------
......@@ -162,10 +162,10 @@ INFO:Map:284 - Map is running with the multi-threading option on. Map currently
INFO:LIT:243 - Logical network
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 9 more times for the following
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N686,
N688,
N754,
N756,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
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