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FMC ADC 100M 14b 4cha - Gateware
Commit 49ea11d3 authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: gennum hang solved -> Synthesis with master branch of general-cores library. 

no_coregen branch generic_fifo is buggy, not outputing the last written data
from time to time.
Was causing the gennum core to hang (waiting forever on the last data).
parent 25910c1a
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hdl/spec/syn/spec_fmc_adc_100Ms.xise
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hdl/spec/syn/spec_top_fmc_adc_100Ms.par
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hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
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hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
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hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
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...@@ -11,23 +11,23 @@ Target Device : xc6slx45t ...@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484 Target Package : fgg484
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Nov 30 14:43:16 2012 Mapped Date : Tue Mar 5 13:58:38 2013
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 8 Number of warnings: 8
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 6,576 out of 54,576 12% Number of Slice Registers: 6,805 out of 54,576 12%
Number used as Flip Flops: 6,576 Number used as Flip Flops: 6,805
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 5,403 out of 27,288 19% Number of Slice LUTs: 5,656 out of 27,288 20%
Number used as logic: 5,150 out of 27,288 18% Number used as logic: 5,168 out of 27,288 18%
Number using O6 output only: 3,289 Number using O6 output only: 3,262
Number using O5 output only: 360 Number using O5 output only: 280
Number using O5 and O6: 1,501 Number using O5 and O6: 1,626
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1% Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0 Number used as Dual Port RAM: 0
...@@ -36,21 +36,21 @@ Slice Logic Utilization: ...@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2 Number using O6 output only: 2
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 251 Number used exclusively as route-thrus: 486
Number with same-slice register load: 230 Number with same-slice register load: 475
Number with same-slice carry load: 21 Number with same-slice carry load: 11
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 2,516 out of 6,822 36% Number of occupied Slices: 2,412 out of 6,822 35%
Nummber of MUXCYs used: 1,384 out of 13,644 10% Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,794 Number of LUT Flip Flop pairs used: 7,602
Number with an unused Flip Flop: 1,901 out of 7,794 24% Number with an unused Flip Flop: 1,775 out of 7,602 23%
Number with an unused LUT: 2,391 out of 7,794 30% Number with an unused LUT: 1,946 out of 7,602 25%
Number of fully used LUT-FF pairs: 3,502 out of 7,794 44% Number of fully used LUT-FF pairs: 3,881 out of 7,602 51%
Number of unique control sets: 235 Number of unique control sets: 260
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 542 out of 54,576 1% to control set restrictions: 673 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -100,11 +100,11 @@ Specific Feature Utilization: ...@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.78 Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 415 MB Peak Memory Usage: 418 MB
Total REAL time to MAP completion: 4 mins 49 secs Total REAL time to MAP completion: 4 mins 46 secs
Total CPU time to MAP completion (all processors): 4 mins 53 secs Total CPU time to MAP completion (all processors): 4 mins 46 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -162,10 +162,10 @@ INFO:Map:284 - Map is running with the multi-threading option on. Map currently ...@@ -162,10 +162,10 @@ INFO:Map:284 - Map is running with the multi-threading option on. Map currently
INFO:LIT:243 - Logical network INFO:LIT:243 - Logical network
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3 cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3
_infrastructure_inst/rst0_sync_r<24> has no load. _infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 9 more times for the following INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown): (max. 5 shown):
N686, N754,
N688, N756,
aux_buttons_i<1>_IBUF, aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF, aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF P_WR_REQ<1>_IBUF
......
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