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FMC ADC 100M 14b 4cha - Gateware
Commit 4d567730 authored by Matthieu Cattin's avatar Matthieu Cattin
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sim: simulation modif for gnum. 

Tying to find the PC hang bug.
parent 555b7a24
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Showing with 15 additions and 15 deletions
hdl/spec/sim/cmd0.vec
View file @ 4d567730
...@@ -282,11 +282,11 @@ wr FF00000000001010 F 00000000 ...@@ -282,11 +282,11 @@ wr FF00000000001010 F 00000000
-- DMA length -- DMA length
wr FF00000000001014 F 00001000 wr FF00000000001014 F 00001000
-- Next item address (lsb) -- Next item address (lsb)
wr FF00000000001018 F 00000000 wr FF00000000001018 F 20000000
-- Next item address (msb) -- Next item address (msb)
wr FF0000000000101C F 00000000 wr FF0000000000101C F 00000000
-- DMA attributes (from carrier to host, last item) -- DMA attributes (from carrier to host, last item)
wr FF00000000001020 F 00000000 wr FF00000000001020 F 00000001
-- Start DMA -- Start DMA
wr FF00000000001000 F 00000001 wr FF00000000001000 F 00000001
...@@ -295,32 +295,32 @@ wait %d3000 ...@@ -295,32 +295,32 @@ wait %d3000
--------------------------------------------- ---------------------------------------------
-- start acquisition -- start acquisition
wr FF00000000001900 F 00000001 --wr FF00000000001900 F 00000001
wait %d500 wait %d500
-- sw trigger -- sw trigger
wr FF00000000001910 F FFFFFFFF --wr FF00000000001910 F FFFFFFFF
wait %d400 wait %d400
-- DMA -- DMA
------------------------------ ------------------------------
-- Carrier start address -- Carrier start address
wr FF00000000001008 F 00000000 --wr FF00000000001008 F 00000000
-- Host start address (lsb) -- Host start address (lsb)
wr FF0000000000100C F 40000000 --wr FF0000000000100C F 40000000
-- Host start address (msb) -- Host start address (msb)
wr FF00000000001010 F 00000000 --wr FF00000000001010 F 00000000
-- DMA length -- DMA length
wr FF00000000001014 F 00000200 --wr FF00000000001014 F 00000200
-- Next item address (lsb) -- Next item address (lsb)
wr FF00000000001018 F 20000000 --wr FF00000000001018 F 20000000
-- Next item address (msb) -- Next item address (msb)
wr FF0000000000101C F 00000000 --wr FF0000000000101C F 00000000
-- DMA attributes (from carrier to host, last item) -- DMA attributes (from carrier to host, last item)
wr FF00000000001020 F 00000000 --wr FF00000000001020 F 00000000
-- Start DMA -- Start DMA
wr FF00000000001000 F 00000001 --wr FF00000000001000 F 00000001
wait %d1000 wait %d1000
......
hdl/spec/sim/sim_models/2048Mb_ddr3/ddr3_parameters.vh
View file @ 4d567730
...@@ -820,7 +820,7 @@ ...@@ -820,7 +820,7 @@
parameter RZQ = 240; // termination resistance parameter RZQ = 240; // termination resistance
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 1; // Turn on Debug messages parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator. parameter RANDOM_SEED = 711689044; //seed value for random generator.
......
hdl/spec/sim/spec.do
View file @ 4d567730
...@@ -6,9 +6,9 @@ log -r /* ...@@ -6,9 +6,9 @@ log -r /*
##do wave_multishot.do ##do wave_multishot.do
##do wave_onewire.do ##do wave_onewire.do
##do wave_adc_core.do ##do wave_adc_core.do
##do wave_gnum.do do wave_gnum.do
##do wave_end_acq_irq.do ##do wave_end_acq_irq.do
do wave_ddr_wb.do ##do wave_ddr_wb.do
view wave view wave
view transcript view transcript
......
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