Commit 4e6378bd authored by Dimitris Lampridis's avatar Dimitris Lampridis

Merge branch 'feature/convention' into proposed_master

parents d98dbd10 bb7a29f7
...@@ -13,3 +13,9 @@ ...@@ -13,3 +13,9 @@
[submodule "hdl/ip_cores/wr-cores"] [submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
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SIM =../testbench/include SIM =../testbench/include
DOC =../../doc/manual
SW =../../software/include/hw SW =../../software/include/hw
SOURCES = $(wildcard *.cheby) SOURCES = $(wildcard *.cheby)
...@@ -13,6 +12,5 @@ $(TARGETS): %.vhd : %.cheby ...@@ -13,6 +12,5 @@ $(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m" @echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@ @cheby -i $< --gen-hdl=$@
@cheby -i $< \ @cheby -i $< \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \ --gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h) --gen-c=$(SW)/$(@:.vhd=.h)
memory-map: memory-map:
bus: wb-32-be bus: wb-32-be
name: fmc_adc_100ms_csr name: fmc_adc_100ms_csr
size: 0x200
description: FMC ADC 100MS/s core registers description: FMC ADC 100MS/s core registers
comment: | comment: |
Wishbone slave for FMC ADC 100MS/s core Wishbone slave for FMC ADC 100MS/s core
......
memory-map:
name: fmc_adc_mezzanine_mmap
bus: wb-32-be
description: FMC-ADC-100M mezzanine memory map
size: 0x2000
x-hdl:
busgroup: True
children:
- submap:
name: fmc_adc_100m_csr
address: 0x1000
description: FMC ADC 100M CSR
filename: fmc_adc_100Ms_csr.cheby
- submap:
name: fmc_adc_eic
address: 0x1500
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
description: FMC ADC Embedded Interrupt Controller
- submap:
name: si570_i2c_master
address: 0x1600
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
description: Si570 control I2C master
- submap:
name: ds18b20_onewire_master
address: 0x1700
description: DS18B20 OneWire master
filename: ../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
- submap:
name: fmc_spi_master
address: 0x1800
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
description: Mezzanine SPI master (ADC control + DAC offsets)
- submap:
name: timetag_core
address: 0x1900
description: Timetag Core
filename: timetag_core_regs.cheby
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memory-map:
name: spec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x6000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
address: 0x2000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: fmc_adc_mezzanine
address: 0x4000
description: FMC ADC Mezzanine
filename: fmc_adc_mezzanine_mmap.cheby
memory-map:
name: svec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x8000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
address: 0x2000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: fmc1_adc_mezzanine
address: 0x4000
description: FMC ADC Mezzanine slot 1
filename: fmc_adc_mezzanine_mmap.cheby
- submap:
name: fmc2_adc_mezzanine
address: 0x6000
description: FMC ADC Mezzanine slot 2
filename: fmc_adc_mezzanine_mmap.cheby
...@@ -2,6 +2,7 @@ memory-map: ...@@ -2,6 +2,7 @@ memory-map:
bus: wb-32-be bus: wb-32-be
name: timetag_core_regs name: timetag_core_regs
description: Time-tagging core registers description: Time-tagging core registers
size: 0x80
comment: | comment: |
Wishbone slave for registers related to time-tagging core Wishbone slave for registers related to time-tagging core
x-hdl: x-hdl:
......
Subproject commit bb5b8f75e6f85335b43fef320375404686a74008 Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
Subproject commit eaacde903ef842af456c867947a0f1005f8bb4f3 Subproject commit 75d51c0b92015b48b176374f9a387b2d25fa8198
Subproject commit 72adf76dab9a6fc33fbff7c86d786c31e175a46a Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
Subproject commit 4feaba679fc13458a35066c9a5bfe9b31cb853cd
Subproject commit ce6b58a38c12da91494dafc2a77cce6f16c0762f
Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152 Subproject commit 6abee52c1b5f3c2a40e202eb9f5890c05e0d7f66
...@@ -3,11 +3,12 @@ files = [ ...@@ -3,11 +3,12 @@ files = [
"fmc_adc_mezzanine_pkg.vhd", "fmc_adc_mezzanine_pkg.vhd",
"fmc_adc_100Ms_core.vhd", "fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd", "fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_aux_trigin.vhd",
"fmc_adc_aux_trigout.vhd",
"fmc_adc_eic.vhd", "fmc_adc_eic.vhd",
"offset_gain_s.vhd", "offset_gain_s.vhd",
"timetag_core_regs.vhd",
"timetag_core.vhd", "timetag_core.vhd",
"../cheby/fmc_adc_mezzanine_mmap.vhd",
"../cheby/fmc_adc_100Ms_csr.vhd",
"../cheby/fmc_adc_aux_trigin.vhd",
"../cheby/fmc_adc_aux_trigout.vhd",
"../cheby/timetag_core_regs.vhd",
] ]
...@@ -350,7 +350,7 @@ begin ...@@ -350,7 +350,7 @@ begin
cmp_csr_wb_slave_adapter : wb_slave_adapter cmp_csr_wb_slave_adapter : wb_slave_adapter
generic map ( generic map (
g_master_use_struct => TRUE, g_master_use_struct => TRUE,
g_master_mode => CLASSIC, g_master_mode => PIPELINED,
g_master_granularity => BYTE, g_master_granularity => BYTE,
g_slave_use_struct => TRUE, g_slave_use_struct => TRUE,
g_slave_mode => g_WB_CSR_MODE, g_slave_mode => g_WB_CSR_MODE,
......
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...@@ -124,9 +124,6 @@ package fmc_adc_mezzanine_pkg is ...@@ -124,9 +124,6 @@ package fmc_adc_mezzanine_pkg is
mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID) mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i : in std_logic; -- WR link status bit wr_tm_link_up_i : in std_logic; -- WR link status bit
wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit wr_tm_time_valid_i : in std_logic; -- WR timecode valid status bit
wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds wr_tm_tai_i : in std_logic_vector(39 downto 0); -- WR timecode seconds
......
...@@ -9,29 +9,30 @@ syn_top = "spec_ref_fmc_adc_100Ms" ...@@ -9,29 +9,30 @@ syn_top = "spec_ref_fmc_adc_100Ms"
syn_project = syn_top + "_wr.xise" syn_project = syn_top + "_wr.xise"
syn_tool = "ise" syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
files = [ files = [
syn_top + "_wr.ucf", syn_top + "_wr.ucf",
"buildinfo_pkg.vhd",
] ]
modules = { modules = {
"local" : [ "local" : [
"../../top/spec_ref_design" "../../top/spec_ref_design"
], ],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
],
} }
fetchto="../../ip_cores" # Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank3_64b_32b" ] syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd = ( spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \ ctrls = ["bank3_64b_32b" ]
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
...@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On" ...@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal" #xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal" #xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project set "Keep Hierarchy" "Yes"
xilinx::project save xilinx::project save
xilinx::project close xilinx::project close
...@@ -9,29 +9,30 @@ syn_top = "svec_ref_fmc_adc_100Ms" ...@@ -9,29 +9,30 @@ syn_top = "svec_ref_fmc_adc_100Ms"
syn_project = syn_top + "_wr.xise" syn_project = syn_top + "_wr.xise"
syn_tool = "ise" syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
files = [ files = [
syn_top + "_wr.ucf", syn_top + "_wr.ucf",
"buildinfo_pkg.vhd",
] ]
modules = { modules = {
"local" : [ "local" : [
"../../top/svec_ref_design" "../../top/svec_ref_design"
], ],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
],
} }
fetchto="../../ip_cores" # Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank4_64b_32b", "bank5_64b_32b"] syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd = ( svec_base_ucf = ['wr', 'ddr4', 'ddr5', 'led', 'gpio']
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \ ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
...@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On" ...@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal" #xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal" #xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
#xilinx::project set "Keep Hierarchy" "Yes"
xilinx::project save xilinx::project save
xilinx::project close xilinx::project close
...@@ -92,8 +92,6 @@ module main; ...@@ -92,8 +92,6 @@ module main;
.si570_scl_b (), .si570_scl_b (),
.si570_sda_b (), .si570_sda_b (),
.mezz_one_wire_b (), .mezz_one_wire_b (),
.sys_scl_b (),
.sys_sda_b (),
.wr_tm_link_up_i (), .wr_tm_link_up_i (),
.wr_tm_time_valid_i (), .wr_tm_time_valid_i (),
.wr_tm_tai_i (), .wr_tm_tai_i (),
...@@ -180,12 +178,6 @@ module main; ...@@ -180,12 +178,6 @@ module main;
#1us; #1us;
// Check SDB
expected = 'h5344422d;
acc.read(`SDB_ADDR, val);
if (val != expected)
$fatal (1, "Unable to detect SDB header at offset 0x%8x.", `SDB_ADDR);
// Check status after reset // Check status after reset
expected = 'h19; expected = 'h19;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val); acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
......
vsim -quiet -L unisim work.main vsim -quiet -L unisim work.main -voptargs=+acc
set StdArithNoWarnings 1 set StdArithNoWarnings 1
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
......
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