hdl: prevent FSM from going through the pre-trigger state, if there are no…

hdl: prevent FSM from going through the pre-trigger state, if there are no pre-trigger samples to be acquired. Fixes the error in the samples counter register when pre_trigger samples was zero.

hdl: prevent FSM from going through the pre-trigger state, if there are no…
hdl: prevent FSM from going through the pre-trigger state, if there are no pre-trigger samples to be acquired. Fixes the error in the samples counter register when pre_trigger samples was zero.
4eaf8f24 · Dimitris Lampridis · f8384514 · 4eaf8f24
Commit 4eaf8f24 authored Apr 13, 2016 by Dimitris Lampridis
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Showing with 10 additions and 2 deletions

fmc_adc_100Ms_core.vhd hdl/adc/rtl/fmc_adc_100Ms_core.vhd +10 -2

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--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
@@ -1212,8 +1212,12 @@ begin

        when IDLE =>
          if acq_start = '1' and acq_config_ok = '1' then
+            if unsigned(pre_trig_value) = to_unsigned(0, pre_trig_value'length) then
+              acq_fsm_current_state <= WAIT_TRIG;
+            else
              acq_fsm_current_state <= PRE_TRIG;
            end if;
+          end if;

        when PRE_TRIG =>
          if acq_stop = '1' then
@@ -1249,10 +1253,14 @@ begin
          else
            if shots_done = '1' then
              acq_fsm_current_state <= IDLE;
+            else
+              if unsigned(pre_trig_value) = to_unsigned(0, pre_trig_value'length) then
+                acq_fsm_current_state <= WAIT_TRIG;
              else
                acq_fsm_current_state <= PRE_TRIG;
              end if;
            end if;
+          end if;

        when others =>
          acq_fsm_current_state <= IDLE;