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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
540f3fe9
Commit
540f3fe9
authored
Oct 31, 2018
by
Dimitris Lampridis
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hdl: refine timing constraints
parent
48154a0a
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5 changed files
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82 additions
and
12 deletions
+82
-12
fmc_adc_100Ms_core.vhd
hdl/rtl/fmc_adc_100Ms_core.vhd
+3
-0
spec_ref_fmc_adc_100Ms_wr.ucf
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
+34
-5
svec_ref_fmc_adc_100Ms_wr.ucf
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
+33
-7
spec_ref_fmc_adc_100Ms.vhd
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+7
-0
svec_ref_fmc_adc_100Ms.vhd
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
+5
-0
No files found.
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @
540f3fe9
...
...
@@ -200,6 +200,9 @@ architecture rtl of fmc_adc_100Ms_core is
signal
fs_freq_t
:
std_logic_vector
(
31
downto
0
);
signal
fs_freq_valid
:
std_logic
;
attribute
keep
:
string
;
attribute
keep
of
fs_clk
:
signal
is
"TRUE"
;
-- SerDes
signal
serdes_in_p
:
std_logic_vector
(
8
downto
0
);
signal
serdes_in_n
:
std_logic_vector
(
8
downto
0
);
...
...
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @
540f3fe9
...
...
@@ -573,7 +573,7 @@ NET "DDR3_UDQS_N" IN_TERM = NONE;
#===============================================================================
# Timing constraints
# Timing constraints
and exceptions
#===============================================================================
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
...
...
@@ -600,10 +600,39 @@ INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#NET "ddr_clk_buf" TNM_NET = ddr_clk;
#NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
#TIMESPEC TS_sys_to_drr_cross = FROM "sys_clk_62_5" TO "ddr_clk" 16ns DATAPATHONLY;
# relax all paths through syncrhonisers:
# 1. define groups for each clock domain
# 2. define group for all sync chains
# 3. create sync chain groups that exclude one clock domain each
# 4. relax path from each clock domain to respective sync chain group
NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
NET "sys_clk_125" TNM_NET = sys_clk_125;
NET "clk_dmtd" TNM_NET = clk_dmtd;
NET "ddr_clk" TNM_NET = ddr_clk;
NET "clk_125m_pllref" TNM_NET = clk_125m_pllref;
NET "phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
NET "cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMEGRP "synchronizers" = "sync_ffs" "sync_reg";
TIMEGRP "sys_62_5_sync" = "synchronizers" EXCEPT "sys_clk_62_5";
TIMEGRP "sys_125_sync" = "synchronizers" EXCEPT "sys_clk_125";
TIMEGRP "dmtd_sync" = "synchronizers" EXCEPT "clk_dmtd";
TIMEGRP "ddr_sync" = "synchronizers" EXCEPT "ddr_clk";
TIMEGRP "ref_sync" = "synchronizers" EXCEPT "clk_125m_pllref";
TIMEGRP "phy_sync" = "synchronizers" EXCEPT "phy_rx_rbclk";
TIMEGRP "adc_sync" = "synchronizers" EXCEPT "fs_clk";
TIMESPEC TS_sys_62_5_sync = FROM sys_clk_62_5 TO "sys_62_5_sync" 20ns DATAPATHONLY;
TIMESPEC TS_sys_125_sync = FROM sys_clk_125 TO "sys_125_sync" 20ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync = FROM clk_dmtd TO "dmtd_sync" 20ns DATAPATHONLY;
TIMESPEC TS_ddr_sync = FROM ddr_clk TO "ddr_sync" 20ns DATAPATHONLY;
TIMESPEC TS_ref_sync = FROM clk_125m_pllref TO "ref_sync" 20ns DATAPATHONLY;
TIMESPEC TS_phy_sync = FROM phy_rx_rbclk TO "phy_sync" 20ns DATAPATHONLY;
TIMESPEC TS_adc_sync = FROM fs_clk TO "adc_sync" 20ns DATAPATHONLY;
#===============================================================================
# False Path
...
...
hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
View file @
540f3fe9
...
...
@@ -957,13 +957,39 @@ INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# external 10MHz clock input
NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
NET "clk_ddr_333m_buf" TNM_NET = clk_ddr_333m;
NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
TIMESPEC TS_crossdomain_01 = FROM "clk_sys_62m5" TO "clk_ddr_333m" 4ns DATAPATHONLY;
# relax all paths through syncrhonisers:
# 1. define groups for each clock domain
# 2. define group for all sync chains
# 3. create sync chain groups that exclude one clock domain each
# 4. relax path from each clock domain to respective sync chain group
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ddr_333m" TNM_NET = ddr_clk;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
NET "cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMEGRP "synchronizers" = "sync_ffs" "sync_reg";
TIMEGRP "sys_62_5_sync" = "synchronizers" EXCEPT "sys_clk_62_5";
TIMEGRP "dmtd_sync" = "synchronizers" EXCEPT "clk_dmtd";
TIMEGRP "ddr_sync" = "synchronizers" EXCEPT "ddr_clk";
TIMEGRP "ref_sync" = "synchronizers" EXCEPT "clk_125m_pllref";
TIMEGRP "phy_sync" = "synchronizers" EXCEPT "phy_rx_rbclk";
TIMEGRP "adc0_sync" = "synchronizers" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync" = "synchronizers" EXCEPT "fs1_clk";
TIMESPEC TS_sys_62_5_sync = FROM sys_clk_62_5 TO "sys_62_5_sync" 20ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync = FROM clk_dmtd TO "dmtd_sync" 20ns DATAPATHONLY;
TIMESPEC TS_ddr_sync = FROM ddr_clk TO "ddr_sync" 20ns DATAPATHONLY;
TIMESPEC TS_ref_sync = FROM clk_125m_pllref TO "ref_sync" 20ns DATAPATHONLY;
TIMESPEC TS_phy_sync = FROM phy_rx_rbclk TO "phy_sync" 20ns DATAPATHONLY;
TIMESPEC TS_adc0_sync = FROM fs0_clk TO "adc0_sync" 20ns DATAPATHONLY;
TIMESPEC TS_adc1_sync = FROM fs1_clk TO "adc1_sync" 20ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
...
...
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @
540f3fe9
...
...
@@ -352,6 +352,13 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
signal
ddr_clk
:
std_logic
;
signal
ddr_clk_buf
:
std_logic
;
attribute
keep
:
string
;
attribute
keep
of
sys_clk_62_5
:
signal
is
"TRUE"
;
attribute
keep
of
sys_clk_125
:
signal
is
"TRUE"
;
attribute
keep
of
clk_dmtd
:
signal
is
"TRUE"
;
attribute
keep
of
ddr_clk
:
signal
is
"TRUE"
;
attribute
keep
of
clk_125m_pllref
:
signal
is
"TRUE"
;
-- Reset
signal
powerup_arst_n
:
std_logic
:
=
'0'
;
signal
powerup_clk_in
:
std_logic_vector
(
2
downto
0
);
...
...
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @
540f3fe9
...
...
@@ -453,6 +453,11 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
signal
ddr0_rst_n
:
std_logic
;
signal
ddr1_rst_n
:
std_logic
;
attribute
keep
:
string
;
attribute
keep
of
clk_sys_62m5
:
signal
is
"TRUE"
;
attribute
keep
of
clk_ref_125m
:
signal
is
"TRUE"
;
attribute
keep
of
clk_ddr_333m
:
signal
is
"TRUE"
;
-- VME
signal
vme_data_b_out
:
std_logic_vector
(
31
downto
0
);
signal
vme_addr_b_out
:
std_logic_vector
(
31
downto
1
);
...
...
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